Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	125826498	0	0	0
ctrl_en_input_filter_rd_A	125826498	63671	0	0
intr_ctrl_en_falling_rd_A	125826498	63383	0	0
intr_ctrl_en_lvlhigh_rd_A	125826498	62138	0	0
intr_ctrl_en_lvllow_rd_A	125826498	63248	0	0
intr_ctrl_en_rising_rd_A	125826498	62802	0	0
intr_enable_rd_A	125826498	63037	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125826498	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125826498	63671	0	0
T1	6573	3	0	0
T2	0	6880	0	0
T3	0	736	0	0
T4	0	5137	0	0
T5	0	8	0	0
T6	0	2070	0	0
T7	0	197	0	0
T8	0	243	0	0
T9	0	250	0	0
T10	0	2114	0	0
T11	4171	0	0	0
T12	16823	0	0	0
T13	2641	0	0	0
T14	8043	0	0	0
T15	9146	0	0	0
T16	58101	0	0	0
T17	1748	0	0	0
T18	5570	0	0	0
T19	7643	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125826498	63383	0	0
T2	187023	7089	0	0
T3	0	772	0	0
T4	0	5007	0	0
T6	0	2173	0	0
T7	0	153	0	0
T8	0	156	0	0
T9	0	211	0	0
T10	0	1819	0	0
T20	0	6	0	0
T21	0	3346	0	0
T22	125121	0	0	0
T23	5635	0	0	0
T24	4459	0	0	0
T25	862	0	0	0
T26	27597	0	0	0
T27	6954	0	0	0
T28	3255	0	0	0
T29	6618	0	0	0
T30	2221	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125826498	62138	0	0
T2	187023	7059	0	0
T3	0	805	0	0
T4	0	5118	0	0
T5	0	8	0	0
T6	0	2160	0	0
T7	0	155	0	0
T8	0	198	0	0
T9	0	265	0	0
T10	0	1732	0	0
T20	0	12	0	0
T22	125121	0	0	0
T23	5635	0	0	0
T24	4459	0	0	0
T25	862	0	0	0
T26	27597	0	0	0
T27	6954	0	0	0
T28	3255	0	0	0
T29	6618	0	0	0
T30	2221	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125826498	63248	0	0
T1	6573	1	0	0
T2	0	7026	0	0
T3	0	713	0	0
T4	0	5119	0	0
T5	0	9	0	0
T6	0	1937	0	0
T7	0	150	0	0
T8	0	181	0	0
T9	0	237	0	0
T10	0	2013	0	0
T11	4171	0	0	0
T12	16823	0	0	0
T13	2641	0	0	0
T14	8043	0	0	0
T15	9146	0	0	0
T16	58101	0	0	0
T17	1748	0	0	0
T18	5570	0	0	0
T19	7643	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125826498	62802	0	0
T2	187023	7143	0	0
T3	0	750	0	0
T4	0	4919	0	0
T5	0	1	0	0
T6	0	2184	0	0
T7	0	160	0	0
T8	0	188	0	0
T9	0	249	0	0
T10	0	1970	0	0
T21	0	3282	0	0
T22	125121	0	0	0
T23	5635	0	0	0
T24	4459	0	0	0
T25	862	0	0	0
T26	27597	0	0	0
T27	6954	0	0	0
T28	3255	0	0	0
T29	6618	0	0	0
T30	2221	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125826498	63037	0	0
T1	6573	2	0	0
T2	0	7217	0	0
T3	0	825	0	0
T4	0	5083	0	0
T6	0	2189	0	0
T7	0	162	0	0
T8	0	185	0	0
T9	0	164	0	0
T10	0	2037	0	0
T11	4171	0	0	0
T12	16823	0	0	0
T13	2641	0	0	0
T14	8043	0	0	0
T15	9146	0	0	0
T16	58101	0	0	0
T17	1748	0	0	0
T18	5570	0	0	0
T19	7643	0	0	0
T21	0	3114	0	0