Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3266312	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

14476953

1

T20

122

T21

118

T22

1691

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7124881	1			T20	37		T21	11		T22	2638
values[0x0]	5220356	1			T20	51		T21	58		T22	198
values[0x1]	5398028	1			T20	49		T21	55		T22	181

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2511744	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

15231521

1

T20

124

T21

119

T22

1966

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	73322	1			T22	14		T24	5		T27	1
valid_sources[0x01]	69429	1			T22	13		T23	3		T27	3
valid_sources[0x02]	63106	1			T22	6		T26	1		T27	3
valid_sources[0x03]	68170	1			T21	1		T22	5		T23	3
valid_sources[0x04]	68585	1			T22	14		T28	2		T29	3
valid_sources[0x05]	64006	1			T22	10		T23	2		T25	1
valid_sources[0x06]	66460	1			T22	11		T23	1		T26	2
valid_sources[0x07]	66623	1			T22	17		T26	1		T28	3
valid_sources[0x08]	71311	1			T22	14		T23	2		T24	3
valid_sources[0x09]	65920	1			T21	1		T22	11		T29	2
valid_sources[0x0a]	63865	1			T22	14		T24	2		T25	2
valid_sources[0x0b]	111460	1			T22	17		T23	4		T24	6
valid_sources[0x0c]	62547	1			T22	10		T23	2		T26	1
valid_sources[0x0d]	68202	1			T21	1		T22	16		T23	4
valid_sources[0x0e]	69357	1			T22	10		T24	2		T27	1
valid_sources[0x0f]	64424	1			T22	14		T25	1		T26	2
valid_sources[0x10]	64446	1			T22	11		T23	3		T24	2
valid_sources[0x11]	64460	1			T22	13		T23	2		T24	13
valid_sources[0x12]	65733	1			T21	1		T22	10		T23	3
valid_sources[0x13]	69264	1			T22	7		T23	6		T24	4
valid_sources[0x14]	66478	1			T22	6		T23	2		T24	1
valid_sources[0x15]	65297	1			T22	8		T24	12		T25	1
valid_sources[0x16]	63286	1			T22	9		T23	3		T26	1
valid_sources[0x17]	68751	1			T21	2		T22	7		T25	2
valid_sources[0x18]	66311	1			T21	1		T22	12		T24	1
valid_sources[0x19]	66393	1			T21	3		T22	17		T24	2
valid_sources[0x1a]	67135	1			T22	7		T23	3		T26	1
valid_sources[0x1b]	64770	1			T21	1		T22	11		T23	3
valid_sources[0x1c]	65308	1			T22	11		T23	1		T24	3
valid_sources[0x1d]	63342	1			T22	16		T24	4		T25	3
valid_sources[0x1e]	68522	1			T22	8		T23	1		T26	1
valid_sources[0x1f]	61211	1			T22	7		T24	2		T27	4
valid_sources[0x20]	70651	1			T21	1		T22	12		T23	1
valid_sources[0x21]	65868	1			T22	14		T23	1		T27	1
valid_sources[0x22]	65723	1			T22	7		T23	2		T26	1
valid_sources[0x23]	68514	1			T21	1		T22	7		T23	1
valid_sources[0x24]	64067	1			T22	18		T23	5		T26	1
valid_sources[0x25]	64828	1			T21	1		T22	16		T23	3
valid_sources[0x26]	67507	1			T21	2		T22	11		T23	1
valid_sources[0x27]	64047	1			T22	20		T23	1		T26	1
valid_sources[0x28]	64818	1			T22	10		T23	4		T25	2
valid_sources[0x29]	65567	1			T21	1		T22	13		T24	7
valid_sources[0x2a]	63816	1			T22	17		T23	1		T24	1
valid_sources[0x2b]	67035	1			T21	1		T22	11		T23	6
valid_sources[0x2c]	63453	1			T21	3		T22	8		T24	2
valid_sources[0x2d]	63662	1			T22	12		T23	4		T25	2
valid_sources[0x2e]	71811	1			T22	10		T23	1		T24	2
valid_sources[0x2f]	63671	1			T22	16		T24	8		T27	2
valid_sources[0x30]	63387	1			T22	8		T23	3		T25	1
valid_sources[0x31]	65959	1			T21	1		T22	5		T23	2
valid_sources[0x32]	71913	1			T21	2		T22	9		T23	2
valid_sources[0x33]	63578	1			T21	1		T22	17		T23	4
valid_sources[0x34]	169770	1			T22	14		T23	5		T24	2
valid_sources[0x35]	77496	1			T22	9		T24	7		T25	1
valid_sources[0x36]	194298	1			T22	6		T24	5		T27	2
valid_sources[0x37]	68401	1			T22	15		T23	2		T28	14
valid_sources[0x38]	65776	1			T22	13		T23	1		T29	4
valid_sources[0x39]	62958	1			T22	13		T23	2		T26	1
valid_sources[0x3a]	67937	1			T22	14		T23	2		T26	1
valid_sources[0x3b]	64656	1			T22	15		T23	3		T25	1
valid_sources[0x3c]	64133	1			T22	13		T25	1		T27	2
valid_sources[0x3d]	68653	1			T22	7		T23	2		T24	1
valid_sources[0x3e]	70956	1			T21	1		T22	12		T23	1
valid_sources[0x3f]	66513	1			T22	7		T23	7		T1	489
valid_sources[0x40]	67345	1			T21	1		T22	13		T23	4
valid_sources[0x41]	67431	1			T22	13		T23	2		T25	1
valid_sources[0x42]	62900	1			T22	12		T23	1		T24	5
valid_sources[0x43]	65102	1			T22	19		T23	1		T24	12
valid_sources[0x44]	67546	1			T22	10		T23	1		T24	7
valid_sources[0x45]	64791	1			T21	2		T22	17		T23	2
valid_sources[0x46]	64825	1			T21	2		T22	17		T23	1
valid_sources[0x47]	70807	1			T22	16		T25	3		T27	2
valid_sources[0x48]	62226	1			T21	1		T22	13		T23	2
valid_sources[0x49]	70139	1			T22	16		T23	1		T24	5
valid_sources[0x4a]	64926	1			T21	1		T22	9		T26	1
valid_sources[0x4b]	71432	1			T21	2		T22	7		T25	1
valid_sources[0x4c]	68187	1			T22	9		T27	3		T28	2
valid_sources[0x4d]	66460	1			T22	14		T23	3		T27	3
valid_sources[0x4e]	63463	1			T21	1		T22	9		T26	1
valid_sources[0x4f]	63711	1			T21	1		T22	8		T23	2
valid_sources[0x50]	68601	1			T22	10		T23	1		T24	1
valid_sources[0x51]	69397	1			T21	1		T22	10		T23	2
valid_sources[0x52]	64756	1			T22	11		T23	3		T27	1
valid_sources[0x53]	63456	1			T22	8		T27	1		T28	4
valid_sources[0x54]	63721	1			T22	13		T23	3		T27	1
valid_sources[0x55]	67861	1			T22	13		T23	2		T24	3
valid_sources[0x56]	70723	1			T22	10		T25	1		T27	3
valid_sources[0x57]	66454	1			T22	11		T24	7		T25	1
valid_sources[0x58]	70621	1			T22	9		T23	3		T24	3
valid_sources[0x59]	71035	1			T21	1		T22	12		T23	2
valid_sources[0x5a]	67485	1			T21	2		T22	19		T26	1
valid_sources[0x5b]	72331	1			T21	1		T22	7		T23	2
valid_sources[0x5c]	67663	1			T22	9		T25	3		T26	1
valid_sources[0x5d]	66347	1			T21	1		T22	8		T23	1
valid_sources[0x5e]	67246	1			T21	2		T22	12		T23	1
valid_sources[0x5f]	66147	1			T22	15		T23	3		T25	1
valid_sources[0x60]	62994	1			T22	6		T23	4		T25	1
valid_sources[0x61]	62767	1			T21	1		T22	4		T23	4
valid_sources[0x62]	65714	1			T21	3		T22	17		T29	8
valid_sources[0x63]	63022	1			T22	19		T23	8		T27	7
valid_sources[0x64]	69445	1			T22	12		T25	2		T28	2
valid_sources[0x65]	61363	1			T21	1		T22	10		T25	1
valid_sources[0x66]	67306	1			T21	1		T22	16		T27	4
valid_sources[0x67]	70492	1			T21	1		T22	8		T26	1
valid_sources[0x68]	62423	1			T22	13		T23	2		T25	1
valid_sources[0x69]	62543	1			T22	9		T23	1		T26	4
valid_sources[0x6a]	66109	1			T22	12		T23	3		T24	2
valid_sources[0x6b]	66816	1			T21	1		T22	13		T24	1
valid_sources[0x6c]	64819	1			T21	1		T22	15		T24	3
valid_sources[0x6d]	109264	1			T21	1		T22	8		T23	1
valid_sources[0x6e]	62538	1			T21	1		T22	12		T26	1
valid_sources[0x6f]	64896	1			T22	11		T23	1		T26	1
valid_sources[0x70]	62631	1			T22	16		T23	8		T24	7
valid_sources[0x71]	67550	1			T21	3		T22	9		T23	4
valid_sources[0x72]	61853	1			T22	19		T25	1		T26	1
valid_sources[0x73]	69839	1			T22	10		T23	1		T27	2
valid_sources[0x74]	68090	1			T21	1		T22	13		T23	2
valid_sources[0x75]	65706	1			T22	10		T24	1		T25	1
valid_sources[0x76]	64728	1			T22	12		T23	1		T24	6
valid_sources[0x77]	63084	1			T22	15		T23	2		T24	8
valid_sources[0x78]	67241	1			T22	13		T23	1		T24	1
valid_sources[0x79]	68424	1			T21	1		T22	7		T24	9
valid_sources[0x7a]	64950	1			T22	15		T23	3		T24	3
valid_sources[0x7b]	65101	1			T22	8		T23	2		T26	1
valid_sources[0x7c]	65597	1			T22	12		T23	2		T26	2
valid_sources[0x7d]	65446	1			T22	8		T24	5		T25	1
valid_sources[0x7e]	61591	1			T22	17		T23	2		T27	1
valid_sources[0x7f]	65764	1			T21	1		T22	13		T23	2
valid_sources[0x80]	63431	1			T22	14		T23	4		T25	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4075209

1

T20

22

T21

5

T22

1312

values[0x0]

all_enables

biggest_size

5202076

1

T20

51

T21

58

T22

198

values[0x1]

all_enables

biggest_size

5199668

1

T20

49

T21

55

T22

181