Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	147126975	0	0	0
ctrl_en_input_filter_rd_A	147126975	82153	0	0
intr_ctrl_en_falling_rd_A	147126975	83328	0	0
intr_ctrl_en_lvlhigh_rd_A	147126975	81237	0	0
intr_ctrl_en_lvllow_rd_A	147126975	82661	0	0
intr_ctrl_en_rising_rd_A	147126975	82703	0	0
intr_enable_rd_A	147126975	80442	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147126975	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147126975	82153	0	0
T1	183286	7097	0	0
T2	0	4302	0	0
T3	0	3066	0	0
T4	0	5923	0	0
T5	0	100	0	0
T6	0	5062	0	0
T7	0	162	0	0
T8	0	743	0	0
T9	0	2185	0	0
T10	0	205	0	0
T11	1163	0	0	0
T12	8530	0	0	0
T13	4302	0	0	0
T14	4410	0	0	0
T15	1826	0	0	0
T16	576749	0	0	0
T17	3095	0	0	0
T18	3228	0	0	0
T19	64765	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147126975	83328	0	0
T1	183286	6383	0	0
T2	0	4206	0	0
T3	0	2975	0	0
T4	0	6051	0	0
T5	0	72	0	0
T6	0	5164	0	0
T7	0	205	0	0
T8	0	730	0	0
T9	0	1860	0	0
T10	0	206	0	0
T11	1163	0	0	0
T12	8530	0	0	0
T13	4302	0	0	0
T14	4410	0	0	0
T15	1826	0	0	0
T16	576749	0	0	0
T17	3095	0	0	0
T18	3228	0	0	0
T19	64765	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147126975	81237	0	0
T1	183286	6423	0	0
T2	0	4129	0	0
T3	0	3046	0	0
T4	0	5814	0	0
T5	0	95	0	0
T6	0	4924	0	0
T7	0	198	0	0
T8	0	847	0	0
T9	0	1940	0	0
T10	0	273	0	0
T11	1163	0	0	0
T12	8530	0	0	0
T13	4302	0	0	0
T14	4410	0	0	0
T15	1826	0	0	0
T16	576749	0	0	0
T17	3095	0	0	0
T18	3228	0	0	0
T19	64765	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147126975	82661	0	0
T1	183286	6195	0	0
T2	0	3997	0	0
T3	0	3392	0	0
T4	0	5576	0	0
T5	0	76	0	0
T6	0	5200	0	0
T7	0	184	0	0
T8	0	888	0	0
T9	0	2015	0	0
T10	0	280	0	0
T11	1163	0	0	0
T12	8530	0	0	0
T13	4302	0	0	0
T14	4410	0	0	0
T15	1826	0	0	0
T16	576749	0	0	0
T17	3095	0	0	0
T18	3228	0	0	0
T19	64765	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147126975	82703	0	0
T1	183286	6887	0	0
T2	0	4358	0	0
T3	0	3278	0	0
T4	0	5943	0	0
T5	0	65	0	0
T6	0	5149	0	0
T7	0	217	0	0
T8	0	692	0	0
T9	0	2038	0	0
T10	0	343	0	0
T11	1163	0	0	0
T12	8530	0	0	0
T13	4302	0	0	0
T14	4410	0	0	0
T15	1826	0	0	0
T16	576749	0	0	0
T17	3095	0	0	0
T18	3228	0	0	0
T19	64765	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147126975	80442	0	0
T1	183286	6515	0	0
T2	0	4207	0	0
T3	0	3143	0	0
T4	0	5939	0	0
T5	0	83	0	0
T6	0	5076	0	0
T7	0	187	0	0
T8	0	682	0	0
T9	0	2072	0	0
T10	0	226	0	0
T11	1163	0	0	0
T12	8530	0	0	0
T13	4302	0	0	0
T14	4410	0	0	0
T15	1826	0	0	0
T16	576749	0	0	0
T17	3095	0	0	0
T18	3228	0	0	0
T19	64765	0	0	0