Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 941
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T761 /workspace/coverage/cover_reg_top/48.gpio_intr_test.2158800698 Mar 31 12:30:34 PM PDT 24 Mar 31 12:30:35 PM PDT 24 44968213 ps
T762 /workspace/coverage/cover_reg_top/7.gpio_intr_test.966977514 Mar 31 12:30:26 PM PDT 24 Mar 31 12:30:27 PM PDT 24 39582345 ps
T78 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.3788427517 Mar 31 12:30:22 PM PDT 24 Mar 31 12:30:23 PM PDT 24 32315998 ps
T763 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.695411048 Mar 31 12:30:24 PM PDT 24 Mar 31 12:30:24 PM PDT 24 31696266 ps
T764 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.1210483246 Mar 31 12:30:32 PM PDT 24 Mar 31 12:30:33 PM PDT 24 34044885 ps
T765 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3539703278 Mar 31 12:31:25 PM PDT 24 Mar 31 12:31:25 PM PDT 24 55340659 ps
T79 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.797910086 Mar 31 12:30:09 PM PDT 24 Mar 31 12:30:10 PM PDT 24 13180188 ps
T766 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1285671268 Mar 31 12:30:30 PM PDT 24 Mar 31 12:30:31 PM PDT 24 56613481 ps
T767 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2386073568 Mar 31 12:30:31 PM PDT 24 Mar 31 12:30:33 PM PDT 24 1005950060 ps
T768 /workspace/coverage/cover_reg_top/27.gpio_intr_test.72240796 Mar 31 12:30:34 PM PDT 24 Mar 31 12:30:35 PM PDT 24 10883887 ps
T769 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.74198131 Mar 31 12:30:33 PM PDT 24 Mar 31 12:30:37 PM PDT 24 110689573 ps
T770 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1307298356 Mar 31 12:30:28 PM PDT 24 Mar 31 12:30:30 PM PDT 24 23316723 ps
T80 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3512574286 Mar 31 12:30:07 PM PDT 24 Mar 31 12:30:08 PM PDT 24 23352016 ps
T771 /workspace/coverage/cover_reg_top/9.gpio_intr_test.1448748379 Mar 31 12:30:26 PM PDT 24 Mar 31 12:30:27 PM PDT 24 10590682 ps
T772 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2290476689 Mar 31 12:30:11 PM PDT 24 Mar 31 12:30:12 PM PDT 24 20748259 ps
T44 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2273385325 Mar 31 12:31:20 PM PDT 24 Mar 31 12:31:22 PM PDT 24 77996554 ps
T773 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3974354854 Mar 31 12:31:23 PM PDT 24 Mar 31 12:31:26 PM PDT 24 202679554 ps
T774 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1423412619 Mar 31 12:30:32 PM PDT 24 Mar 31 12:30:33 PM PDT 24 40920557 ps
T775 /workspace/coverage/cover_reg_top/22.gpio_intr_test.2835109535 Mar 31 12:30:32 PM PDT 24 Mar 31 12:30:33 PM PDT 24 15892211 ps
T776 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3117387376 Mar 31 12:30:19 PM PDT 24 Mar 31 12:30:22 PM PDT 24 97755528 ps
T777 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2232847990 Mar 31 12:29:59 PM PDT 24 Mar 31 12:30:03 PM PDT 24 637839882 ps
T778 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1556941060 Mar 31 12:30:26 PM PDT 24 Mar 31 12:30:27 PM PDT 24 71118245 ps
T779 /workspace/coverage/cover_reg_top/24.gpio_intr_test.3244905710 Mar 31 12:30:28 PM PDT 24 Mar 31 12:30:30 PM PDT 24 41209723 ps
T780 /workspace/coverage/cover_reg_top/5.gpio_intr_test.1950904903 Mar 31 12:30:28 PM PDT 24 Mar 31 12:30:29 PM PDT 24 48299979 ps
T84 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2857798519 Mar 31 12:30:25 PM PDT 24 Mar 31 12:30:26 PM PDT 24 26534679 ps
T781 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1236899052 Mar 31 12:30:31 PM PDT 24 Mar 31 12:30:33 PM PDT 24 76051326 ps
T782 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2730005491 Mar 31 12:30:33 PM PDT 24 Mar 31 12:30:34 PM PDT 24 67578200 ps
T783 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3662533615 Mar 31 12:30:06 PM PDT 24 Mar 31 12:30:07 PM PDT 24 16455217 ps
T784 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.90773522 Mar 31 12:30:04 PM PDT 24 Mar 31 12:30:08 PM PDT 24 617642049 ps
T785 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.2630583746 Mar 31 12:30:24 PM PDT 24 Mar 31 12:30:24 PM PDT 24 30914946 ps
T786 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.3109833480 Mar 31 12:30:12 PM PDT 24 Mar 31 12:30:13 PM PDT 24 105503633 ps
T787 /workspace/coverage/cover_reg_top/15.gpio_intr_test.3471143287 Mar 31 12:30:31 PM PDT 24 Mar 31 12:30:32 PM PDT 24 42524236 ps
T788 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.904875982 Mar 31 12:30:28 PM PDT 24 Mar 31 12:30:29 PM PDT 24 118441053 ps
T789 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.642327511 Mar 31 12:30:23 PM PDT 24 Mar 31 12:30:24 PM PDT 24 43884497 ps
T790 /workspace/coverage/cover_reg_top/14.gpio_intr_test.3686342827 Mar 31 12:30:23 PM PDT 24 Mar 31 12:30:24 PM PDT 24 32942348 ps
T791 /workspace/coverage/cover_reg_top/8.gpio_intr_test.2419377761 Mar 31 12:30:04 PM PDT 24 Mar 31 12:30:05 PM PDT 24 41044341 ps
T792 /workspace/coverage/cover_reg_top/26.gpio_intr_test.2257270811 Mar 31 12:30:36 PM PDT 24 Mar 31 12:30:37 PM PDT 24 97360091 ps
T85 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1370797146 Mar 31 12:30:31 PM PDT 24 Mar 31 12:30:32 PM PDT 24 15047281 ps
T793 /workspace/coverage/cover_reg_top/40.gpio_intr_test.3895456898 Mar 31 12:30:32 PM PDT 24 Mar 31 12:30:33 PM PDT 24 72041692 ps
T794 /workspace/coverage/cover_reg_top/28.gpio_intr_test.1754184630 Mar 31 12:30:34 PM PDT 24 Mar 31 12:30:35 PM PDT 24 62092939 ps
T795 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.736875760 Mar 31 12:30:28 PM PDT 24 Mar 31 12:30:29 PM PDT 24 144829159 ps
T796 /workspace/coverage/cover_reg_top/47.gpio_intr_test.435056233 Mar 31 12:30:31 PM PDT 24 Mar 31 12:30:32 PM PDT 24 15669033 ps
T81 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1434142667 Mar 31 12:30:17 PM PDT 24 Mar 31 12:30:20 PM PDT 24 519778009 ps
T797 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.2325977515 Mar 31 12:30:18 PM PDT 24 Mar 31 12:30:20 PM PDT 24 149129986 ps
T798 /workspace/coverage/cover_reg_top/35.gpio_intr_test.3267879092 Mar 31 12:30:57 PM PDT 24 Mar 31 12:30:58 PM PDT 24 134597423 ps
T799 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.4265058652 Mar 31 12:30:04 PM PDT 24 Mar 31 12:30:05 PM PDT 24 214760067 ps
T800 /workspace/coverage/cover_reg_top/20.gpio_intr_test.3743534066 Mar 31 12:30:26 PM PDT 24 Mar 31 12:30:26 PM PDT 24 14543810 ps
T801 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3134634234 Mar 31 12:30:02 PM PDT 24 Mar 31 12:30:03 PM PDT 24 57946983 ps
T802 /workspace/coverage/cover_reg_top/29.gpio_intr_test.2814731857 Mar 31 12:30:36 PM PDT 24 Mar 31 12:30:37 PM PDT 24 159095174 ps
T803 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1697133835 Mar 31 12:30:44 PM PDT 24 Mar 31 12:30:46 PM PDT 24 119894447 ps
T804 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1083529587 Mar 31 12:30:09 PM PDT 24 Mar 31 12:30:10 PM PDT 24 70770898 ps
T805 /workspace/coverage/cover_reg_top/25.gpio_intr_test.2225680319 Mar 31 12:30:32 PM PDT 24 Mar 31 12:30:33 PM PDT 24 15960443 ps
T806 /workspace/coverage/cover_reg_top/49.gpio_intr_test.2301521119 Mar 31 12:30:32 PM PDT 24 Mar 31 12:30:33 PM PDT 24 15202693 ps
T807 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.12786908 Mar 31 12:29:59 PM PDT 24 Mar 31 12:30:01 PM PDT 24 95533142 ps
T808 /workspace/coverage/cover_reg_top/3.gpio_intr_test.1629824381 Mar 31 12:30:02 PM PDT 24 Mar 31 12:30:03 PM PDT 24 31308604 ps
T809 /workspace/coverage/cover_reg_top/39.gpio_intr_test.3836022738 Mar 31 12:30:33 PM PDT 24 Mar 31 12:30:34 PM PDT 24 36164645 ps
T810 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.470573986 Mar 31 12:30:19 PM PDT 24 Mar 31 12:30:20 PM PDT 24 41435612 ps
T811 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.4094525170 Mar 31 12:30:21 PM PDT 24 Mar 31 12:30:22 PM PDT 24 34028965 ps
T812 /workspace/coverage/cover_reg_top/19.gpio_intr_test.362346693 Mar 31 12:31:05 PM PDT 24 Mar 31 12:31:06 PM PDT 24 14092804 ps
T813 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2799125402 Mar 31 12:30:31 PM PDT 24 Mar 31 12:30:34 PM PDT 24 522723600 ps
T814 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.591943846 Mar 31 12:30:21 PM PDT 24 Mar 31 12:30:21 PM PDT 24 26078589 ps
T815 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3337136681 Mar 31 12:30:31 PM PDT 24 Mar 31 12:30:33 PM PDT 24 46603022 ps
T816 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1881457189 Mar 31 12:31:23 PM PDT 24 Mar 31 12:31:26 PM PDT 24 810488979 ps
T817 /workspace/coverage/cover_reg_top/33.gpio_intr_test.1948140667 Mar 31 12:30:33 PM PDT 24 Mar 31 12:30:34 PM PDT 24 13807911 ps
T818 /workspace/coverage/cover_reg_top/16.gpio_intr_test.2233009925 Mar 31 12:30:28 PM PDT 24 Mar 31 12:30:29 PM PDT 24 62275272 ps
T819 /workspace/coverage/cover_reg_top/38.gpio_intr_test.3179463988 Mar 31 12:30:37 PM PDT 24 Mar 31 12:30:38 PM PDT 24 31328767 ps
T820 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1905560968 Mar 31 12:30:23 PM PDT 24 Mar 31 12:30:24 PM PDT 24 16566506 ps
T821 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.2919910714 Mar 31 12:31:23 PM PDT 24 Mar 31 12:31:24 PM PDT 24 65332514 ps
T822 /workspace/coverage/cover_reg_top/6.gpio_intr_test.3788949167 Mar 31 12:30:19 PM PDT 24 Mar 31 12:30:21 PM PDT 24 53800435 ps
T823 /workspace/coverage/cover_reg_top/44.gpio_intr_test.2181987968 Mar 31 12:30:51 PM PDT 24 Mar 31 12:30:51 PM PDT 24 21289362 ps
T824 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1543553278 Mar 31 12:30:23 PM PDT 24 Mar 31 12:30:25 PM PDT 24 200349415 ps
T825 /workspace/coverage/cover_reg_top/13.gpio_intr_test.749250245 Mar 31 12:30:27 PM PDT 24 Mar 31 12:30:28 PM PDT 24 27549038 ps
T82 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2382045576 Mar 31 12:30:38 PM PDT 24 Mar 31 12:30:39 PM PDT 24 12520465 ps
T826 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1180211732 Mar 31 12:30:30 PM PDT 24 Mar 31 12:30:32 PM PDT 24 387691498 ps
T827 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3360454589 Mar 31 12:30:28 PM PDT 24 Mar 31 12:30:30 PM PDT 24 349878975 ps
T828 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1088611968 Mar 31 12:30:29 PM PDT 24 Mar 31 12:30:30 PM PDT 24 15924233 ps
T829 /workspace/coverage/cover_reg_top/0.gpio_intr_test.2377432852 Mar 31 12:29:59 PM PDT 24 Mar 31 12:30:00 PM PDT 24 20958188 ps
T86 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2695100007 Mar 31 12:30:01 PM PDT 24 Mar 31 12:30:02 PM PDT 24 47303950 ps
T830 /workspace/coverage/cover_reg_top/1.gpio_intr_test.3157146301 Mar 31 12:30:01 PM PDT 24 Mar 31 12:30:02 PM PDT 24 24097176 ps
T83 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.2117872534 Mar 31 12:30:00 PM PDT 24 Mar 31 12:30:01 PM PDT 24 25600793 ps
T831 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.280222960 Mar 31 12:30:27 PM PDT 24 Mar 31 12:30:28 PM PDT 24 172841644 ps
T832 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.418858920 Mar 31 12:30:24 PM PDT 24 Mar 31 12:30:24 PM PDT 24 48174000 ps
T833 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1169551039 Mar 31 12:30:28 PM PDT 24 Mar 31 12:30:29 PM PDT 24 124558874 ps
T834 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1425467134 Mar 31 12:30:07 PM PDT 24 Mar 31 12:30:08 PM PDT 24 18325825 ps
T835 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3436644752 Mar 31 12:30:28 PM PDT 24 Mar 31 12:30:29 PM PDT 24 188836378 ps
T836 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3703738664 Mar 31 12:30:05 PM PDT 24 Mar 31 12:30:06 PM PDT 24 37341740 ps
T837 /workspace/coverage/cover_reg_top/37.gpio_intr_test.4040557279 Mar 31 12:30:32 PM PDT 24 Mar 31 12:30:33 PM PDT 24 27552982 ps
T838 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1326038372 Mar 31 12:30:03 PM PDT 24 Mar 31 12:30:04 PM PDT 24 22719957 ps
T839 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.668424659 Mar 31 12:30:29 PM PDT 24 Mar 31 12:30:30 PM PDT 24 11145027 ps
T840 /workspace/coverage/cover_reg_top/41.gpio_intr_test.1348110077 Mar 31 12:30:42 PM PDT 24 Mar 31 12:30:42 PM PDT 24 14057128 ps
T841 /workspace/coverage/cover_reg_top/18.gpio_intr_test.459400400 Mar 31 12:30:33 PM PDT 24 Mar 31 12:30:33 PM PDT 24 18150269 ps
T842 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2922645935 Mar 31 12:28:32 PM PDT 24 Mar 31 12:28:33 PM PDT 24 74497948 ps
T843 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4203121507 Mar 31 12:27:59 PM PDT 24 Mar 31 12:28:01 PM PDT 24 376723773 ps
T844 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2269568390 Mar 31 12:28:38 PM PDT 24 Mar 31 12:28:39 PM PDT 24 146367637 ps
T845 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.655395395 Mar 31 12:28:05 PM PDT 24 Mar 31 12:28:06 PM PDT 24 85883011 ps
T846 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3965866935 Mar 31 12:28:26 PM PDT 24 Mar 31 12:28:32 PM PDT 24 85946235 ps
T847 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2477562095 Mar 31 12:28:24 PM PDT 24 Mar 31 12:28:25 PM PDT 24 42034388 ps
T848 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.854068191 Mar 31 12:28:00 PM PDT 24 Mar 31 12:28:01 PM PDT 24 36929993 ps
T849 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.4048737717 Mar 31 12:27:57 PM PDT 24 Mar 31 12:28:03 PM PDT 24 164195060 ps
T850 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.245426146 Mar 31 12:27:58 PM PDT 24 Mar 31 12:28:00 PM PDT 24 159847929 ps
T851 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2592738536 Mar 31 12:28:11 PM PDT 24 Mar 31 12:28:12 PM PDT 24 51842583 ps
T852 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3307181001 Mar 31 12:29:23 PM PDT 24 Mar 31 12:29:24 PM PDT 24 99445961 ps
T853 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.374142315 Mar 31 12:28:16 PM PDT 24 Mar 31 12:28:18 PM PDT 24 82329832 ps
T854 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3484510617 Mar 31 12:28:23 PM PDT 24 Mar 31 12:28:24 PM PDT 24 94982445 ps
T855 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.217801259 Mar 31 12:28:29 PM PDT 24 Mar 31 12:28:31 PM PDT 24 55682119 ps
T856 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3995222760 Mar 31 12:29:23 PM PDT 24 Mar 31 12:29:24 PM PDT 24 97085889 ps
T857 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3043997662 Mar 31 12:28:28 PM PDT 24 Mar 31 12:28:29 PM PDT 24 88530594 ps
T858 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3927352923 Mar 31 12:29:30 PM PDT 24 Mar 31 12:29:31 PM PDT 24 64624416 ps
T859 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2006909914 Mar 31 12:28:31 PM PDT 24 Mar 31 12:28:32 PM PDT 24 558184285 ps
T860 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.216884174 Mar 31 12:28:19 PM PDT 24 Mar 31 12:28:20 PM PDT 24 43634943 ps
T861 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.3280146335 Mar 31 12:28:31 PM PDT 24 Mar 31 12:28:32 PM PDT 24 90287804 ps
T862 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.113427464 Mar 31 12:28:23 PM PDT 24 Mar 31 12:28:24 PM PDT 24 39773194 ps
T863 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3094168553 Mar 31 12:28:19 PM PDT 24 Mar 31 12:28:20 PM PDT 24 28663263 ps
T864 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.914488021 Mar 31 12:29:19 PM PDT 24 Mar 31 12:29:20 PM PDT 24 198695104 ps
T865 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2518448446 Mar 31 12:28:22 PM PDT 24 Mar 31 12:28:23 PM PDT 24 176115478 ps
T866 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2223096641 Mar 31 12:28:23 PM PDT 24 Mar 31 12:28:30 PM PDT 24 229313947 ps
T867 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.858383595 Mar 31 12:29:15 PM PDT 24 Mar 31 12:29:17 PM PDT 24 221102468 ps
T868 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.154933150 Mar 31 12:28:26 PM PDT 24 Mar 31 12:28:28 PM PDT 24 398069948 ps
T869 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2552915760 Mar 31 12:29:31 PM PDT 24 Mar 31 12:29:32 PM PDT 24 154331160 ps
T870 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.614951742 Mar 31 12:28:14 PM PDT 24 Mar 31 12:28:15 PM PDT 24 54813910 ps
T871 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2788235469 Mar 31 12:28:39 PM PDT 24 Mar 31 12:28:40 PM PDT 24 86323601 ps
T872 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4008999419 Mar 31 12:28:01 PM PDT 24 Mar 31 12:28:02 PM PDT 24 44136941 ps
T873 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.958421813 Mar 31 12:28:24 PM PDT 24 Mar 31 12:28:25 PM PDT 24 360747865 ps
T874 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3510716488 Mar 31 12:28:27 PM PDT 24 Mar 31 12:28:28 PM PDT 24 141551567 ps
T875 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.758399390 Mar 31 12:28:21 PM PDT 24 Mar 31 12:28:22 PM PDT 24 227329004 ps
T876 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.4197197926 Mar 31 12:28:38 PM PDT 24 Mar 31 12:28:39 PM PDT 24 191580719 ps
T877 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2124295384 Mar 31 12:28:32 PM PDT 24 Mar 31 12:28:33 PM PDT 24 982286509 ps
T878 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.2157377687 Mar 31 12:28:07 PM PDT 24 Mar 31 12:28:09 PM PDT 24 747235319 ps
T879 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1325178863 Mar 31 12:28:00 PM PDT 24 Mar 31 12:28:01 PM PDT 24 262566922 ps
T880 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2752263930 Mar 31 12:28:24 PM PDT 24 Mar 31 12:28:26 PM PDT 24 155247310 ps
T881 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.169830804 Mar 31 12:28:07 PM PDT 24 Mar 31 12:28:08 PM PDT 24 39197182 ps
T882 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3779069475 Mar 31 12:28:23 PM PDT 24 Mar 31 12:28:24 PM PDT 24 50916884 ps
T883 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2247677246 Mar 31 12:29:01 PM PDT 24 Mar 31 12:29:08 PM PDT 24 238906525 ps
T884 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2574927661 Mar 31 12:28:28 PM PDT 24 Mar 31 12:28:29 PM PDT 24 55173503 ps
T885 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2224439233 Mar 31 12:28:13 PM PDT 24 Mar 31 12:28:14 PM PDT 24 290432212 ps
T886 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1911470142 Mar 31 12:27:49 PM PDT 24 Mar 31 12:27:51 PM PDT 24 210599227 ps
T887 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.731256824 Mar 31 12:28:45 PM PDT 24 Mar 31 12:28:46 PM PDT 24 52930002 ps
T888 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.743087821 Mar 31 12:28:28 PM PDT 24 Mar 31 12:28:29 PM PDT 24 263180423 ps
T889 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.90849804 Mar 31 12:28:36 PM PDT 24 Mar 31 12:28:37 PM PDT 24 36555078 ps
T890 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1641807349 Mar 31 12:28:59 PM PDT 24 Mar 31 12:29:01 PM PDT 24 83511903 ps
T891 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.767573938 Mar 31 12:28:20 PM PDT 24 Mar 31 12:28:21 PM PDT 24 517858075 ps
T892 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3753491502 Mar 31 12:28:37 PM PDT 24 Mar 31 12:28:39 PM PDT 24 69233045 ps
T893 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4072215626 Mar 31 12:28:20 PM PDT 24 Mar 31 12:28:21 PM PDT 24 55970057 ps
T894 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.636664667 Mar 31 12:28:38 PM PDT 24 Mar 31 12:28:39 PM PDT 24 37863039 ps
T895 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1939190133 Mar 31 12:28:39 PM PDT 24 Mar 31 12:28:40 PM PDT 24 31397850 ps
T896 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1385450802 Mar 31 12:27:59 PM PDT 24 Mar 31 12:28:00 PM PDT 24 51042246 ps
T897 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3284434900 Mar 31 12:29:26 PM PDT 24 Mar 31 12:29:27 PM PDT 24 159643894 ps
T898 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1499566078 Mar 31 12:28:38 PM PDT 24 Mar 31 12:28:39 PM PDT 24 52224713 ps
T899 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1308657923 Mar 31 12:28:33 PM PDT 24 Mar 31 12:28:35 PM PDT 24 131107128 ps
T900 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1779460141 Mar 31 12:28:33 PM PDT 24 Mar 31 12:28:35 PM PDT 24 732635852 ps
T901 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1358149602 Mar 31 12:29:01 PM PDT 24 Mar 31 12:29:04 PM PDT 24 331050727 ps
T902 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2902983898 Mar 31 12:28:19 PM PDT 24 Mar 31 12:28:20 PM PDT 24 196526678 ps
T903 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3838694625 Mar 31 12:27:52 PM PDT 24 Mar 31 12:27:54 PM PDT 24 396629406 ps
T904 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.494460196 Mar 31 12:28:04 PM PDT 24 Mar 31 12:28:05 PM PDT 24 466969759 ps
T905 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.84834878 Mar 31 12:28:40 PM PDT 24 Mar 31 12:28:41 PM PDT 24 81954232 ps
T906 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2819035807 Mar 31 12:28:27 PM PDT 24 Mar 31 12:28:28 PM PDT 24 598955693 ps
T907 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.832443269 Mar 31 12:28:22 PM PDT 24 Mar 31 12:28:24 PM PDT 24 87194938 ps
T908 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2746003689 Mar 31 12:28:40 PM PDT 24 Mar 31 12:28:41 PM PDT 24 168880622 ps
T909 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2229595265 Mar 31 12:28:15 PM PDT 24 Mar 31 12:28:17 PM PDT 24 33721168 ps
T910 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1680396281 Mar 31 12:28:13 PM PDT 24 Mar 31 12:28:19 PM PDT 24 56174796 ps
T911 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.744376401 Mar 31 12:28:19 PM PDT 24 Mar 31 12:28:20 PM PDT 24 72468397 ps
T912 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1096968494 Mar 31 12:28:33 PM PDT 24 Mar 31 12:28:34 PM PDT 24 35472484 ps
T913 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2098125899 Mar 31 12:28:26 PM PDT 24 Mar 31 12:28:28 PM PDT 24 131619597 ps
T914 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.3668825729 Mar 31 12:29:27 PM PDT 24 Mar 31 12:29:28 PM PDT 24 60658673 ps
T915 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3953638289 Mar 31 12:28:39 PM PDT 24 Mar 31 12:28:40 PM PDT 24 59605867 ps
T916 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3139099800 Mar 31 12:27:58 PM PDT 24 Mar 31 12:27:59 PM PDT 24 25071580 ps
T917 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1918990327 Mar 31 12:28:29 PM PDT 24 Mar 31 12:28:31 PM PDT 24 120399198 ps
T918 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3483845905 Mar 31 12:27:58 PM PDT 24 Mar 31 12:28:04 PM PDT 24 231805873 ps
T919 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3812764788 Mar 31 12:28:30 PM PDT 24 Mar 31 12:28:32 PM PDT 24 39591443 ps
T920 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.412781457 Mar 31 12:28:21 PM PDT 24 Mar 31 12:28:22 PM PDT 24 110037197 ps
T921 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.279075938 Mar 31 12:28:25 PM PDT 24 Mar 31 12:28:26 PM PDT 24 125211126 ps
T922 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1771138161 Mar 31 12:28:22 PM PDT 24 Mar 31 12:28:23 PM PDT 24 279598721 ps
T923 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1400915614 Mar 31 12:28:30 PM PDT 24 Mar 31 12:28:32 PM PDT 24 104395225 ps
T924 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2161975679 Mar 31 12:27:54 PM PDT 24 Mar 31 12:28:05 PM PDT 24 142919307 ps
T925 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.4243443631 Mar 31 12:29:36 PM PDT 24 Mar 31 12:29:37 PM PDT 24 51024107 ps
T926 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.75135923 Mar 31 12:28:03 PM PDT 24 Mar 31 12:28:04 PM PDT 24 94869483 ps
T927 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.4133572757 Mar 31 12:28:05 PM PDT 24 Mar 31 12:28:06 PM PDT 24 285556823 ps
T928 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3931309959 Mar 31 12:28:02 PM PDT 24 Mar 31 12:28:03 PM PDT 24 40854183 ps
T929 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1561886067 Mar 31 12:28:01 PM PDT 24 Mar 31 12:28:02 PM PDT 24 106736006 ps
T930 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3844183452 Mar 31 12:28:35 PM PDT 24 Mar 31 12:28:37 PM PDT 24 363090996 ps
T931 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1379274586 Mar 31 12:28:38 PM PDT 24 Mar 31 12:28:39 PM PDT 24 133763169 ps
T932 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2764355071 Mar 31 12:28:14 PM PDT 24 Mar 31 12:28:15 PM PDT 24 71544847 ps
T933 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3555836362 Mar 31 12:28:13 PM PDT 24 Mar 31 12:28:14 PM PDT 24 214282539 ps
T934 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2855324018 Mar 31 12:28:40 PM PDT 24 Mar 31 12:28:41 PM PDT 24 89396189 ps
T935 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2483814535 Mar 31 12:28:05 PM PDT 24 Mar 31 12:28:06 PM PDT 24 70018830 ps
T936 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.782636408 Mar 31 12:28:32 PM PDT 24 Mar 31 12:28:33 PM PDT 24 71035271 ps
T937 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3871170188 Mar 31 12:28:25 PM PDT 24 Mar 31 12:28:27 PM PDT 24 43973474 ps
T938 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.148322561 Mar 31 12:28:00 PM PDT 24 Mar 31 12:28:01 PM PDT 24 228725513 ps
T939 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3574268307 Mar 31 12:28:18 PM PDT 24 Mar 31 12:28:19 PM PDT 24 61276692 ps
T940 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.741065856 Mar 31 12:28:00 PM PDT 24 Mar 31 12:28:01 PM PDT 24 32329456 ps
T941 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3233205823 Mar 31 12:28:22 PM PDT 24 Mar 31 12:28:24 PM PDT 24 108557439 ps

Test location /workspace/coverage/default/2.gpio_full_random.1284038543
Short name T21
Test name
Test status
Simulation time 142847004 ps
CPU time 0.73 seconds
Started Mar 31 12:38:00 PM PDT 24
Finished Mar 31 12:38:01 PM PDT 24
Peak memory 196708 kb
Host smart-cca9cb1c-a478-49a0-b695-2edfd488d821
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284038543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.1284038543
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.623415504
Short name T107
Test name
Test status
Simulation time 135644034 ps
CPU time 1.86 seconds
Started Mar 31 12:38:17 PM PDT 24
Finished Mar 31 12:38:19 PM PDT 24
Peak memory 198064 kb
Host smart-84e7b992-167a-4e67-8de7-a0af471b2a4c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623415504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.gpio_intr_with_filter_rand_intr_event.623415504
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_stress_all.75364448
Short name T1
Test name
Test status
Simulation time 18513818831 ps
CPU time 201.99 seconds
Started Mar 31 12:37:46 PM PDT 24
Finished Mar 31 12:41:08 PM PDT 24
Peak memory 198108 kb
Host smart-d66aef7e-9937-4be0-9c0f-945d8da5bdfa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75364448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpi
o_stress_all.75364448
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.1706541759
Short name T30
Test name
Test status
Simulation time 9564796974 ps
CPU time 295.61 seconds
Started Mar 31 12:38:32 PM PDT 24
Finished Mar 31 12:43:27 PM PDT 24
Peak memory 198188 kb
Host smart-c01a8e77-f4ca-4156-b33b-bd69de54f817
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1706541759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.1706541759
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.4084374454
Short name T38
Test name
Test status
Simulation time 386080808 ps
CPU time 0.99 seconds
Started Mar 31 12:38:12 PM PDT 24
Finished Mar 31 12:38:13 PM PDT 24
Peak memory 213860 kb
Host smart-5320f58f-9d23-440a-a15d-96f4a3b94cb6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084374454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.4084374454
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.4064091123
Short name T72
Test name
Test status
Simulation time 42561968 ps
CPU time 0.74 seconds
Started Mar 31 12:30:04 PM PDT 24
Finished Mar 31 12:30:05 PM PDT 24
Peak memory 195708 kb
Host smart-955d9682-cd6e-4140-825f-8dde476ed8e3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064091123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.4064091123
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.1785468785
Short name T28
Test name
Test status
Simulation time 169468163 ps
CPU time 3.2 seconds
Started Mar 31 12:38:22 PM PDT 24
Finished Mar 31 12:38:25 PM PDT 24
Peak memory 197172 kb
Host smart-e2ddc062-5bcd-4862-9a8a-cad788773c32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785468785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.1785468785
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.619023055
Short name T37
Test name
Test status
Simulation time 420662929 ps
CPU time 1.43 seconds
Started Mar 31 12:30:28 PM PDT 24
Finished Mar 31 12:30:30 PM PDT 24
Peak memory 197684 kb
Host smart-ef3b4eda-4b26-46eb-ba5f-4ff434c91b65
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619023055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.gpio_tl_intg_err.619023055
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.233248877
Short name T41
Test name
Test status
Simulation time 38431273 ps
CPU time 0.56 seconds
Started Mar 31 12:37:38 PM PDT 24
Finished Mar 31 12:37:39 PM PDT 24
Peak memory 193772 kb
Host smart-9f945cba-c892-48a6-a684-db56c1576550
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233248877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.233248877
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3663850659
Short name T73
Test name
Test status
Simulation time 101859923 ps
CPU time 0.75 seconds
Started Mar 31 12:29:59 PM PDT 24
Finished Mar 31 12:30:01 PM PDT 24
Peak memory 196540 kb
Host smart-d2ddcfc2-bcf3-47db-a403-28ce043771c2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663850659 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.3663850659
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1169551039
Short name T833
Test name
Test status
Simulation time 124558874 ps
CPU time 1.45 seconds
Started Mar 31 12:30:28 PM PDT 24
Finished Mar 31 12:30:29 PM PDT 24
Peak memory 197428 kb
Host smart-60ec8587-63a1-43e7-8600-90baaa9e69e8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169551039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.1169551039
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1425467134
Short name T834
Test name
Test status
Simulation time 18325825 ps
CPU time 0.75 seconds
Started Mar 31 12:30:07 PM PDT 24
Finished Mar 31 12:30:08 PM PDT 24
Peak memory 196124 kb
Host smart-584e2e56-32eb-4ebc-8773-8491d5cafe40
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425467134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.1425467134
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1434142667
Short name T81
Test name
Test status
Simulation time 519778009 ps
CPU time 2.51 seconds
Started Mar 31 12:30:17 PM PDT 24
Finished Mar 31 12:30:20 PM PDT 24
Peak memory 196468 kb
Host smart-7c22168b-542b-4d82-b74a-d8e7b75e1594
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434142667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.1434142667
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3134634234
Short name T801
Test name
Test status
Simulation time 57946983 ps
CPU time 0.6 seconds
Started Mar 31 12:30:02 PM PDT 24
Finished Mar 31 12:30:03 PM PDT 24
Peak memory 194012 kb
Host smart-c47e7eea-7b13-4acb-98b4-dde8d10eea51
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134634234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.3134634234
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2242569082
Short name T727
Test name
Test status
Simulation time 341854900 ps
CPU time 0.85 seconds
Started Mar 31 12:30:04 PM PDT 24
Finished Mar 31 12:30:05 PM PDT 24
Peak memory 197700 kb
Host smart-9a1a9c15-3983-4e91-b5a4-9f0cf7a3f5c3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242569082 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.2242569082
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.591943846
Short name T814
Test name
Test status
Simulation time 26078589 ps
CPU time 0.64 seconds
Started Mar 31 12:30:21 PM PDT 24
Finished Mar 31 12:30:21 PM PDT 24
Peak memory 194536 kb
Host smart-c1cb9f5b-2d5e-44cf-8b95-3f3d2177ce0f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591943846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_
csr_rw.591943846
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.2377432852
Short name T829
Test name
Test status
Simulation time 20958188 ps
CPU time 0.56 seconds
Started Mar 31 12:29:59 PM PDT 24
Finished Mar 31 12:30:00 PM PDT 24
Peak memory 193476 kb
Host smart-702ade13-f55a-41d9-94a6-58f56ee5b301
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377432852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.2377432852
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.783726236
Short name T751
Test name
Test status
Simulation time 328192360 ps
CPU time 2.83 seconds
Started Mar 31 12:30:03 PM PDT 24
Finished Mar 31 12:30:06 PM PDT 24
Peak memory 197708 kb
Host smart-082ba052-65ca-44a7-8c78-19c1c2ed3641
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783726236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.783726236
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.3109833480
Short name T786
Test name
Test status
Simulation time 105503633 ps
CPU time 0.87 seconds
Started Mar 31 12:30:12 PM PDT 24
Finished Mar 31 12:30:13 PM PDT 24
Peak memory 197508 kb
Host smart-b6d6292e-25b4-4323-908a-60b328dc5ef8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109833480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.3109833480
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1881457189
Short name T816
Test name
Test status
Simulation time 810488979 ps
CPU time 3.48 seconds
Started Mar 31 12:31:23 PM PDT 24
Finished Mar 31 12:31:26 PM PDT 24
Peak memory 196712 kb
Host smart-9a74b1d2-8107-4fb0-b8fa-7c3d33eaca70
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881457189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.1881457189
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2112740899
Short name T106
Test name
Test status
Simulation time 88591777 ps
CPU time 0.59 seconds
Started Mar 31 12:30:13 PM PDT 24
Finished Mar 31 12:30:14 PM PDT 24
Peak memory 194528 kb
Host smart-4eb0f7d8-9d27-4387-a9cf-df3feaa8a50a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112740899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.2112740899
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.4004124228
Short name T755
Test name
Test status
Simulation time 55424598 ps
CPU time 0.81 seconds
Started Mar 31 12:31:22 PM PDT 24
Finished Mar 31 12:31:23 PM PDT 24
Peak memory 197476 kb
Host smart-9a87c80a-4cf4-4de9-ab03-725ab267ec8a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004124228 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.4004124228
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2594174629
Short name T104
Test name
Test status
Simulation time 20752479 ps
CPU time 0.6 seconds
Started Mar 31 12:30:19 PM PDT 24
Finished Mar 31 12:30:20 PM PDT 24
Peak memory 194472 kb
Host smart-b3ae563b-d20e-4b31-b076-fc7b9b85d297
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594174629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.2594174629
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.3157146301
Short name T830
Test name
Test status
Simulation time 24097176 ps
CPU time 0.59 seconds
Started Mar 31 12:30:01 PM PDT 24
Finished Mar 31 12:30:02 PM PDT 24
Peak memory 194012 kb
Host smart-63794f71-3235-49dc-b6ea-dafc9bfbc1a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157146301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.3157146301
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3539703278
Short name T765
Test name
Test status
Simulation time 55340659 ps
CPU time 0.71 seconds
Started Mar 31 12:31:25 PM PDT 24
Finished Mar 31 12:31:25 PM PDT 24
Peak memory 194608 kb
Host smart-6a876b33-1c78-4af3-a6e9-4995922505b1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539703278 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.3539703278
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3974354854
Short name T773
Test name
Test status
Simulation time 202679554 ps
CPU time 2.82 seconds
Started Mar 31 12:31:23 PM PDT 24
Finished Mar 31 12:31:26 PM PDT 24
Peak memory 197572 kb
Host smart-f3371285-ee86-46e2-996c-540f2f25041e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974354854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.3974354854
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.12786908
Short name T807
Test name
Test status
Simulation time 95533142 ps
CPU time 1.38 seconds
Started Mar 31 12:29:59 PM PDT 24
Finished Mar 31 12:30:01 PM PDT 24
Peak memory 197684 kb
Host smart-bc8754a8-f393-4914-850f-57a4a8ba7613
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12786908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_tl_intg_err.12786908
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.1738968492
Short name T723
Test name
Test status
Simulation time 28535111 ps
CPU time 1.37 seconds
Started Mar 31 12:30:30 PM PDT 24
Finished Mar 31 12:30:32 PM PDT 24
Peak memory 197744 kb
Host smart-4684384f-09b8-48af-8b06-cc91287c068c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738968492 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.1738968492
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.1959298845
Short name T68
Test name
Test status
Simulation time 36501587 ps
CPU time 0.56 seconds
Started Mar 31 12:30:29 PM PDT 24
Finished Mar 31 12:30:30 PM PDT 24
Peak memory 193632 kb
Host smart-32267982-23be-4e3a-8f7f-6534296ad5c6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959298845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.1959298845
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.4009531280
Short name T736
Test name
Test status
Simulation time 18522103 ps
CPU time 0.67 seconds
Started Mar 31 12:30:23 PM PDT 24
Finished Mar 31 12:30:24 PM PDT 24
Peak memory 194116 kb
Host smart-76674ce6-9c65-44d5-b033-c10f58b608af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009531280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.4009531280
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.695411048
Short name T763
Test name
Test status
Simulation time 31696266 ps
CPU time 0.67 seconds
Started Mar 31 12:30:24 PM PDT 24
Finished Mar 31 12:30:24 PM PDT 24
Peak memory 194592 kb
Host smart-f81aba49-4eeb-4c43-9bfc-fabcb92e68b9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695411048 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 10.gpio_same_csr_outstanding.695411048
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3117387376
Short name T776
Test name
Test status
Simulation time 97755528 ps
CPU time 2.39 seconds
Started Mar 31 12:30:19 PM PDT 24
Finished Mar 31 12:30:22 PM PDT 24
Peak memory 197796 kb
Host smart-4c8f9304-7b1d-4d1a-9556-4128ec560c88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117387376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.3117387376
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.3000864081
Short name T33
Test name
Test status
Simulation time 70421192 ps
CPU time 0.85 seconds
Started Mar 31 12:30:27 PM PDT 24
Finished Mar 31 12:30:28 PM PDT 24
Peak memory 196564 kb
Host smart-b7eeea6e-4022-4050-8361-837aec76100c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000864081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.3000864081
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.969833245
Short name T757
Test name
Test status
Simulation time 144619290 ps
CPU time 1.04 seconds
Started Mar 31 12:30:15 PM PDT 24
Finished Mar 31 12:30:16 PM PDT 24
Peak memory 197588 kb
Host smart-bea0ae17-9d78-48e2-9a48-ff48eea92bcd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969833245 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.969833245
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1811367433
Short name T105
Test name
Test status
Simulation time 77573495 ps
CPU time 0.59 seconds
Started Mar 31 12:30:15 PM PDT 24
Finished Mar 31 12:30:16 PM PDT 24
Peak memory 194464 kb
Host smart-2324ed11-0203-4b50-a751-9aaecc52a9de
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811367433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.1811367433
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.2267941324
Short name T720
Test name
Test status
Simulation time 49875818 ps
CPU time 0.61 seconds
Started Mar 31 12:30:27 PM PDT 24
Finished Mar 31 12:30:28 PM PDT 24
Peak memory 194048 kb
Host smart-1058858e-7bc1-4345-9e0c-71252fd78191
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267941324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.2267941324
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.2469353633
Short name T74
Test name
Test status
Simulation time 49176789 ps
CPU time 0.69 seconds
Started Mar 31 12:30:34 PM PDT 24
Finished Mar 31 12:30:34 PM PDT 24
Peak memory 194812 kb
Host smart-04f6fe7e-52f4-4666-af85-2745ff6dc5ab
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469353633 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.2469353633
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2799125402
Short name T813
Test name
Test status
Simulation time 522723600 ps
CPU time 2.37 seconds
Started Mar 31 12:30:31 PM PDT 24
Finished Mar 31 12:30:34 PM PDT 24
Peak memory 197704 kb
Host smart-42bddf45-e4da-48ff-9827-8d861e0efc32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799125402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.2799125402
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.4009149916
Short name T45
Test name
Test status
Simulation time 158767968 ps
CPU time 1.11 seconds
Started Mar 31 12:30:33 PM PDT 24
Finished Mar 31 12:30:34 PM PDT 24
Peak memory 197804 kb
Host smart-2f111bed-f173-46c6-8614-26012b0a6c71
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009149916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.4009149916
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1403152052
Short name T753
Test name
Test status
Simulation time 58225228 ps
CPU time 0.94 seconds
Started Mar 31 12:30:31 PM PDT 24
Finished Mar 31 12:30:32 PM PDT 24
Peak memory 197596 kb
Host smart-b62300d2-bd71-481a-b445-2470525bc14e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403152052 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.1403152052
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1370797146
Short name T85
Test name
Test status
Simulation time 15047281 ps
CPU time 0.63 seconds
Started Mar 31 12:30:31 PM PDT 24
Finished Mar 31 12:30:32 PM PDT 24
Peak memory 194708 kb
Host smart-dc5dfa08-3c34-4973-ae19-b8bfa7a4bc59
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370797146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.1370797146
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.2389198254
Short name T725
Test name
Test status
Simulation time 35619316 ps
CPU time 0.63 seconds
Started Mar 31 12:30:31 PM PDT 24
Finished Mar 31 12:30:32 PM PDT 24
Peak memory 193416 kb
Host smart-6120f11a-7c06-4da0-856e-b77ba42cd1e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389198254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.2389198254
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2581197565
Short name T69
Test name
Test status
Simulation time 173841108 ps
CPU time 0.76 seconds
Started Mar 31 12:30:24 PM PDT 24
Finished Mar 31 12:30:24 PM PDT 24
Peak memory 195656 kb
Host smart-3e1f2a75-2b22-4a5c-b040-e3dc1d9f5c29
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581197565 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2581197565
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1180211732
Short name T826
Test name
Test status
Simulation time 387691498 ps
CPU time 2.04 seconds
Started Mar 31 12:30:30 PM PDT 24
Finished Mar 31 12:30:32 PM PDT 24
Peak memory 197720 kb
Host smart-f2d6c9c3-5d4f-49d3-9fda-b48deb77e198
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180211732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.1180211732
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1238915377
Short name T35
Test name
Test status
Simulation time 226013532 ps
CPU time 1.14 seconds
Started Mar 31 12:30:30 PM PDT 24
Finished Mar 31 12:30:31 PM PDT 24
Peak memory 197660 kb
Host smart-14ea1cb2-f5d8-4cdd-a6b2-7f927dff66a6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238915377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.1238915377
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.2326993335
Short name T760
Test name
Test status
Simulation time 43077164 ps
CPU time 0.73 seconds
Started Mar 31 12:30:26 PM PDT 24
Finished Mar 31 12:30:27 PM PDT 24
Peak memory 197688 kb
Host smart-b400e0c3-f5fa-4533-813c-4a8ea7c375cc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326993335 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.2326993335
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2397372614
Short name T67
Test name
Test status
Simulation time 16344842 ps
CPU time 0.59 seconds
Started Mar 31 12:30:31 PM PDT 24
Finished Mar 31 12:30:32 PM PDT 24
Peak memory 194400 kb
Host smart-fe5cbce2-c08c-4947-8fda-26101906db9d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397372614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.2397372614
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.749250245
Short name T825
Test name
Test status
Simulation time 27549038 ps
CPU time 0.58 seconds
Started Mar 31 12:30:27 PM PDT 24
Finished Mar 31 12:30:28 PM PDT 24
Peak memory 193380 kb
Host smart-397c18de-131c-4294-86d6-c9ed064f6c76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749250245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.749250245
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1251736358
Short name T90
Test name
Test status
Simulation time 55744180 ps
CPU time 0.74 seconds
Started Mar 31 12:30:27 PM PDT 24
Finished Mar 31 12:30:28 PM PDT 24
Peak memory 195800 kb
Host smart-4bec757a-fba8-4ecd-9858-d4410c4853eb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251736358 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.1251736358
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1307298356
Short name T770
Test name
Test status
Simulation time 23316723 ps
CPU time 1.17 seconds
Started Mar 31 12:30:28 PM PDT 24
Finished Mar 31 12:30:30 PM PDT 24
Peak memory 197760 kb
Host smart-07cced7b-3f08-450b-a29c-e3c4be0bdcc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307298356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.1307298356
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.659874863
Short name T46
Test name
Test status
Simulation time 443905629 ps
CPU time 1.45 seconds
Started Mar 31 12:30:22 PM PDT 24
Finished Mar 31 12:30:24 PM PDT 24
Peak memory 197756 kb
Host smart-89ce83b0-49ad-41ee-970e-8a0c496ee22d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659874863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.gpio_tl_intg_err.659874863
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1285671268
Short name T766
Test name
Test status
Simulation time 56613481 ps
CPU time 0.91 seconds
Started Mar 31 12:30:30 PM PDT 24
Finished Mar 31 12:30:31 PM PDT 24
Peak memory 197712 kb
Host smart-7a98fe6c-1479-461a-ad4e-05dad2ff66d4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285671268 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.1285671268
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1905560968
Short name T820
Test name
Test status
Simulation time 16566506 ps
CPU time 0.68 seconds
Started Mar 31 12:30:23 PM PDT 24
Finished Mar 31 12:30:24 PM PDT 24
Peak memory 195104 kb
Host smart-3d13c004-c49e-4a7d-83e3-3b3a7653f08a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905560968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.1905560968
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.3686342827
Short name T790
Test name
Test status
Simulation time 32942348 ps
CPU time 0.6 seconds
Started Mar 31 12:30:23 PM PDT 24
Finished Mar 31 12:30:24 PM PDT 24
Peak memory 193444 kb
Host smart-762e9174-18af-4bf5-a569-b7e62c676570
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686342827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.3686342827
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2360930879
Short name T89
Test name
Test status
Simulation time 37860291 ps
CPU time 0.66 seconds
Started Mar 31 12:30:26 PM PDT 24
Finished Mar 31 12:30:27 PM PDT 24
Peak memory 194608 kb
Host smart-efe019a5-f348-40ec-ab0a-0561204bc477
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360930879 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.2360930879
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.74198131
Short name T769
Test name
Test status
Simulation time 110689573 ps
CPU time 2.94 seconds
Started Mar 31 12:30:33 PM PDT 24
Finished Mar 31 12:30:37 PM PDT 24
Peak memory 197688 kb
Host smart-efd0f00d-bc34-4c57-8b19-4230e4084243
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74198131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.74198131
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.904875982
Short name T788
Test name
Test status
Simulation time 118441053 ps
CPU time 1.54 seconds
Started Mar 31 12:30:28 PM PDT 24
Finished Mar 31 12:30:29 PM PDT 24
Peak memory 197756 kb
Host smart-a3a66ec2-73b5-4b7b-a9b5-ac633ea09786
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904875982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.gpio_tl_intg_err.904875982
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.3941023237
Short name T740
Test name
Test status
Simulation time 83329636 ps
CPU time 0.76 seconds
Started Mar 31 12:30:32 PM PDT 24
Finished Mar 31 12:30:33 PM PDT 24
Peak memory 197596 kb
Host smart-caaf1e94-a8f8-4f3b-beec-d166eb666df4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941023237 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.3941023237
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1339777238
Short name T754
Test name
Test status
Simulation time 218465836 ps
CPU time 0.56 seconds
Started Mar 31 12:30:34 PM PDT 24
Finished Mar 31 12:30:34 PM PDT 24
Peak memory 194548 kb
Host smart-a88b8715-8153-4a4d-a549-3ceb97bce1dd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339777238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.1339777238
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.3471143287
Short name T787
Test name
Test status
Simulation time 42524236 ps
CPU time 0.59 seconds
Started Mar 31 12:30:31 PM PDT 24
Finished Mar 31 12:30:32 PM PDT 24
Peak memory 193276 kb
Host smart-3d3a9d7e-fac7-431e-a90b-225ad17e8860
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471143287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.3471143287
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1423412619
Short name T774
Test name
Test status
Simulation time 40920557 ps
CPU time 0.72 seconds
Started Mar 31 12:30:32 PM PDT 24
Finished Mar 31 12:30:33 PM PDT 24
Peak memory 196044 kb
Host smart-5715bd98-acfc-4bd1-86be-adb65e6ef228
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423412619 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.1423412619
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1697133835
Short name T803
Test name
Test status
Simulation time 119894447 ps
CPU time 1.71 seconds
Started Mar 31 12:30:44 PM PDT 24
Finished Mar 31 12:30:46 PM PDT 24
Peak memory 197776 kb
Host smart-befb29a9-3ffb-4c6c-9848-f2bbb380d415
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697133835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.1697133835
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2386073568
Short name T767
Test name
Test status
Simulation time 1005950060 ps
CPU time 1.94 seconds
Started Mar 31 12:30:31 PM PDT 24
Finished Mar 31 12:30:33 PM PDT 24
Peak memory 197524 kb
Host smart-dda7b9ed-4f93-4ba0-baf8-ccdce7d61742
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386073568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.2386073568
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1088611968
Short name T828
Test name
Test status
Simulation time 15924233 ps
CPU time 0.79 seconds
Started Mar 31 12:30:29 PM PDT 24
Finished Mar 31 12:30:30 PM PDT 24
Peak memory 197656 kb
Host smart-65e2e2c3-d2ea-48fb-9563-e326ecfe0dd7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088611968 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.1088611968
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1944529243
Short name T77
Test name
Test status
Simulation time 20409240 ps
CPU time 0.62 seconds
Started Mar 31 12:30:27 PM PDT 24
Finished Mar 31 12:30:27 PM PDT 24
Peak memory 194212 kb
Host smart-4a0d8a59-dc15-43b9-ab08-3871f14b562b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944529243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.1944529243
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.2233009925
Short name T818
Test name
Test status
Simulation time 62275272 ps
CPU time 0.62 seconds
Started Mar 31 12:30:28 PM PDT 24
Finished Mar 31 12:30:29 PM PDT 24
Peak memory 194032 kb
Host smart-6d8c8563-be50-43fb-87bc-0c6559b3260b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233009925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.2233009925
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.762756226
Short name T88
Test name
Test status
Simulation time 19771786 ps
CPU time 0.84 seconds
Started Mar 31 12:30:26 PM PDT 24
Finished Mar 31 12:30:27 PM PDT 24
Peak memory 195740 kb
Host smart-8542dac5-dda4-4f1f-ac34-8855746914e9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762756226 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 16.gpio_same_csr_outstanding.762756226
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.3482124147
Short name T744
Test name
Test status
Simulation time 44130097 ps
CPU time 2.24 seconds
Started Mar 31 12:30:24 PM PDT 24
Finished Mar 31 12:30:26 PM PDT 24
Peak memory 197760 kb
Host smart-5b0e53b3-d234-4161-8afc-b01f18b7831e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482124147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.3482124147
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.845115092
Short name T743
Test name
Test status
Simulation time 336749836 ps
CPU time 1.53 seconds
Started Mar 31 12:30:32 PM PDT 24
Finished Mar 31 12:30:34 PM PDT 24
Peak memory 197804 kb
Host smart-b47aed29-a107-49b2-9e0d-b1b11e77bac1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845115092 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.845115092
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.668424659
Short name T839
Test name
Test status
Simulation time 11145027 ps
CPU time 0.57 seconds
Started Mar 31 12:30:29 PM PDT 24
Finished Mar 31 12:30:30 PM PDT 24
Peak memory 193692 kb
Host smart-cc07a16c-d4f4-46be-bf35-fc5c534e0520
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668424659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio
_csr_rw.668424659
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.150501894
Short name T719
Test name
Test status
Simulation time 40077561 ps
CPU time 0.58 seconds
Started Mar 31 12:30:49 PM PDT 24
Finished Mar 31 12:30:55 PM PDT 24
Peak memory 194056 kb
Host smart-4cd8b912-6d12-4ee3-b279-6289d9a5dbd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150501894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.150501894
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2730005491
Short name T782
Test name
Test status
Simulation time 67578200 ps
CPU time 0.64 seconds
Started Mar 31 12:30:33 PM PDT 24
Finished Mar 31 12:30:34 PM PDT 24
Peak memory 194032 kb
Host smart-139a654f-f18a-45f7-a854-b93a90ad5b64
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730005491 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.2730005491
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3337136681
Short name T815
Test name
Test status
Simulation time 46603022 ps
CPU time 1.21 seconds
Started Mar 31 12:30:31 PM PDT 24
Finished Mar 31 12:30:33 PM PDT 24
Peak memory 197768 kb
Host smart-38389ee3-0ee5-4d11-b11b-9799c5c5720a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337136681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.3337136681
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.702714090
Short name T748
Test name
Test status
Simulation time 34055098 ps
CPU time 0.88 seconds
Started Mar 31 12:30:38 PM PDT 24
Finished Mar 31 12:30:39 PM PDT 24
Peak memory 197628 kb
Host smart-86fe0b5c-1530-4c2b-a3de-17406ae2c275
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702714090 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.702714090
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2382045576
Short name T82
Test name
Test status
Simulation time 12520465 ps
CPU time 0.58 seconds
Started Mar 31 12:30:38 PM PDT 24
Finished Mar 31 12:30:39 PM PDT 24
Peak memory 194336 kb
Host smart-597446ed-6ade-48c9-8b34-dabd3f6d7a6d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382045576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.2382045576
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.459400400
Short name T841
Test name
Test status
Simulation time 18150269 ps
CPU time 0.58 seconds
Started Mar 31 12:30:33 PM PDT 24
Finished Mar 31 12:30:33 PM PDT 24
Peak memory 193388 kb
Host smart-a09b9bcb-98b0-4415-bfe3-2f94069cecbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459400400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.459400400
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1928391047
Short name T92
Test name
Test status
Simulation time 35762257 ps
CPU time 0.91 seconds
Started Mar 31 12:30:30 PM PDT 24
Finished Mar 31 12:30:31 PM PDT 24
Peak memory 196552 kb
Host smart-ec509fcd-aea0-4f09-a581-f663bdc237f6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928391047 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.1928391047
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.1622653845
Short name T735
Test name
Test status
Simulation time 161314315 ps
CPU time 2.27 seconds
Started Mar 31 12:30:35 PM PDT 24
Finished Mar 31 12:30:37 PM PDT 24
Peak memory 197728 kb
Host smart-83bf38b2-9428-4038-9a5d-2e68bfdf02f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622653845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.1622653845
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.280222960
Short name T831
Test name
Test status
Simulation time 172841644 ps
CPU time 0.82 seconds
Started Mar 31 12:30:27 PM PDT 24
Finished Mar 31 12:30:28 PM PDT 24
Peak memory 196844 kb
Host smart-ba04d122-2e91-4dd8-9fba-e47ee596228b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280222960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.gpio_tl_intg_err.280222960
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.1210483246
Short name T764
Test name
Test status
Simulation time 34044885 ps
CPU time 0.91 seconds
Started Mar 31 12:30:32 PM PDT 24
Finished Mar 31 12:30:33 PM PDT 24
Peak memory 197688 kb
Host smart-d66d3d4d-1671-45b0-bb5f-c8614dbb9926
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210483246 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.1210483246
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.141195837
Short name T75
Test name
Test status
Simulation time 97001954 ps
CPU time 0.62 seconds
Started Mar 31 12:30:38 PM PDT 24
Finished Mar 31 12:30:39 PM PDT 24
Peak memory 194492 kb
Host smart-2adeecab-d940-4b20-aea2-6f7cdb27f962
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141195837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio
_csr_rw.141195837
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.362346693
Short name T812
Test name
Test status
Simulation time 14092804 ps
CPU time 0.59 seconds
Started Mar 31 12:31:05 PM PDT 24
Finished Mar 31 12:31:06 PM PDT 24
Peak memory 194012 kb
Host smart-e3a3d6f0-68c9-4c73-bd86-f2b30d672db7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362346693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.362346693
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.117919893
Short name T759
Test name
Test status
Simulation time 54304514 ps
CPU time 0.66 seconds
Started Mar 31 12:30:30 PM PDT 24
Finished Mar 31 12:30:31 PM PDT 24
Peak memory 194320 kb
Host smart-e3e510c5-df01-45f0-82dd-cd3f3bcd694d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117919893 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 19.gpio_same_csr_outstanding.117919893
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.675137224
Short name T734
Test name
Test status
Simulation time 681234030 ps
CPU time 2.43 seconds
Started Mar 31 12:30:30 PM PDT 24
Finished Mar 31 12:30:32 PM PDT 24
Peak memory 197716 kb
Host smart-9aeee119-317c-4f5e-9101-26107272ab22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675137224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.675137224
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2755028838
Short name T34
Test name
Test status
Simulation time 529108586 ps
CPU time 1.44 seconds
Started Mar 31 12:30:35 PM PDT 24
Finished Mar 31 12:30:36 PM PDT 24
Peak memory 197688 kb
Host smart-45a3e291-f182-4c68-8fe3-964f91c1d90a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755028838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.2755028838
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.4203641905
Short name T71
Test name
Test status
Simulation time 16082679 ps
CPU time 0.75 seconds
Started Mar 31 12:30:01 PM PDT 24
Finished Mar 31 12:30:02 PM PDT 24
Peak memory 196308 kb
Host smart-05298539-2c83-4675-b67d-f838321538ba
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203641905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.4203641905
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2232847990
Short name T777
Test name
Test status
Simulation time 637839882 ps
CPU time 3.45 seconds
Started Mar 31 12:29:59 PM PDT 24
Finished Mar 31 12:30:03 PM PDT 24
Peak memory 197648 kb
Host smart-62157cfe-a98c-445f-84b5-9b1295972e16
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232847990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.2232847990
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.3466577402
Short name T739
Test name
Test status
Simulation time 73853275 ps
CPU time 0.65 seconds
Started Mar 31 12:31:23 PM PDT 24
Finished Mar 31 12:31:24 PM PDT 24
Peak memory 194400 kb
Host smart-c9e2bf07-ea4d-4481-ab92-2196f684f934
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466577402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.3466577402
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2070552953
Short name T745
Test name
Test status
Simulation time 23245812 ps
CPU time 0.72 seconds
Started Mar 31 12:30:04 PM PDT 24
Finished Mar 31 12:30:05 PM PDT 24
Peak memory 197672 kb
Host smart-69c54756-97af-45df-9b73-06037259d2c7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070552953 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.2070552953
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2695100007
Short name T86
Test name
Test status
Simulation time 47303950 ps
CPU time 0.64 seconds
Started Mar 31 12:30:01 PM PDT 24
Finished Mar 31 12:30:02 PM PDT 24
Peak memory 195308 kb
Host smart-fe4a946d-c8fb-4e9f-a4b9-eb79cf67c641
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695100007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.2695100007
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.886629517
Short name T721
Test name
Test status
Simulation time 11379471 ps
CPU time 0.59 seconds
Started Mar 31 12:30:20 PM PDT 24
Finished Mar 31 12:30:21 PM PDT 24
Peak memory 193412 kb
Host smart-a34f131d-2358-451e-93f6-884e4442a1bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886629517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.886629517
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.814008704
Short name T93
Test name
Test status
Simulation time 30487105 ps
CPU time 0.78 seconds
Started Mar 31 12:30:28 PM PDT 24
Finished Mar 31 12:30:28 PM PDT 24
Peak memory 195572 kb
Host smart-48d50fb6-8b2d-4010-90c9-ed138967d17d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814008704 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.gpio_same_csr_outstanding.814008704
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2580983003
Short name T718
Test name
Test status
Simulation time 176785756 ps
CPU time 2.89 seconds
Started Mar 31 12:30:20 PM PDT 24
Finished Mar 31 12:30:23 PM PDT 24
Peak memory 197768 kb
Host smart-2f54947a-68d0-4328-8b13-88bb83c1f030
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580983003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.2580983003
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.2919910714
Short name T821
Test name
Test status
Simulation time 65332514 ps
CPU time 0.9 seconds
Started Mar 31 12:31:23 PM PDT 24
Finished Mar 31 12:31:24 PM PDT 24
Peak memory 196376 kb
Host smart-a287dc95-fefe-471c-af86-493cb4849ab9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919910714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.2919910714
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.3743534066
Short name T800
Test name
Test status
Simulation time 14543810 ps
CPU time 0.55 seconds
Started Mar 31 12:30:26 PM PDT 24
Finished Mar 31 12:30:26 PM PDT 24
Peak memory 193332 kb
Host smart-ab567ef0-50a3-4227-bce5-f80cb31fe156
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743534066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.3743534066
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.1873611142
Short name T747
Test name
Test status
Simulation time 12668985 ps
CPU time 0.68 seconds
Started Mar 31 12:30:30 PM PDT 24
Finished Mar 31 12:30:31 PM PDT 24
Peak memory 194016 kb
Host smart-9897e0e6-f203-4787-8bb6-76169a8b681a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873611142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.1873611142
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.2835109535
Short name T775
Test name
Test status
Simulation time 15892211 ps
CPU time 0.63 seconds
Started Mar 31 12:30:32 PM PDT 24
Finished Mar 31 12:30:33 PM PDT 24
Peak memory 194132 kb
Host smart-35b6136a-39b2-4781-95b0-1f88d3593bbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835109535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.2835109535
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.427899937
Short name T726
Test name
Test status
Simulation time 36110565 ps
CPU time 0.57 seconds
Started Mar 31 12:30:40 PM PDT 24
Finished Mar 31 12:30:41 PM PDT 24
Peak memory 194000 kb
Host smart-e849d6f7-3c38-42a4-99c2-7aec82ef0872
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427899937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.427899937
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.3244905710
Short name T779
Test name
Test status
Simulation time 41209723 ps
CPU time 0.6 seconds
Started Mar 31 12:30:28 PM PDT 24
Finished Mar 31 12:30:30 PM PDT 24
Peak memory 193368 kb
Host smart-16b2a677-460f-4f8d-b82b-b9dc9df011bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244905710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.3244905710
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.2225680319
Short name T805
Test name
Test status
Simulation time 15960443 ps
CPU time 0.62 seconds
Started Mar 31 12:30:32 PM PDT 24
Finished Mar 31 12:30:33 PM PDT 24
Peak memory 193352 kb
Host smart-0dc37c2b-ecce-4532-93e7-1e0fca25ce22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225680319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.2225680319
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.2257270811
Short name T792
Test name
Test status
Simulation time 97360091 ps
CPU time 0.65 seconds
Started Mar 31 12:30:36 PM PDT 24
Finished Mar 31 12:30:37 PM PDT 24
Peak memory 193460 kb
Host smart-b7073ed4-6fd2-4051-bf63-378d5f280b92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257270811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.2257270811
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.72240796
Short name T768
Test name
Test status
Simulation time 10883887 ps
CPU time 0.63 seconds
Started Mar 31 12:30:34 PM PDT 24
Finished Mar 31 12:30:35 PM PDT 24
Peak memory 193360 kb
Host smart-d8da7b9f-1cdb-4f9d-95ae-7452a94ab260
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72240796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.72240796
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.1754184630
Short name T794
Test name
Test status
Simulation time 62092939 ps
CPU time 0.56 seconds
Started Mar 31 12:30:34 PM PDT 24
Finished Mar 31 12:30:35 PM PDT 24
Peak memory 193428 kb
Host smart-31165cb0-f4de-4c86-bbbb-32d8d42decf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754184630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.1754184630
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.2814731857
Short name T802
Test name
Test status
Simulation time 159095174 ps
CPU time 0.62 seconds
Started Mar 31 12:30:36 PM PDT 24
Finished Mar 31 12:30:37 PM PDT 24
Peak memory 193456 kb
Host smart-7113487e-5354-4dc5-b13c-8b3c61332371
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814731857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.2814731857
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.3788427517
Short name T78
Test name
Test status
Simulation time 32315998 ps
CPU time 0.88 seconds
Started Mar 31 12:30:22 PM PDT 24
Finished Mar 31 12:30:23 PM PDT 24
Peak memory 196324 kb
Host smart-3cf70bd0-6b51-4bd6-ada8-63f1a67ff1b6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788427517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.3788427517
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2528172851
Short name T756
Test name
Test status
Simulation time 62709410 ps
CPU time 2.23 seconds
Started Mar 31 12:30:18 PM PDT 24
Finished Mar 31 12:30:22 PM PDT 24
Peak memory 196748 kb
Host smart-4268ae84-ab8c-440c-a056-e66a3d7ca338
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528172851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.2528172851
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.2117872534
Short name T83
Test name
Test status
Simulation time 25600793 ps
CPU time 0.65 seconds
Started Mar 31 12:30:00 PM PDT 24
Finished Mar 31 12:30:01 PM PDT 24
Peak memory 194652 kb
Host smart-cb5b8af2-4cb8-4999-bc24-7deee1ebed9b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117872534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.2117872534
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2443717405
Short name T732
Test name
Test status
Simulation time 20293483 ps
CPU time 0.7 seconds
Started Mar 31 12:29:59 PM PDT 24
Finished Mar 31 12:29:59 PM PDT 24
Peak memory 197296 kb
Host smart-612547f2-d52e-4675-9dc7-52fcc874d5af
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443717405 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.2443717405
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.797910086
Short name T79
Test name
Test status
Simulation time 13180188 ps
CPU time 0.6 seconds
Started Mar 31 12:30:09 PM PDT 24
Finished Mar 31 12:30:10 PM PDT 24
Peak memory 194372 kb
Host smart-1291669f-042f-45e0-81ca-51808264c9ea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797910086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_
csr_rw.797910086
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.1629824381
Short name T808
Test name
Test status
Simulation time 31308604 ps
CPU time 0.6 seconds
Started Mar 31 12:30:02 PM PDT 24
Finished Mar 31 12:30:03 PM PDT 24
Peak memory 193384 kb
Host smart-83afd730-106b-433e-bf07-42ebb34ed68b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629824381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.1629824381
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.1931572903
Short name T91
Test name
Test status
Simulation time 30166404 ps
CPU time 0.78 seconds
Started Mar 31 12:31:26 PM PDT 24
Finished Mar 31 12:31:28 PM PDT 24
Peak memory 195300 kb
Host smart-659cbcbc-67ee-4e4d-a06d-d208fbfd6efd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931572903 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.1931572903
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.2325977515
Short name T797
Test name
Test status
Simulation time 149129986 ps
CPU time 2.23 seconds
Started Mar 31 12:30:18 PM PDT 24
Finished Mar 31 12:30:20 PM PDT 24
Peak memory 197772 kb
Host smart-338000a1-e55a-4e1d-bf17-00066deeb128
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325977515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.2325977515
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2273385325
Short name T44
Test name
Test status
Simulation time 77996554 ps
CPU time 1.13 seconds
Started Mar 31 12:31:20 PM PDT 24
Finished Mar 31 12:31:22 PM PDT 24
Peak memory 197568 kb
Host smart-9c255890-203f-4b2e-9d24-896752aed1b2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273385325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.2273385325
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.3219967126
Short name T722
Test name
Test status
Simulation time 27973457 ps
CPU time 0.59 seconds
Started Mar 31 12:30:33 PM PDT 24
Finished Mar 31 12:30:34 PM PDT 24
Peak memory 194028 kb
Host smart-7da2bb7b-b294-4e11-b1d1-3068027fdbe9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219967126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.3219967126
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.3243758183
Short name T737
Test name
Test status
Simulation time 20719036 ps
CPU time 0.62 seconds
Started Mar 31 12:30:48 PM PDT 24
Finished Mar 31 12:30:48 PM PDT 24
Peak memory 193468 kb
Host smart-4adb6c0c-570f-4218-8b9d-6df761aa8c15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243758183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.3243758183
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.3403432592
Short name T758
Test name
Test status
Simulation time 12070892 ps
CPU time 0.59 seconds
Started Mar 31 12:30:58 PM PDT 24
Finished Mar 31 12:30:58 PM PDT 24
Peak memory 193408 kb
Host smart-50813b0c-ba13-4775-84de-d4337809c86b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403432592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.3403432592
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.1948140667
Short name T817
Test name
Test status
Simulation time 13807911 ps
CPU time 0.65 seconds
Started Mar 31 12:30:33 PM PDT 24
Finished Mar 31 12:30:34 PM PDT 24
Peak memory 193996 kb
Host smart-821e2c47-b207-4114-a9e8-8ca0667e79b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948140667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.1948140667
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.3374354238
Short name T738
Test name
Test status
Simulation time 25460712 ps
CPU time 0.57 seconds
Started Mar 31 12:30:52 PM PDT 24
Finished Mar 31 12:30:53 PM PDT 24
Peak memory 194076 kb
Host smart-a8a29564-debd-4fd3-940f-151226203db5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374354238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.3374354238
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.3267879092
Short name T798
Test name
Test status
Simulation time 134597423 ps
CPU time 0.62 seconds
Started Mar 31 12:30:57 PM PDT 24
Finished Mar 31 12:30:58 PM PDT 24
Peak memory 194084 kb
Host smart-f3eaee81-1fe7-4205-851e-87f8796f9a14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267879092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.3267879092
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.759904329
Short name T742
Test name
Test status
Simulation time 62256462 ps
CPU time 0.65 seconds
Started Mar 31 12:30:34 PM PDT 24
Finished Mar 31 12:30:35 PM PDT 24
Peak memory 193464 kb
Host smart-e914638a-6364-46f8-bc86-0e2ea9679298
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759904329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.759904329
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.4040557279
Short name T837
Test name
Test status
Simulation time 27552982 ps
CPU time 0.63 seconds
Started Mar 31 12:30:32 PM PDT 24
Finished Mar 31 12:30:33 PM PDT 24
Peak memory 193416 kb
Host smart-3ef11706-77cd-4641-9342-eb4ba914e5af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040557279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.4040557279
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.3179463988
Short name T819
Test name
Test status
Simulation time 31328767 ps
CPU time 0.55 seconds
Started Mar 31 12:30:37 PM PDT 24
Finished Mar 31 12:30:38 PM PDT 24
Peak memory 192648 kb
Host smart-e699130e-8526-4634-abfa-e5d2e541f091
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179463988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.3179463988
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.3836022738
Short name T809
Test name
Test status
Simulation time 36164645 ps
CPU time 0.6 seconds
Started Mar 31 12:30:33 PM PDT 24
Finished Mar 31 12:30:34 PM PDT 24
Peak memory 193340 kb
Host smart-58a034dd-354a-4964-8ab7-c01dc12ae9ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836022738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.3836022738
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2857798519
Short name T84
Test name
Test status
Simulation time 26534679 ps
CPU time 0.76 seconds
Started Mar 31 12:30:25 PM PDT 24
Finished Mar 31 12:30:26 PM PDT 24
Peak memory 195712 kb
Host smart-65400151-c7f4-4a12-b890-1f1a46555a8d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857798519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.2857798519
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.3047319788
Short name T76
Test name
Test status
Simulation time 127244753 ps
CPU time 1.38 seconds
Started Mar 31 12:30:28 PM PDT 24
Finished Mar 31 12:30:29 PM PDT 24
Peak memory 197648 kb
Host smart-2bb7f06b-b641-4706-b67e-e784f57f9fac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047319788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.3047319788
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3512574286
Short name T80
Test name
Test status
Simulation time 23352016 ps
CPU time 0.65 seconds
Started Mar 31 12:30:07 PM PDT 24
Finished Mar 31 12:30:08 PM PDT 24
Peak memory 194700 kb
Host smart-dd5a0b3b-c4fe-447d-abf0-7bca33ca7e16
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512574286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.3512574286
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1236899052
Short name T781
Test name
Test status
Simulation time 76051326 ps
CPU time 1.98 seconds
Started Mar 31 12:30:31 PM PDT 24
Finished Mar 31 12:30:33 PM PDT 24
Peak memory 197900 kb
Host smart-f9caa238-1f44-433d-9dd1-6a90df8f2c2f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236899052 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.1236899052
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1326038372
Short name T838
Test name
Test status
Simulation time 22719957 ps
CPU time 0.6 seconds
Started Mar 31 12:30:03 PM PDT 24
Finished Mar 31 12:30:04 PM PDT 24
Peak memory 194280 kb
Host smart-4c9e0163-bf25-402f-a736-5916c1018712
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326038372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.1326038372
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.3924459905
Short name T750
Test name
Test status
Simulation time 43032916 ps
CPU time 0.62 seconds
Started Mar 31 12:30:22 PM PDT 24
Finished Mar 31 12:30:23 PM PDT 24
Peak memory 194020 kb
Host smart-23be5a90-458b-417a-9760-a810bd023cbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924459905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.3924459905
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1083529587
Short name T804
Test name
Test status
Simulation time 70770898 ps
CPU time 0.74 seconds
Started Mar 31 12:30:09 PM PDT 24
Finished Mar 31 12:30:10 PM PDT 24
Peak memory 195956 kb
Host smart-3a98f665-19a9-485a-94f6-5e94d0389698
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083529587 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.1083529587
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.90773522
Short name T784
Test name
Test status
Simulation time 617642049 ps
CPU time 3.11 seconds
Started Mar 31 12:30:04 PM PDT 24
Finished Mar 31 12:30:08 PM PDT 24
Peak memory 197700 kb
Host smart-98f36599-a1cf-4153-bff7-74aba7f59d4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90773522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.90773522
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.4265058652
Short name T799
Test name
Test status
Simulation time 214760067 ps
CPU time 1.39 seconds
Started Mar 31 12:30:04 PM PDT 24
Finished Mar 31 12:30:05 PM PDT 24
Peak memory 197716 kb
Host smart-ea3e9799-6368-481a-b798-143ab9120eca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265058652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.4265058652
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.3895456898
Short name T793
Test name
Test status
Simulation time 72041692 ps
CPU time 0.6 seconds
Started Mar 31 12:30:32 PM PDT 24
Finished Mar 31 12:30:33 PM PDT 24
Peak memory 194040 kb
Host smart-c34c5b1e-c2fe-4573-bcf7-f3d5f2c73af8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895456898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.3895456898
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.1348110077
Short name T840
Test name
Test status
Simulation time 14057128 ps
CPU time 0.56 seconds
Started Mar 31 12:30:42 PM PDT 24
Finished Mar 31 12:30:42 PM PDT 24
Peak memory 194036 kb
Host smart-b8da39ec-5bf8-4603-a6ef-0d64882bb14f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348110077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.1348110077
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.2150343788
Short name T728
Test name
Test status
Simulation time 43736447 ps
CPU time 0.58 seconds
Started Mar 31 12:30:37 PM PDT 24
Finished Mar 31 12:30:38 PM PDT 24
Peak memory 192692 kb
Host smart-586dd122-5b6b-4241-858a-e0a8089002fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150343788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.2150343788
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.649793723
Short name T746
Test name
Test status
Simulation time 39652257 ps
CPU time 0.57 seconds
Started Mar 31 12:30:37 PM PDT 24
Finished Mar 31 12:30:37 PM PDT 24
Peak memory 193272 kb
Host smart-d5aedfc6-6d81-4d9a-a39a-cb7b64167172
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649793723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.649793723
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.2181987968
Short name T823
Test name
Test status
Simulation time 21289362 ps
CPU time 0.58 seconds
Started Mar 31 12:30:51 PM PDT 24
Finished Mar 31 12:30:51 PM PDT 24
Peak memory 193384 kb
Host smart-1f250a1c-ed77-40ab-96a2-7b32e18c4015
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181987968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.2181987968
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.1991959346
Short name T733
Test name
Test status
Simulation time 36072997 ps
CPU time 0.57 seconds
Started Mar 31 12:30:39 PM PDT 24
Finished Mar 31 12:30:39 PM PDT 24
Peak memory 194004 kb
Host smart-cb107cc7-acf7-42f8-a2d5-62a66bdce4e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991959346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1991959346
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.2044597544
Short name T752
Test name
Test status
Simulation time 65498451 ps
CPU time 0.57 seconds
Started Mar 31 12:30:37 PM PDT 24
Finished Mar 31 12:30:38 PM PDT 24
Peak memory 194112 kb
Host smart-8dad7cc9-5061-4b6a-b45d-7ff016e1ab89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044597544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.2044597544
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.435056233
Short name T796
Test name
Test status
Simulation time 15669033 ps
CPU time 0.6 seconds
Started Mar 31 12:30:31 PM PDT 24
Finished Mar 31 12:30:32 PM PDT 24
Peak memory 193988 kb
Host smart-d4765b86-e42d-41c9-9f8b-e5942166b4c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435056233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.435056233
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.2158800698
Short name T761
Test name
Test status
Simulation time 44968213 ps
CPU time 0.57 seconds
Started Mar 31 12:30:34 PM PDT 24
Finished Mar 31 12:30:35 PM PDT 24
Peak memory 193440 kb
Host smart-4e3e283e-bce7-4cf0-8449-acaba98d12a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158800698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.2158800698
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.2301521119
Short name T806
Test name
Test status
Simulation time 15202693 ps
CPU time 0.62 seconds
Started Mar 31 12:30:32 PM PDT 24
Finished Mar 31 12:30:33 PM PDT 24
Peak memory 193416 kb
Host smart-67953a44-fa24-4da3-8823-b307a6acef52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301521119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.2301521119
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.470573986
Short name T810
Test name
Test status
Simulation time 41435612 ps
CPU time 1.07 seconds
Started Mar 31 12:30:19 PM PDT 24
Finished Mar 31 12:30:20 PM PDT 24
Peak memory 197660 kb
Host smart-2b3158c3-c5fc-4f0e-bc40-ecc36d48643c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470573986 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.470573986
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.4094525170
Short name T811
Test name
Test status
Simulation time 34028965 ps
CPU time 0.64 seconds
Started Mar 31 12:30:21 PM PDT 24
Finished Mar 31 12:30:22 PM PDT 24
Peak memory 195224 kb
Host smart-159fb20b-7a3f-449f-8e9e-decfedd19697
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094525170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.4094525170
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.1950904903
Short name T780
Test name
Test status
Simulation time 48299979 ps
CPU time 0.59 seconds
Started Mar 31 12:30:28 PM PDT 24
Finished Mar 31 12:30:29 PM PDT 24
Peak memory 193368 kb
Host smart-c802cc5b-3627-40fc-b62a-309e0f23fae7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950904903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.1950904903
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.642327511
Short name T789
Test name
Test status
Simulation time 43884497 ps
CPU time 0.69 seconds
Started Mar 31 12:30:23 PM PDT 24
Finished Mar 31 12:30:24 PM PDT 24
Peak memory 194652 kb
Host smart-4e3c6fae-a33e-4f97-ab7c-148eea0c6b53
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642327511 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 5.gpio_same_csr_outstanding.642327511
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2457629676
Short name T724
Test name
Test status
Simulation time 409068653 ps
CPU time 1.63 seconds
Started Mar 31 12:30:17 PM PDT 24
Finished Mar 31 12:30:19 PM PDT 24
Peak memory 197824 kb
Host smart-4d72d32d-a98e-4578-87f1-5d6ba325ab56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457629676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.2457629676
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3001641520
Short name T43
Test name
Test status
Simulation time 508754733 ps
CPU time 1.13 seconds
Started Mar 31 12:30:16 PM PDT 24
Finished Mar 31 12:30:18 PM PDT 24
Peak memory 197688 kb
Host smart-23d90660-29e2-4b7b-a340-abdff2b6b62a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001641520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.3001641520
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2061248229
Short name T731
Test name
Test status
Simulation time 46045276 ps
CPU time 0.87 seconds
Started Mar 31 12:30:22 PM PDT 24
Finished Mar 31 12:30:23 PM PDT 24
Peak memory 197656 kb
Host smart-29ebf488-b212-4c82-87bd-c178a3e81adb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061248229 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.2061248229
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.418858920
Short name T832
Test name
Test status
Simulation time 48174000 ps
CPU time 0.6 seconds
Started Mar 31 12:30:24 PM PDT 24
Finished Mar 31 12:30:24 PM PDT 24
Peak memory 194344 kb
Host smart-9453e476-e026-41eb-8c55-d705212e173d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418858920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_
csr_rw.418858920
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.3788949167
Short name T822
Test name
Test status
Simulation time 53800435 ps
CPU time 0.67 seconds
Started Mar 31 12:30:19 PM PDT 24
Finished Mar 31 12:30:21 PM PDT 24
Peak memory 193404 kb
Host smart-b6443e66-4d6d-4c0d-a84c-b9ace8e3b6e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788949167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.3788949167
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1239331562
Short name T87
Test name
Test status
Simulation time 56750713 ps
CPU time 0.69 seconds
Started Mar 31 12:30:28 PM PDT 24
Finished Mar 31 12:30:29 PM PDT 24
Peak memory 195328 kb
Host smart-79dafd8f-70fc-4c8c-a213-7a78c1d259e2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239331562 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.1239331562
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.296721699
Short name T749
Test name
Test status
Simulation time 754029784 ps
CPU time 3.12 seconds
Started Mar 31 12:30:33 PM PDT 24
Finished Mar 31 12:30:36 PM PDT 24
Peak memory 197764 kb
Host smart-7a4d413b-0f6f-486d-8ecd-a2f25111e725
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296721699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.296721699
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.256150507
Short name T48
Test name
Test status
Simulation time 148098996 ps
CPU time 1.13 seconds
Started Mar 31 12:30:21 PM PDT 24
Finished Mar 31 12:30:23 PM PDT 24
Peak memory 197664 kb
Host smart-79193f96-4536-4f16-b51a-47dbd0403df2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256150507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.gpio_tl_intg_err.256150507
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1556941060
Short name T778
Test name
Test status
Simulation time 71118245 ps
CPU time 0.83 seconds
Started Mar 31 12:30:26 PM PDT 24
Finished Mar 31 12:30:27 PM PDT 24
Peak memory 197616 kb
Host smart-87aa4bdb-4432-4f61-b1f0-1b2ce38d6984
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556941060 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.1556941060
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.29512648
Short name T70
Test name
Test status
Simulation time 46290127 ps
CPU time 0.6 seconds
Started Mar 31 12:30:18 PM PDT 24
Finished Mar 31 12:30:19 PM PDT 24
Peak memory 194460 kb
Host smart-104615ae-5741-40ab-92a2-4da01ebefc8f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29512648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_c
sr_rw.29512648
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.966977514
Short name T762
Test name
Test status
Simulation time 39582345 ps
CPU time 0.65 seconds
Started Mar 31 12:30:26 PM PDT 24
Finished Mar 31 12:30:27 PM PDT 24
Peak memory 194012 kb
Host smart-11aa9a9e-e88b-473c-806d-abe16e1bc0eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966977514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.966977514
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3703738664
Short name T836
Test name
Test status
Simulation time 37341740 ps
CPU time 0.82 seconds
Started Mar 31 12:30:05 PM PDT 24
Finished Mar 31 12:30:06 PM PDT 24
Peak memory 196048 kb
Host smart-51d64916-9412-48c7-af04-da751edb0229
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703738664 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.3703738664
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.671792131
Short name T729
Test name
Test status
Simulation time 209267046 ps
CPU time 2.28 seconds
Started Mar 31 12:30:20 PM PDT 24
Finished Mar 31 12:30:23 PM PDT 24
Peak memory 197736 kb
Host smart-9a175985-512e-4daa-ac27-78d1b590e599
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671792131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.671792131
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.736875760
Short name T795
Test name
Test status
Simulation time 144829159 ps
CPU time 1.49 seconds
Started Mar 31 12:30:28 PM PDT 24
Finished Mar 31 12:30:29 PM PDT 24
Peak memory 197776 kb
Host smart-bb51a431-3d2d-4315-a34b-06204459775b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736875760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.gpio_tl_intg_err.736875760
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.126353748
Short name T717
Test name
Test status
Simulation time 19612552 ps
CPU time 0.87 seconds
Started Mar 31 12:30:29 PM PDT 24
Finished Mar 31 12:30:30 PM PDT 24
Peak memory 197628 kb
Host smart-2c6cd46b-1681-4fa5-93bc-9e498d86d5b3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126353748 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.126353748
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3662533615
Short name T783
Test name
Test status
Simulation time 16455217 ps
CPU time 0.62 seconds
Started Mar 31 12:30:06 PM PDT 24
Finished Mar 31 12:30:07 PM PDT 24
Peak memory 194720 kb
Host smart-fa0d9ccd-3111-434c-8b11-3f90de832962
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662533615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.3662533615
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.2419377761
Short name T791
Test name
Test status
Simulation time 41044341 ps
CPU time 0.58 seconds
Started Mar 31 12:30:04 PM PDT 24
Finished Mar 31 12:30:05 PM PDT 24
Peak memory 193304 kb
Host smart-d1df25bc-9828-48f2-be51-f05aa5ad172a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419377761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.2419377761
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.2630583746
Short name T785
Test name
Test status
Simulation time 30914946 ps
CPU time 0.7 seconds
Started Mar 31 12:30:24 PM PDT 24
Finished Mar 31 12:30:24 PM PDT 24
Peak memory 194892 kb
Host smart-836d55bf-08bc-4df2-9187-ce53fa1739d7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630583746 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.2630583746
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1543553278
Short name T824
Test name
Test status
Simulation time 200349415 ps
CPU time 1.88 seconds
Started Mar 31 12:30:23 PM PDT 24
Finished Mar 31 12:30:25 PM PDT 24
Peak memory 197712 kb
Host smart-d40b10e7-2d5b-421b-bc3a-bffeb923dd72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543553278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.1543553278
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3500275410
Short name T47
Test name
Test status
Simulation time 149137164 ps
CPU time 0.87 seconds
Started Mar 31 12:30:24 PM PDT 24
Finished Mar 31 12:30:25 PM PDT 24
Peak memory 196820 kb
Host smart-26fd9c1f-52a2-492d-b8ee-4a078b8f0c2e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500275410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.3500275410
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3436644752
Short name T835
Test name
Test status
Simulation time 188836378 ps
CPU time 0.91 seconds
Started Mar 31 12:30:28 PM PDT 24
Finished Mar 31 12:30:29 PM PDT 24
Peak memory 197532 kb
Host smart-5064f815-dd40-4889-9ea8-ad94ae28eab1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436644752 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.3436644752
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2177963680
Short name T741
Test name
Test status
Simulation time 15302019 ps
CPU time 0.65 seconds
Started Mar 31 12:30:28 PM PDT 24
Finished Mar 31 12:30:29 PM PDT 24
Peak memory 194516 kb
Host smart-5d8bf557-b004-4cfc-81ba-70f1abadbef7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177963680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.2177963680
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.1448748379
Short name T771
Test name
Test status
Simulation time 10590682 ps
CPU time 0.58 seconds
Started Mar 31 12:30:26 PM PDT 24
Finished Mar 31 12:30:27 PM PDT 24
Peak memory 193420 kb
Host smart-bdffa1eb-a5a3-4557-949e-4a4198256e33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448748379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.1448748379
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2290476689
Short name T772
Test name
Test status
Simulation time 20748259 ps
CPU time 0.66 seconds
Started Mar 31 12:30:11 PM PDT 24
Finished Mar 31 12:30:12 PM PDT 24
Peak memory 194468 kb
Host smart-11732f24-88d8-429a-82c4-284d01a315d4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290476689 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.2290476689
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1064423211
Short name T730
Test name
Test status
Simulation time 118897512 ps
CPU time 1.43 seconds
Started Mar 31 12:30:25 PM PDT 24
Finished Mar 31 12:30:27 PM PDT 24
Peak memory 197776 kb
Host smart-2ebd2f41-1f52-43df-8f64-af427f0bb939
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064423211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.1064423211
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3360454589
Short name T827
Test name
Test status
Simulation time 349878975 ps
CPU time 1.41 seconds
Started Mar 31 12:30:28 PM PDT 24
Finished Mar 31 12:30:30 PM PDT 24
Peak memory 197684 kb
Host smart-3464d05a-f4b8-49fb-9951-ad727ba0db88
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360454589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.3360454589
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.2464528924
Short name T391
Test name
Test status
Simulation time 39730994 ps
CPU time 0.92 seconds
Started Mar 31 12:37:37 PM PDT 24
Finished Mar 31 12:37:39 PM PDT 24
Peak memory 196324 kb
Host smart-47ad2361-dfe9-4791-9f00-732ae1c4d5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464528924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.2464528924
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.4062481491
Short name T131
Test name
Test status
Simulation time 672304684 ps
CPU time 9.39 seconds
Started Mar 31 12:37:33 PM PDT 24
Finished Mar 31 12:37:42 PM PDT 24
Peak memory 196792 kb
Host smart-e10ce75f-04be-4951-80af-63a12decfde7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062481491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.4062481491
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.260026619
Short name T436
Test name
Test status
Simulation time 99932809 ps
CPU time 0.68 seconds
Started Mar 31 12:37:38 PM PDT 24
Finished Mar 31 12:37:39 PM PDT 24
Peak memory 194708 kb
Host smart-f8bdb495-96f3-4788-a994-b78ae9f6926b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260026619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.260026619
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.717449984
Short name T154
Test name
Test status
Simulation time 503541712 ps
CPU time 1.25 seconds
Started Mar 31 12:37:34 PM PDT 24
Finished Mar 31 12:37:39 PM PDT 24
Peak memory 196568 kb
Host smart-3c874d4c-2d73-49fa-9fba-9b5e12c9c998
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717449984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.717449984
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.1604211804
Short name T66
Test name
Test status
Simulation time 66045233 ps
CPU time 2.61 seconds
Started Mar 31 12:37:33 PM PDT 24
Finished Mar 31 12:37:36 PM PDT 24
Peak memory 197968 kb
Host smart-4284d81a-cd23-422c-8a71-192d26045d0b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604211804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.1604211804
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.4031158516
Short name T265
Test name
Test status
Simulation time 277682846 ps
CPU time 1.73 seconds
Started Mar 31 12:37:39 PM PDT 24
Finished Mar 31 12:37:41 PM PDT 24
Peak memory 196040 kb
Host smart-510e61e0-560a-4361-acfa-928cf95bc205
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031158516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
4031158516
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.2125631562
Short name T445
Test name
Test status
Simulation time 30377138 ps
CPU time 1.04 seconds
Started Mar 31 12:37:29 PM PDT 24
Finished Mar 31 12:37:30 PM PDT 24
Peak memory 195972 kb
Host smart-8a9ac8b5-3a41-447b-a25f-e08eeebf826d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125631562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.2125631562
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.2809662355
Short name T273
Test name
Test status
Simulation time 207062688 ps
CPU time 1.08 seconds
Started Mar 31 12:37:31 PM PDT 24
Finished Mar 31 12:37:32 PM PDT 24
Peak memory 196676 kb
Host smart-cfee281a-3b80-4be5-a1dc-412dca018168
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809662355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.2809662355
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2236641337
Short name T659
Test name
Test status
Simulation time 1025128080 ps
CPU time 3.55 seconds
Started Mar 31 12:37:38 PM PDT 24
Finished Mar 31 12:37:42 PM PDT 24
Peak memory 197828 kb
Host smart-7f0dffea-71e8-4d2a-8a99-7966b2b909a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236641337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.2236641337
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.3332037993
Short name T39
Test name
Test status
Simulation time 33600644 ps
CPU time 0.77 seconds
Started Mar 31 12:37:38 PM PDT 24
Finished Mar 31 12:37:39 PM PDT 24
Peak memory 213624 kb
Host smart-699283da-1083-4593-8088-f01cf17212a4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332037993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.3332037993
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.2995496683
Short name T122
Test name
Test status
Simulation time 68144915 ps
CPU time 1.13 seconds
Started Mar 31 12:37:51 PM PDT 24
Finished Mar 31 12:37:53 PM PDT 24
Peak memory 195608 kb
Host smart-555bf98e-ba58-429b-bf05-baa2debbd03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995496683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.2995496683
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.4163802825
Short name T206
Test name
Test status
Simulation time 784504256 ps
CPU time 1.12 seconds
Started Mar 31 12:37:55 PM PDT 24
Finished Mar 31 12:37:56 PM PDT 24
Peak memory 195632 kb
Host smart-3a612863-008a-41dc-9b46-591142483bef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163802825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.4163802825
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.1305179384
Short name T456
Test name
Test status
Simulation time 16752403768 ps
CPU time 86.61 seconds
Started Mar 31 12:37:46 PM PDT 24
Finished Mar 31 12:39:12 PM PDT 24
Peak memory 198192 kb
Host smart-ca203df5-9660-4f99-850b-4babe9220aa1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305179384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.1305179384
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.2165810125
Short name T537
Test name
Test status
Simulation time 20101530 ps
CPU time 0.59 seconds
Started Mar 31 12:37:36 PM PDT 24
Finished Mar 31 12:37:37 PM PDT 24
Peak memory 193924 kb
Host smart-4aa88b46-97ef-4b60-8f71-d4fffb7e5451
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165810125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.2165810125
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.3388327830
Short name T413
Test name
Test status
Simulation time 26822227 ps
CPU time 0.58 seconds
Started Mar 31 12:37:33 PM PDT 24
Finished Mar 31 12:37:34 PM PDT 24
Peak memory 193984 kb
Host smart-473531a0-93ff-4165-95dc-9116a85c06a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388327830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.3388327830
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.1428010964
Short name T541
Test name
Test status
Simulation time 1109425260 ps
CPU time 25.84 seconds
Started Mar 31 12:38:00 PM PDT 24
Finished Mar 31 12:38:26 PM PDT 24
Peak memory 197896 kb
Host smart-055fbc7c-8f00-4394-9bbd-c40dd9bf1060
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428010964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.1428010964
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.1091479052
Short name T478
Test name
Test status
Simulation time 47410942 ps
CPU time 0.66 seconds
Started Mar 31 12:37:58 PM PDT 24
Finished Mar 31 12:37:59 PM PDT 24
Peak memory 194540 kb
Host smart-43e90cbe-0831-420c-92f5-5c87ed07cbda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091479052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.1091479052
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.1829548145
Short name T266
Test name
Test status
Simulation time 66765519 ps
CPU time 1.13 seconds
Started Mar 31 12:37:37 PM PDT 24
Finished Mar 31 12:37:38 PM PDT 24
Peak memory 195984 kb
Host smart-4a8ffc4a-9fd6-48ef-97a3-c1a2518f242a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829548145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.1829548145
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.3036333875
Short name T594
Test name
Test status
Simulation time 64911892 ps
CPU time 2.54 seconds
Started Mar 31 12:37:49 PM PDT 24
Finished Mar 31 12:37:52 PM PDT 24
Peak memory 197808 kb
Host smart-f3e12f62-6788-4998-8a97-fe8d05b9d47d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036333875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.3036333875
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.2353067358
Short name T690
Test name
Test status
Simulation time 334169075 ps
CPU time 1.76 seconds
Started Mar 31 12:37:36 PM PDT 24
Finished Mar 31 12:37:38 PM PDT 24
Peak memory 196824 kb
Host smart-67c5a5c4-b040-4c72-883c-6aab0581db47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353067358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
2353067358
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.1309334990
Short name T51
Test name
Test status
Simulation time 64685939 ps
CPU time 0.76 seconds
Started Mar 31 12:37:39 PM PDT 24
Finished Mar 31 12:37:40 PM PDT 24
Peak memory 195016 kb
Host smart-33ed20f9-5ff2-41e8-9154-037324963139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309334990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.1309334990
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.771791939
Short name T194
Test name
Test status
Simulation time 219772836 ps
CPU time 1.24 seconds
Started Mar 31 12:37:57 PM PDT 24
Finished Mar 31 12:37:59 PM PDT 24
Peak memory 198060 kb
Host smart-76a28fc4-6b5a-46cd-a1c9-999f509b061b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771791939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup_
pulldown.771791939
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.438657053
Short name T355
Test name
Test status
Simulation time 309761501 ps
CPU time 4.29 seconds
Started Mar 31 12:37:39 PM PDT 24
Finished Mar 31 12:37:43 PM PDT 24
Peak memory 197936 kb
Host smart-1126439d-6efb-4893-9b49-f949732c0eb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438657053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand
om_long_reg_writes_reg_reads.438657053
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.3578714545
Short name T40
Test name
Test status
Simulation time 38033427 ps
CPU time 0.85 seconds
Started Mar 31 12:37:36 PM PDT 24
Finished Mar 31 12:37:37 PM PDT 24
Peak memory 213700 kb
Host smart-a1b79d39-f994-43bb-9fb5-65ff08a77b87
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578714545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.3578714545
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.2527934478
Short name T504
Test name
Test status
Simulation time 230309650 ps
CPU time 1.19 seconds
Started Mar 31 12:37:38 PM PDT 24
Finished Mar 31 12:37:40 PM PDT 24
Peak memory 197096 kb
Host smart-8a916baa-f2d2-4f52-a2e4-0cfdd6a3fe29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527934478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2527934478
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.3740120882
Short name T279
Test name
Test status
Simulation time 320717552 ps
CPU time 1.43 seconds
Started Mar 31 12:37:40 PM PDT 24
Finished Mar 31 12:37:41 PM PDT 24
Peak memory 196648 kb
Host smart-1db4eddf-458a-468c-9f4e-3e299f3c1dc7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740120882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.3740120882
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.332981244
Short name T640
Test name
Test status
Simulation time 14619228155 ps
CPU time 95.92 seconds
Started Mar 31 12:37:38 PM PDT 24
Finished Mar 31 12:39:14 PM PDT 24
Peak memory 198104 kb
Host smart-3323dd93-b5e0-4db1-bbbb-1b96d8fdb97f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332981244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gp
io_stress_all.332981244
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.191868660
Short name T677
Test name
Test status
Simulation time 34094783 ps
CPU time 0.57 seconds
Started Mar 31 12:38:05 PM PDT 24
Finished Mar 31 12:38:06 PM PDT 24
Peak memory 193832 kb
Host smart-d2e48e84-d128-432f-b097-624f985a7658
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191868660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.191868660
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.1449623908
Short name T686
Test name
Test status
Simulation time 85012264 ps
CPU time 0.81 seconds
Started Mar 31 12:38:18 PM PDT 24
Finished Mar 31 12:38:19 PM PDT 24
Peak memory 196476 kb
Host smart-2cf8834a-c817-44d0-821b-97953be6d78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449623908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.1449623908
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.2936591434
Short name T230
Test name
Test status
Simulation time 3068588677 ps
CPU time 18.96 seconds
Started Mar 31 12:38:35 PM PDT 24
Finished Mar 31 12:38:54 PM PDT 24
Peak memory 196596 kb
Host smart-d757b2e7-6834-4ca8-a117-cf465eff039b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936591434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.2936591434
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.4224739724
Short name T339
Test name
Test status
Simulation time 368647151 ps
CPU time 1.03 seconds
Started Mar 31 12:38:23 PM PDT 24
Finished Mar 31 12:38:24 PM PDT 24
Peak memory 197896 kb
Host smart-286c49f2-0d20-4945-9154-7a4dbbfb5095
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224739724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.4224739724
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.3729154495
Short name T439
Test name
Test status
Simulation time 158267391 ps
CPU time 1.28 seconds
Started Mar 31 12:38:04 PM PDT 24
Finished Mar 31 12:38:05 PM PDT 24
Peak memory 196912 kb
Host smart-cc778040-67e4-402e-bd3b-e511965b3512
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729154495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.3729154495
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.1992613349
Short name T559
Test name
Test status
Simulation time 332155118 ps
CPU time 2.03 seconds
Started Mar 31 12:38:04 PM PDT 24
Finished Mar 31 12:38:06 PM PDT 24
Peak memory 197972 kb
Host smart-a059751b-e2ee-41df-a02e-209b3f5ccc7b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992613349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.1992613349
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.2312842423
Short name T269
Test name
Test status
Simulation time 1775321963 ps
CPU time 2.53 seconds
Started Mar 31 12:38:04 PM PDT 24
Finished Mar 31 12:38:07 PM PDT 24
Peak memory 196804 kb
Host smart-58292a83-5f18-45a1-9bdc-e103772a8b0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312842423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.2312842423
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.1738071781
Short name T523
Test name
Test status
Simulation time 27833108 ps
CPU time 0.91 seconds
Started Mar 31 12:38:12 PM PDT 24
Finished Mar 31 12:38:13 PM PDT 24
Peak memory 196648 kb
Host smart-7a659c19-7f55-42ba-bdc3-2e6b3cfb41eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738071781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.1738071781
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.1148260419
Short name T101
Test name
Test status
Simulation time 101595374 ps
CPU time 0.8 seconds
Started Mar 31 12:38:03 PM PDT 24
Finished Mar 31 12:38:04 PM PDT 24
Peak memory 196308 kb
Host smart-c9f9edb5-e19a-47af-80f4-a15abf902288
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148260419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.1148260419
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.3735385566
Short name T146
Test name
Test status
Simulation time 221661790 ps
CPU time 2.83 seconds
Started Mar 31 12:38:20 PM PDT 24
Finished Mar 31 12:38:23 PM PDT 24
Peak memory 197924 kb
Host smart-77fdde34-d7a5-4e71-ab99-afbebc936ef0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735385566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.3735385566
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.1090250680
Short name T341
Test name
Test status
Simulation time 100099400 ps
CPU time 1.31 seconds
Started Mar 31 12:38:18 PM PDT 24
Finished Mar 31 12:38:20 PM PDT 24
Peak memory 197956 kb
Host smart-e89e4bd0-ee4b-432b-94b6-509da7c97fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090250680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.1090250680
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.2805565093
Short name T609
Test name
Test status
Simulation time 38782282 ps
CPU time 0.97 seconds
Started Mar 31 12:38:06 PM PDT 24
Finished Mar 31 12:38:07 PM PDT 24
Peak memory 195696 kb
Host smart-8bc7a062-76a6-4356-92a6-26a38a4852d0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805565093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.2805565093
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.3463489779
Short name T607
Test name
Test status
Simulation time 5379131051 ps
CPU time 141.01 seconds
Started Mar 31 12:38:20 PM PDT 24
Finished Mar 31 12:40:41 PM PDT 24
Peak memory 198164 kb
Host smart-430b2fda-21af-4ef9-aee4-4f550fbf9b03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463489779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.3463489779
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.894706195
Short name T638
Test name
Test status
Simulation time 52386823 ps
CPU time 0.61 seconds
Started Mar 31 12:38:24 PM PDT 24
Finished Mar 31 12:38:28 PM PDT 24
Peak memory 194120 kb
Host smart-97bbec53-a9b6-40cb-9d98-0ab31df7db3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894706195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.894706195
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.3821135616
Short name T514
Test name
Test status
Simulation time 69288986 ps
CPU time 0.79 seconds
Started Mar 31 12:38:07 PM PDT 24
Finished Mar 31 12:38:08 PM PDT 24
Peak memory 195392 kb
Host smart-665f9d64-47f2-482f-8620-4f9e48a243ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821135616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.3821135616
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.2117629906
Short name T242
Test name
Test status
Simulation time 1158145937 ps
CPU time 5.74 seconds
Started Mar 31 12:38:22 PM PDT 24
Finished Mar 31 12:38:28 PM PDT 24
Peak memory 196232 kb
Host smart-9e6ae6a0-9c31-4682-9818-3e42a72fa3f3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117629906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.2117629906
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.1325729412
Short name T306
Test name
Test status
Simulation time 124227967 ps
CPU time 0.72 seconds
Started Mar 31 12:38:09 PM PDT 24
Finished Mar 31 12:38:10 PM PDT 24
Peak memory 194692 kb
Host smart-04ebf739-04af-4142-812b-64206247b235
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325729412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.1325729412
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.445514489
Short name T253
Test name
Test status
Simulation time 110067552 ps
CPU time 1.5 seconds
Started Mar 31 12:38:01 PM PDT 24
Finished Mar 31 12:38:02 PM PDT 24
Peak memory 197048 kb
Host smart-3b074a31-b1e6-4de3-aa53-a439d7279c6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445514489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.445514489
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.405233226
Short name T477
Test name
Test status
Simulation time 28474002 ps
CPU time 1 seconds
Started Mar 31 12:38:22 PM PDT 24
Finished Mar 31 12:38:23 PM PDT 24
Peak memory 195524 kb
Host smart-dff6f5d1-4daf-4c6a-814f-1f72a82b5ce9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405233226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger.
405233226
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.1312693019
Short name T301
Test name
Test status
Simulation time 212349095 ps
CPU time 1.11 seconds
Started Mar 31 12:38:16 PM PDT 24
Finished Mar 31 12:38:18 PM PDT 24
Peak memory 195960 kb
Host smart-174b2800-0535-49d2-8f03-ad963340556f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312693019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.1312693019
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.3706897606
Short name T458
Test name
Test status
Simulation time 67586582 ps
CPU time 0.77 seconds
Started Mar 31 12:38:09 PM PDT 24
Finished Mar 31 12:38:11 PM PDT 24
Peak memory 196600 kb
Host smart-0fcc0fd5-c5b8-4473-a6a9-f7ec3ddaf96a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706897606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.3706897606
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.3701110185
Short name T708
Test name
Test status
Simulation time 234378326 ps
CPU time 1.54 seconds
Started Mar 31 12:38:03 PM PDT 24
Finished Mar 31 12:38:05 PM PDT 24
Peak memory 198000 kb
Host smart-307db528-2db9-4f22-8057-706f92758bd1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701110185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.3701110185
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.2868660647
Short name T170
Test name
Test status
Simulation time 445677288 ps
CPU time 1.36 seconds
Started Mar 31 12:38:16 PM PDT 24
Finished Mar 31 12:38:18 PM PDT 24
Peak memory 195484 kb
Host smart-e854b957-927a-4341-a43f-1f8e1df99312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868660647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.2868660647
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.1048055052
Short name T289
Test name
Test status
Simulation time 128401702 ps
CPU time 1.03 seconds
Started Mar 31 12:38:05 PM PDT 24
Finished Mar 31 12:38:07 PM PDT 24
Peak memory 195808 kb
Host smart-5f4ca8e9-b87b-488c-a20d-a6cdb001d01d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048055052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.1048055052
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.689569852
Short name T8
Test name
Test status
Simulation time 4362723132 ps
CPU time 25.46 seconds
Started Mar 31 12:38:17 PM PDT 24
Finished Mar 31 12:38:42 PM PDT 24
Peak memory 198204 kb
Host smart-8e509d32-4963-43e3-a073-0d75a8683b1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689569852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.g
pio_stress_all.689569852
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.2108529020
Short name T534
Test name
Test status
Simulation time 23034445 ps
CPU time 0.58 seconds
Started Mar 31 12:38:18 PM PDT 24
Finished Mar 31 12:38:19 PM PDT 24
Peak memory 194112 kb
Host smart-b224e3c9-445d-45df-9f5c-6426456be33e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108529020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.2108529020
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.1899086981
Short name T95
Test name
Test status
Simulation time 28855832 ps
CPU time 0.73 seconds
Started Mar 31 12:38:08 PM PDT 24
Finished Mar 31 12:38:10 PM PDT 24
Peak memory 195312 kb
Host smart-08a186e0-3606-4bf9-b809-6a175ab840e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899086981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.1899086981
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.1968851712
Short name T583
Test name
Test status
Simulation time 439240585 ps
CPU time 19.57 seconds
Started Mar 31 12:38:24 PM PDT 24
Finished Mar 31 12:38:44 PM PDT 24
Peak memory 196932 kb
Host smart-80731b5f-6572-46b5-9418-6006fa807144
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968851712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.1968851712
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.336343620
Short name T572
Test name
Test status
Simulation time 103053900 ps
CPU time 0.85 seconds
Started Mar 31 12:38:09 PM PDT 24
Finished Mar 31 12:38:10 PM PDT 24
Peak memory 196024 kb
Host smart-93923ccc-e721-4d26-9106-533e0c6d3624
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336343620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.336343620
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.2863994679
Short name T402
Test name
Test status
Simulation time 99284835 ps
CPU time 1.37 seconds
Started Mar 31 12:38:05 PM PDT 24
Finished Mar 31 12:38:07 PM PDT 24
Peak memory 197156 kb
Host smart-1905c5dc-e051-484e-a1c9-25797d195080
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863994679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.2863994679
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.3999290445
Short name T435
Test name
Test status
Simulation time 130079144 ps
CPU time 1.49 seconds
Started Mar 31 12:38:26 PM PDT 24
Finished Mar 31 12:38:29 PM PDT 24
Peak memory 196272 kb
Host smart-3b3dbbee-14aa-4d7d-9d91-bd4caaa90890
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999290445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.3999290445
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.867987852
Short name T243
Test name
Test status
Simulation time 121255240 ps
CPU time 3.18 seconds
Started Mar 31 12:38:24 PM PDT 24
Finished Mar 31 12:38:28 PM PDT 24
Peak memory 197160 kb
Host smart-bc3395d8-a1c0-4b3c-b749-495f7b89bed1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867987852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger.
867987852
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.1737728126
Short name T493
Test name
Test status
Simulation time 272491614 ps
CPU time 1.2 seconds
Started Mar 31 12:38:24 PM PDT 24
Finished Mar 31 12:38:26 PM PDT 24
Peak memory 197124 kb
Host smart-6548094c-486e-4363-8dc5-79e85090847f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737728126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.1737728126
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.3024247257
Short name T239
Test name
Test status
Simulation time 103834676 ps
CPU time 0.7 seconds
Started Mar 31 12:38:21 PM PDT 24
Finished Mar 31 12:38:22 PM PDT 24
Peak memory 195304 kb
Host smart-128169ee-e0d3-4636-b486-b91d8be32695
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024247257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.3024247257
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.3893468560
Short name T713
Test name
Test status
Simulation time 859587113 ps
CPU time 3.61 seconds
Started Mar 31 12:38:17 PM PDT 24
Finished Mar 31 12:38:21 PM PDT 24
Peak memory 197932 kb
Host smart-12ab2e4e-bda4-4f65-868a-97cf61b0d9f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893468560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.3893468560
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.3154346581
Short name T346
Test name
Test status
Simulation time 128000521 ps
CPU time 0.89 seconds
Started Mar 31 12:38:02 PM PDT 24
Finished Mar 31 12:38:03 PM PDT 24
Peak memory 197272 kb
Host smart-2a3a7865-fa7c-40dd-a3ea-93c97753aff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154346581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.3154346581
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.507126519
Short name T227
Test name
Test status
Simulation time 829743952 ps
CPU time 1.33 seconds
Started Mar 31 12:38:21 PM PDT 24
Finished Mar 31 12:38:22 PM PDT 24
Peak memory 196776 kb
Host smart-4a9fdfe2-89bb-4eb1-a4b6-78ffbdf1da99
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507126519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.507126519
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.2137445743
Short name T474
Test name
Test status
Simulation time 11318168950 ps
CPU time 119.14 seconds
Started Mar 31 12:38:19 PM PDT 24
Finished Mar 31 12:40:18 PM PDT 24
Peak memory 198200 kb
Host smart-3b44c9ce-9e89-4dae-af93-3b090dc0ad22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137445743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.2137445743
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.2022631624
Short name T570
Test name
Test status
Simulation time 11994782 ps
CPU time 0.57 seconds
Started Mar 31 12:38:22 PM PDT 24
Finished Mar 31 12:38:23 PM PDT 24
Peak memory 194168 kb
Host smart-1c8986b3-c5bf-4f53-a257-8448f4abc945
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022631624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.2022631624
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.1574166460
Short name T443
Test name
Test status
Simulation time 79617331 ps
CPU time 0.78 seconds
Started Mar 31 12:38:06 PM PDT 24
Finished Mar 31 12:38:08 PM PDT 24
Peak memory 195372 kb
Host smart-4b8c5666-207f-4e5c-afcb-55693f210f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574166460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.1574166460
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.3703862998
Short name T175
Test name
Test status
Simulation time 872905856 ps
CPU time 12.78 seconds
Started Mar 31 12:38:13 PM PDT 24
Finished Mar 31 12:38:26 PM PDT 24
Peak memory 196756 kb
Host smart-e1519e72-8c40-434d-9cea-251fbe3e77f6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703862998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.3703862998
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.2627365677
Short name T602
Test name
Test status
Simulation time 72067379 ps
CPU time 0.96 seconds
Started Mar 31 12:38:12 PM PDT 24
Finished Mar 31 12:38:13 PM PDT 24
Peak memory 197880 kb
Host smart-d05934b3-f46c-4f88-819c-29a2b405d99f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627365677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.2627365677
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.1040729566
Short name T515
Test name
Test status
Simulation time 412085107 ps
CPU time 1.33 seconds
Started Mar 31 12:38:06 PM PDT 24
Finished Mar 31 12:38:07 PM PDT 24
Peak memory 197120 kb
Host smart-f4cd45aa-74cd-46a8-a932-faee05bf1f31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040729566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.1040729566
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.4224461975
Short name T663
Test name
Test status
Simulation time 140692235 ps
CPU time 1.66 seconds
Started Mar 31 12:38:16 PM PDT 24
Finished Mar 31 12:38:17 PM PDT 24
Peak memory 196472 kb
Host smart-85ce3086-55f9-4fba-a91c-b67acf12069c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224461975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.4224461975
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.4087219212
Short name T148
Test name
Test status
Simulation time 73847279 ps
CPU time 1.76 seconds
Started Mar 31 12:38:09 PM PDT 24
Finished Mar 31 12:38:11 PM PDT 24
Peak memory 195844 kb
Host smart-ba412f98-2984-4df0-b0ef-8267c269db6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087219212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.4087219212
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.1298563058
Short name T277
Test name
Test status
Simulation time 215353092 ps
CPU time 1.08 seconds
Started Mar 31 12:38:18 PM PDT 24
Finished Mar 31 12:38:19 PM PDT 24
Peak memory 195736 kb
Host smart-3a4bcb3a-f994-41e5-9d9f-70ff7eceaf22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298563058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.1298563058
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.2073624708
Short name T695
Test name
Test status
Simulation time 46425902 ps
CPU time 1.08 seconds
Started Mar 31 12:38:18 PM PDT 24
Finished Mar 31 12:38:19 PM PDT 24
Peak memory 195812 kb
Host smart-253908d1-c93c-470a-9400-f78f46d856fc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073624708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.2073624708
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.1164853439
Short name T332
Test name
Test status
Simulation time 1018991354 ps
CPU time 4.36 seconds
Started Mar 31 12:38:07 PM PDT 24
Finished Mar 31 12:38:12 PM PDT 24
Peak memory 197968 kb
Host smart-e3e6e567-4174-4035-a151-18301c612f75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164853439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.1164853439
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.2599671458
Short name T642
Test name
Test status
Simulation time 51759841 ps
CPU time 1.05 seconds
Started Mar 31 12:38:22 PM PDT 24
Finished Mar 31 12:38:23 PM PDT 24
Peak memory 195672 kb
Host smart-6990ecf3-a885-4c61-84d1-745679bff1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599671458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.2599671458
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.254246838
Short name T380
Test name
Test status
Simulation time 155248303 ps
CPU time 1.45 seconds
Started Mar 31 12:38:17 PM PDT 24
Finished Mar 31 12:38:19 PM PDT 24
Peak memory 196364 kb
Host smart-5b6de46c-82fa-4527-a573-c7f2dc3e2ea3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254246838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.254246838
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.1524281792
Short name T486
Test name
Test status
Simulation time 39697001247 ps
CPU time 207.78 seconds
Started Mar 31 12:38:07 PM PDT 24
Finished Mar 31 12:41:36 PM PDT 24
Peak memory 198152 kb
Host smart-c942f845-0d3a-4bb5-a3ab-0039085a029f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524281792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.1524281792
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.2792466494
Short name T699
Test name
Test status
Simulation time 106751471 ps
CPU time 0.6 seconds
Started Mar 31 12:38:11 PM PDT 24
Finished Mar 31 12:38:12 PM PDT 24
Peak memory 194616 kb
Host smart-71a9a311-29b4-42dd-9d18-151eae98e94a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792466494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.2792466494
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.3133750699
Short name T712
Test name
Test status
Simulation time 48086309 ps
CPU time 0.63 seconds
Started Mar 31 12:38:12 PM PDT 24
Finished Mar 31 12:38:12 PM PDT 24
Peak memory 194076 kb
Host smart-b5e5c50f-365f-4231-b686-b2f410865e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133750699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.3133750699
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.1758980007
Short name T507
Test name
Test status
Simulation time 688041899 ps
CPU time 17.97 seconds
Started Mar 31 12:38:23 PM PDT 24
Finished Mar 31 12:38:41 PM PDT 24
Peak memory 196996 kb
Host smart-f78075c2-5fd1-4065-878c-f1ddda4e273f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758980007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.1758980007
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.1477418304
Short name T177
Test name
Test status
Simulation time 132281027 ps
CPU time 1.05 seconds
Started Mar 31 12:38:12 PM PDT 24
Finished Mar 31 12:38:13 PM PDT 24
Peak memory 196688 kb
Host smart-845c08c1-c96d-4c47-b505-6cf3169fcd4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477418304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.1477418304
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.673035809
Short name T256
Test name
Test status
Simulation time 383754504 ps
CPU time 1.58 seconds
Started Mar 31 12:38:23 PM PDT 24
Finished Mar 31 12:38:30 PM PDT 24
Peak memory 198012 kb
Host smart-c98faebc-3302-4744-bce9-e1e6e4d78f6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673035809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.673035809
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.4176641644
Short name T573
Test name
Test status
Simulation time 451947720 ps
CPU time 2.6 seconds
Started Mar 31 12:38:06 PM PDT 24
Finished Mar 31 12:38:09 PM PDT 24
Peak memory 196372 kb
Host smart-8c611215-58ee-4fa6-bb66-517bca568a57
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176641644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.4176641644
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.2784775212
Short name T454
Test name
Test status
Simulation time 62380781 ps
CPU time 1.19 seconds
Started Mar 31 12:38:30 PM PDT 24
Finished Mar 31 12:38:31 PM PDT 24
Peak memory 196968 kb
Host smart-06e33e2f-7362-485c-8029-3f856156af9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784775212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.2784775212
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.3358346687
Short name T231
Test name
Test status
Simulation time 34621502 ps
CPU time 0.84 seconds
Started Mar 31 12:38:08 PM PDT 24
Finished Mar 31 12:38:10 PM PDT 24
Peak memory 195424 kb
Host smart-d5b92f3a-91ad-478f-b079-c107da0b14f3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358346687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.3358346687
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.3844976351
Short name T525
Test name
Test status
Simulation time 236060227 ps
CPU time 4.07 seconds
Started Mar 31 12:38:16 PM PDT 24
Finished Mar 31 12:38:20 PM PDT 24
Peak memory 197968 kb
Host smart-b98099c0-520a-4f3c-b620-9dea64704f61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844976351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.3844976351
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.1556682523
Short name T166
Test name
Test status
Simulation time 81002045 ps
CPU time 1.16 seconds
Started Mar 31 12:38:08 PM PDT 24
Finished Mar 31 12:38:10 PM PDT 24
Peak memory 195824 kb
Host smart-c8d08148-0727-4b48-ba9b-4787822a1789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556682523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.1556682523
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.381473407
Short name T307
Test name
Test status
Simulation time 84564549 ps
CPU time 0.83 seconds
Started Mar 31 12:38:12 PM PDT 24
Finished Mar 31 12:38:13 PM PDT 24
Peak memory 195188 kb
Host smart-3594e02b-8db7-4f74-82f3-46710e31e78a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381473407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.381473407
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.865872609
Short name T645
Test name
Test status
Simulation time 2225026836 ps
CPU time 32.3 seconds
Started Mar 31 12:38:10 PM PDT 24
Finished Mar 31 12:38:42 PM PDT 24
Peak memory 198132 kb
Host smart-68fe2010-055c-4cb6-b4c5-433798c3537a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865872609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.g
pio_stress_all.865872609
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.755661615
Short name T688
Test name
Test status
Simulation time 11472689 ps
CPU time 0.57 seconds
Started Mar 31 12:38:11 PM PDT 24
Finished Mar 31 12:38:11 PM PDT 24
Peak memory 193884 kb
Host smart-7833e197-b94d-441f-b3be-9f285fa37a76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755661615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.755661615
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.3590980962
Short name T298
Test name
Test status
Simulation time 49125213 ps
CPU time 0.94 seconds
Started Mar 31 12:38:10 PM PDT 24
Finished Mar 31 12:38:11 PM PDT 24
Peak memory 196536 kb
Host smart-3a9a308c-3b6b-4fc9-a4bb-3db1b772beba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590980962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.3590980962
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.1830160232
Short name T577
Test name
Test status
Simulation time 799109940 ps
CPU time 18.4 seconds
Started Mar 31 12:38:11 PM PDT 24
Finished Mar 31 12:38:30 PM PDT 24
Peak memory 196252 kb
Host smart-91d35a17-4e72-426c-9a9d-c7538d89770c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830160232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.1830160232
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.1436978389
Short name T633
Test name
Test status
Simulation time 101240158 ps
CPU time 0.77 seconds
Started Mar 31 12:38:19 PM PDT 24
Finished Mar 31 12:38:20 PM PDT 24
Peak memory 195960 kb
Host smart-542a3f32-ec4e-49bb-82ac-f6bd290fe273
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436978389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.1436978389
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.3197433763
Short name T182
Test name
Test status
Simulation time 33417092 ps
CPU time 0.85 seconds
Started Mar 31 12:38:12 PM PDT 24
Finished Mar 31 12:38:13 PM PDT 24
Peak memory 196344 kb
Host smart-34270748-7eec-4e7a-a5d7-63567fc1b0b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197433763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.3197433763
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.2494926554
Short name T481
Test name
Test status
Simulation time 71461923 ps
CPU time 2.9 seconds
Started Mar 31 12:38:21 PM PDT 24
Finished Mar 31 12:38:24 PM PDT 24
Peak memory 198012 kb
Host smart-b1bd9ede-3f90-49ef-adfe-54796ca054f7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494926554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.2494926554
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.1661060560
Short name T470
Test name
Test status
Simulation time 3076412891 ps
CPU time 3.14 seconds
Started Mar 31 12:38:09 PM PDT 24
Finished Mar 31 12:38:13 PM PDT 24
Peak memory 198104 kb
Host smart-d7f3b4ef-a435-4947-a5b2-3b9223f5f004
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661060560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.1661060560
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.2347949108
Short name T608
Test name
Test status
Simulation time 41731755 ps
CPU time 1.04 seconds
Started Mar 31 12:38:12 PM PDT 24
Finished Mar 31 12:38:13 PM PDT 24
Peak memory 196008 kb
Host smart-8bc39950-cb7c-40e0-a8ab-cdb848f249f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347949108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.2347949108
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.2252709806
Short name T506
Test name
Test status
Simulation time 96215041 ps
CPU time 0.74 seconds
Started Mar 31 12:38:12 PM PDT 24
Finished Mar 31 12:38:13 PM PDT 24
Peak memory 195412 kb
Host smart-ccfd284e-de4f-4fa1-a33b-e74d561de47c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252709806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.2252709806
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.4007948645
Short name T669
Test name
Test status
Simulation time 310352169 ps
CPU time 3.77 seconds
Started Mar 31 12:38:18 PM PDT 24
Finished Mar 31 12:38:22 PM PDT 24
Peak memory 197948 kb
Host smart-a83c6412-8696-44c3-b9fa-5381b155f7e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007948645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.4007948645
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.4097852859
Short name T566
Test name
Test status
Simulation time 42582975 ps
CPU time 0.92 seconds
Started Mar 31 12:38:12 PM PDT 24
Finished Mar 31 12:38:13 PM PDT 24
Peak memory 197288 kb
Host smart-8527ee93-4a06-4a50-bd4b-bf5f8674713b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097852859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.4097852859
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.3890529256
Short name T121
Test name
Test status
Simulation time 71251493 ps
CPU time 1.09 seconds
Started Mar 31 12:38:18 PM PDT 24
Finished Mar 31 12:38:19 PM PDT 24
Peak memory 195744 kb
Host smart-3ad01807-69e6-4cf3-9b95-77986ecf734e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890529256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.3890529256
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.1806807880
Short name T536
Test name
Test status
Simulation time 11663658936 ps
CPU time 66.79 seconds
Started Mar 31 12:38:11 PM PDT 24
Finished Mar 31 12:39:18 PM PDT 24
Peak memory 198128 kb
Host smart-57190feb-8605-4688-ba03-c6849f419c87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806807880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.1806807880
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.2113371251
Short name T60
Test name
Test status
Simulation time 54841805788 ps
CPU time 299.29 seconds
Started Mar 31 12:38:13 PM PDT 24
Finished Mar 31 12:43:13 PM PDT 24
Peak memory 198228 kb
Host smart-1f714eab-f29e-48f6-8168-f26efb3d63aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2113371251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.2113371251
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.3779650805
Short name T418
Test name
Test status
Simulation time 18271557 ps
CPU time 0.56 seconds
Started Mar 31 12:38:16 PM PDT 24
Finished Mar 31 12:38:17 PM PDT 24
Peak memory 193880 kb
Host smart-0e7fe466-bbbb-4323-a5f8-5035a22f5158
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779650805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.3779650805
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.4207120696
Short name T357
Test name
Test status
Simulation time 102699125 ps
CPU time 0.95 seconds
Started Mar 31 12:38:17 PM PDT 24
Finished Mar 31 12:38:18 PM PDT 24
Peak memory 195648 kb
Host smart-6a279309-a0d4-4058-915f-8eb838ab5c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207120696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.4207120696
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.3322767983
Short name T665
Test name
Test status
Simulation time 196069082 ps
CPU time 10.17 seconds
Started Mar 31 12:38:13 PM PDT 24
Finished Mar 31 12:38:23 PM PDT 24
Peak memory 196904 kb
Host smart-5ac118bd-f157-48ce-a407-9c574fb36cfe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322767983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.3322767983
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.1706811408
Short name T598
Test name
Test status
Simulation time 32010866 ps
CPU time 0.69 seconds
Started Mar 31 12:38:23 PM PDT 24
Finished Mar 31 12:38:24 PM PDT 24
Peak memory 194832 kb
Host smart-f1ed2a4b-27cb-4be7-8b77-d979aedd927b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706811408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.1706811408
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.3788593998
Short name T226
Test name
Test status
Simulation time 188720847 ps
CPU time 0.92 seconds
Started Mar 31 12:38:18 PM PDT 24
Finished Mar 31 12:38:19 PM PDT 24
Peak memory 196696 kb
Host smart-6ed91f2b-f507-4ac1-9975-58e8aefab907
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788593998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.3788593998
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.62923873
Short name T630
Test name
Test status
Simulation time 1440277984 ps
CPU time 3.54 seconds
Started Mar 31 12:38:24 PM PDT 24
Finished Mar 31 12:38:28 PM PDT 24
Peak memory 198064 kb
Host smart-c432f56d-3cfc-4267-a53a-ebe66f813eab
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62923873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.gpio_intr_with_filter_rand_intr_event.62923873
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.3278185874
Short name T200
Test name
Test status
Simulation time 799634438 ps
CPU time 2.84 seconds
Started Mar 31 12:38:21 PM PDT 24
Finished Mar 31 12:38:24 PM PDT 24
Peak memory 196416 kb
Host smart-ee58bc1a-d3bc-46c8-9813-0deee380b1ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278185874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.3278185874
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.2194859075
Short name T451
Test name
Test status
Simulation time 154645857 ps
CPU time 1.08 seconds
Started Mar 31 12:38:17 PM PDT 24
Finished Mar 31 12:38:18 PM PDT 24
Peak memory 195728 kb
Host smart-42bd5f3f-da49-4e67-a833-332d983d28b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194859075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.2194859075
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.4060673426
Short name T356
Test name
Test status
Simulation time 102692736 ps
CPU time 0.94 seconds
Started Mar 31 12:38:22 PM PDT 24
Finished Mar 31 12:38:23 PM PDT 24
Peak memory 196844 kb
Host smart-bee43a6f-3799-4cee-b077-6a71caa45fee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060673426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.4060673426
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.1676982852
Short name T208
Test name
Test status
Simulation time 441562997 ps
CPU time 4.62 seconds
Started Mar 31 12:38:17 PM PDT 24
Finished Mar 31 12:38:21 PM PDT 24
Peak memory 197944 kb
Host smart-623a1a3d-072b-42a4-866c-895d847e9d18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676982852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.1676982852
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.1062394555
Short name T348
Test name
Test status
Simulation time 59898879 ps
CPU time 1.18 seconds
Started Mar 31 12:38:20 PM PDT 24
Finished Mar 31 12:38:22 PM PDT 24
Peak memory 196228 kb
Host smart-b9c03f19-4bd5-4db3-b944-cd347d85e628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062394555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.1062394555
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.2592322753
Short name T419
Test name
Test status
Simulation time 182398690 ps
CPU time 1.42 seconds
Started Mar 31 12:38:13 PM PDT 24
Finished Mar 31 12:38:14 PM PDT 24
Peak memory 196148 kb
Host smart-b5cf72a3-4aff-4147-8105-d3609580b742
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592322753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.2592322753
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.692835211
Short name T715
Test name
Test status
Simulation time 35191595790 ps
CPU time 126.16 seconds
Started Mar 31 12:38:13 PM PDT 24
Finished Mar 31 12:40:19 PM PDT 24
Peak memory 198100 kb
Host smart-d7cb89b2-c588-4cc1-a649-c7327cda680b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692835211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.g
pio_stress_all.692835211
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.966365520
Short name T62
Test name
Test status
Simulation time 30175273480 ps
CPU time 689.11 seconds
Started Mar 31 12:38:21 PM PDT 24
Finished Mar 31 12:49:50 PM PDT 24
Peak memory 198216 kb
Host smart-59675620-f67b-4594-b7fb-f67daea8cfc0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=966365520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.966365520
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.2938847973
Short name T351
Test name
Test status
Simulation time 18864685 ps
CPU time 0.6 seconds
Started Mar 31 12:38:14 PM PDT 24
Finished Mar 31 12:38:15 PM PDT 24
Peak memory 195564 kb
Host smart-1fd2132b-8cfb-4529-9171-029cdd5ba184
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938847973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.2938847973
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.3069526892
Short name T701
Test name
Test status
Simulation time 100953810 ps
CPU time 0.75 seconds
Started Mar 31 12:38:10 PM PDT 24
Finished Mar 31 12:38:11 PM PDT 24
Peak memory 194148 kb
Host smart-6aab6976-2fc4-437e-b5c3-094436370fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069526892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.3069526892
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.2162033991
Short name T141
Test name
Test status
Simulation time 520767510 ps
CPU time 26.62 seconds
Started Mar 31 12:38:23 PM PDT 24
Finished Mar 31 12:38:50 PM PDT 24
Peak memory 196916 kb
Host smart-b963d781-5e90-4115-9964-142e431599f4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162033991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.2162033991
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.2464200773
Short name T587
Test name
Test status
Simulation time 238492109 ps
CPU time 1.01 seconds
Started Mar 31 12:38:18 PM PDT 24
Finished Mar 31 12:38:19 PM PDT 24
Peak memory 196544 kb
Host smart-1f9f57ed-b5fc-4604-8f97-36991247853d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464200773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.2464200773
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.1849177884
Short name T12
Test name
Test status
Simulation time 243725829 ps
CPU time 1.45 seconds
Started Mar 31 12:38:23 PM PDT 24
Finished Mar 31 12:38:24 PM PDT 24
Peak memory 196944 kb
Host smart-884acbcb-730a-49c0-a9d0-37c58ce785bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849177884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.1849177884
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.1659622781
Short name T428
Test name
Test status
Simulation time 70308169 ps
CPU time 2.63 seconds
Started Mar 31 12:38:23 PM PDT 24
Finished Mar 31 12:38:26 PM PDT 24
Peak memory 198036 kb
Host smart-de125479-d401-4d5e-8bc7-db9d770a14bd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659622781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.1659622781
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.982139997
Short name T373
Test name
Test status
Simulation time 509719970 ps
CPU time 1.19 seconds
Started Mar 31 12:38:21 PM PDT 24
Finished Mar 31 12:38:22 PM PDT 24
Peak memory 196260 kb
Host smart-139002a1-ac13-4646-b9d0-ecd54c9854ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982139997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.
982139997
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.3284270261
Short name T362
Test name
Test status
Simulation time 69688535 ps
CPU time 0.87 seconds
Started Mar 31 12:38:22 PM PDT 24
Finished Mar 31 12:38:23 PM PDT 24
Peak memory 196512 kb
Host smart-1beb26ea-c9b6-45d4-8991-6a3e4ee36867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284270261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.3284270261
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.3218283733
Short name T26
Test name
Test status
Simulation time 20119953 ps
CPU time 0.84 seconds
Started Mar 31 12:38:13 PM PDT 24
Finished Mar 31 12:38:14 PM PDT 24
Peak memory 196616 kb
Host smart-0487ac36-71a3-4608-9e71-5ca3be6da577
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218283733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.3218283733
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.1942961652
Short name T224
Test name
Test status
Simulation time 1869931494 ps
CPU time 4.34 seconds
Started Mar 31 12:38:14 PM PDT 24
Finished Mar 31 12:38:18 PM PDT 24
Peak memory 197928 kb
Host smart-af5c402a-97a2-4a34-b464-77dd4bce06e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942961652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.1942961652
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.3914012877
Short name T634
Test name
Test status
Simulation time 49284487 ps
CPU time 1.26 seconds
Started Mar 31 12:38:21 PM PDT 24
Finished Mar 31 12:38:22 PM PDT 24
Peak memory 196668 kb
Host smart-21c46d55-20fd-4fe7-bc26-c833cf9b2eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914012877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.3914012877
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.532772762
Short name T214
Test name
Test status
Simulation time 159020991 ps
CPU time 1.2 seconds
Started Mar 31 12:38:17 PM PDT 24
Finished Mar 31 12:38:18 PM PDT 24
Peak memory 196776 kb
Host smart-32fabae6-ebe1-4917-8ca1-a37af33e1cb8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532772762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.532772762
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.4136056442
Short name T615
Test name
Test status
Simulation time 4256859929 ps
CPU time 60.35 seconds
Started Mar 31 12:38:12 PM PDT 24
Finished Mar 31 12:39:12 PM PDT 24
Peak memory 198176 kb
Host smart-a51bf3b7-8847-45e5-a955-b84a37dd9938
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136056442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.4136056442
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.3165690957
Short name T159
Test name
Test status
Simulation time 44869048 ps
CPU time 0.55 seconds
Started Mar 31 12:38:27 PM PDT 24
Finished Mar 31 12:38:28 PM PDT 24
Peak memory 193872 kb
Host smart-4c983e76-dae8-4042-a4d0-8c614b574fa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165690957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.3165690957
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.735794582
Short name T322
Test name
Test status
Simulation time 52769672 ps
CPU time 1.03 seconds
Started Mar 31 12:38:13 PM PDT 24
Finished Mar 31 12:38:14 PM PDT 24
Peak memory 195768 kb
Host smart-bcadddde-8e30-4998-9513-0c08a4c949fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735794582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.735794582
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.1742580697
Short name T449
Test name
Test status
Simulation time 112838415 ps
CPU time 5.32 seconds
Started Mar 31 12:38:21 PM PDT 24
Finished Mar 31 12:38:26 PM PDT 24
Peak memory 196932 kb
Host smart-9e46bcc4-7717-4f83-a4c1-93d0285888c7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742580697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.1742580697
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.1959823089
Short name T603
Test name
Test status
Simulation time 66527247 ps
CPU time 0.93 seconds
Started Mar 31 12:38:15 PM PDT 24
Finished Mar 31 12:38:16 PM PDT 24
Peak memory 197820 kb
Host smart-1dd3077e-51d9-4579-9057-4445ca0ecbf3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959823089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.1959823089
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.3592488670
Short name T257
Test name
Test status
Simulation time 32945603 ps
CPU time 0.75 seconds
Started Mar 31 12:38:21 PM PDT 24
Finished Mar 31 12:38:22 PM PDT 24
Peak memory 195348 kb
Host smart-e619bdd2-ca02-4c30-ae60-29f5da1cd512
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592488670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.3592488670
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.3832947271
Short name T571
Test name
Test status
Simulation time 80658441 ps
CPU time 1.1 seconds
Started Mar 31 12:38:18 PM PDT 24
Finished Mar 31 12:38:20 PM PDT 24
Peak memory 196392 kb
Host smart-a1be46ff-3203-4fff-998d-37fa6244ccea
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832947271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.3832947271
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.1491294646
Short name T252
Test name
Test status
Simulation time 132938824 ps
CPU time 2.74 seconds
Started Mar 31 12:38:16 PM PDT 24
Finished Mar 31 12:38:24 PM PDT 24
Peak memory 196748 kb
Host smart-ad529715-2bb1-477f-9f62-2dc4c075f160
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491294646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.1491294646
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.3010284143
Short name T637
Test name
Test status
Simulation time 165430155 ps
CPU time 0.79 seconds
Started Mar 31 12:38:23 PM PDT 24
Finished Mar 31 12:38:24 PM PDT 24
Peak memory 195520 kb
Host smart-4b0c70a3-c024-432c-8c63-347d9c0b8042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010284143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.3010284143
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.3246947969
Short name T151
Test name
Test status
Simulation time 73079222 ps
CPU time 0.88 seconds
Started Mar 31 12:38:24 PM PDT 24
Finished Mar 31 12:38:25 PM PDT 24
Peak memory 195800 kb
Host smart-c77ff4e3-5622-40a7-9820-2a4fe4691b98
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246947969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.3246947969
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1056555427
Short name T162
Test name
Test status
Simulation time 414682172 ps
CPU time 4.61 seconds
Started Mar 31 12:38:13 PM PDT 24
Finished Mar 31 12:38:18 PM PDT 24
Peak memory 197988 kb
Host smart-b718ed46-de1f-49bb-a362-d63c90e3963b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056555427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1056555427
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.2534717381
Short name T335
Test name
Test status
Simulation time 50858370 ps
CPU time 1.09 seconds
Started Mar 31 12:38:22 PM PDT 24
Finished Mar 31 12:38:23 PM PDT 24
Peak memory 195696 kb
Host smart-0bf49fa3-2355-4a4b-8c30-d07b7bf5275e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534717381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.2534717381
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.314689522
Short name T540
Test name
Test status
Simulation time 78301556 ps
CPU time 0.72 seconds
Started Mar 31 12:38:19 PM PDT 24
Finished Mar 31 12:38:20 PM PDT 24
Peak memory 195868 kb
Host smart-1369cd7a-aafe-4913-b2c5-89b59bc470a7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314689522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.314689522
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.169949041
Short name T211
Test name
Test status
Simulation time 20081317241 ps
CPU time 41.25 seconds
Started Mar 31 12:38:17 PM PDT 24
Finished Mar 31 12:38:59 PM PDT 24
Peak memory 198152 kb
Host smart-c070480b-eda9-44c3-a8d2-58b53094c52d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169949041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.g
pio_stress_all.169949041
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.1395613166
Short name T58
Test name
Test status
Simulation time 13968028 ps
CPU time 0.56 seconds
Started Mar 31 12:38:28 PM PDT 24
Finished Mar 31 12:38:29 PM PDT 24
Peak memory 193396 kb
Host smart-1460dde1-5ff8-4379-bf99-7c4d12871863
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395613166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.1395613166
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.3096079250
Short name T285
Test name
Test status
Simulation time 54083976 ps
CPU time 0.96 seconds
Started Mar 31 12:38:11 PM PDT 24
Finished Mar 31 12:38:12 PM PDT 24
Peak memory 195752 kb
Host smart-a0353e45-407f-4e61-aef6-474224d901a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096079250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.3096079250
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.1220292465
Short name T229
Test name
Test status
Simulation time 1244698907 ps
CPU time 17 seconds
Started Mar 31 12:38:28 PM PDT 24
Finished Mar 31 12:38:45 PM PDT 24
Peak memory 195408 kb
Host smart-b8069b32-223d-428f-9b00-2103dd882ffb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220292465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.1220292465
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.2186703059
Short name T254
Test name
Test status
Simulation time 225399778 ps
CPU time 0.98 seconds
Started Mar 31 12:38:13 PM PDT 24
Finished Mar 31 12:38:14 PM PDT 24
Peak memory 196636 kb
Host smart-e16af31d-8ddb-488d-bf06-db10e7d46e03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186703059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.2186703059
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.2246300700
Short name T55
Test name
Test status
Simulation time 52734468 ps
CPU time 0.91 seconds
Started Mar 31 12:38:19 PM PDT 24
Finished Mar 31 12:38:20 PM PDT 24
Peak memory 196556 kb
Host smart-fd83a166-d2dd-437d-ad8c-fff2de5ea6b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246300700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.2246300700
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.526543162
Short name T535
Test name
Test status
Simulation time 67911887 ps
CPU time 2.66 seconds
Started Mar 31 12:38:32 PM PDT 24
Finished Mar 31 12:38:34 PM PDT 24
Peak memory 198000 kb
Host smart-aa63a20a-a149-46e9-80be-5a513bc7e99b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526543162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.gpio_intr_with_filter_rand_intr_event.526543162
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.2950662466
Short name T650
Test name
Test status
Simulation time 768373241 ps
CPU time 2.77 seconds
Started Mar 31 12:38:23 PM PDT 24
Finished Mar 31 12:38:26 PM PDT 24
Peak memory 196884 kb
Host smart-3912550c-e3b7-4f73-a781-f1cd63cd961a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950662466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.2950662466
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.3522866101
Short name T342
Test name
Test status
Simulation time 29899805 ps
CPU time 0.83 seconds
Started Mar 31 12:38:24 PM PDT 24
Finished Mar 31 12:38:28 PM PDT 24
Peak memory 196572 kb
Host smart-c2c89ab5-70be-46e7-9977-196f03b62107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522866101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.3522866101
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.3141839167
Short name T359
Test name
Test status
Simulation time 219756510 ps
CPU time 1.22 seconds
Started Mar 31 12:38:22 PM PDT 24
Finished Mar 31 12:38:23 PM PDT 24
Peak memory 196588 kb
Host smart-d5e3ff00-3909-4392-920c-5eed0549c6f3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141839167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.3141839167
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.3034843017
Short name T100
Test name
Test status
Simulation time 944901097 ps
CPU time 4.03 seconds
Started Mar 31 12:38:19 PM PDT 24
Finished Mar 31 12:38:23 PM PDT 24
Peak memory 197620 kb
Host smart-85455091-fd1a-4326-9ca3-7e5df8281844
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034843017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.3034843017
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.1653615369
Short name T592
Test name
Test status
Simulation time 142064985 ps
CPU time 1.1 seconds
Started Mar 31 12:38:19 PM PDT 24
Finished Mar 31 12:38:20 PM PDT 24
Peak memory 195588 kb
Host smart-bb3950ed-0595-4086-95bf-8aa12f743b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653615369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.1653615369
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.4162496652
Short name T471
Test name
Test status
Simulation time 606382361 ps
CPU time 1.21 seconds
Started Mar 31 12:38:13 PM PDT 24
Finished Mar 31 12:38:14 PM PDT 24
Peak memory 195864 kb
Host smart-9a76dd87-91c3-4ba2-ab6e-c0975b869f1c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162496652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.4162496652
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.1256881034
Short name T503
Test name
Test status
Simulation time 50834335020 ps
CPU time 134.73 seconds
Started Mar 31 12:38:19 PM PDT 24
Finished Mar 31 12:40:34 PM PDT 24
Peak memory 198024 kb
Host smart-1e31407a-f47e-494b-8d7a-39f769e77dab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256881034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.1256881034
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.2215019194
Short name T236
Test name
Test status
Simulation time 13191816 ps
CPU time 0.59 seconds
Started Mar 31 12:37:46 PM PDT 24
Finished Mar 31 12:37:47 PM PDT 24
Peak memory 193856 kb
Host smart-0b56b5ff-5dbf-47a0-8ec5-5a91b8465ead
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215019194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.2215019194
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.2613822734
Short name T138
Test name
Test status
Simulation time 81092120 ps
CPU time 0.86 seconds
Started Mar 31 12:37:39 PM PDT 24
Finished Mar 31 12:37:40 PM PDT 24
Peak memory 195528 kb
Host smart-fa928868-eb33-4316-991d-d0ee5915fd9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613822734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.2613822734
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.1477689882
Short name T120
Test name
Test status
Simulation time 2062044655 ps
CPU time 27.62 seconds
Started Mar 31 12:37:40 PM PDT 24
Finished Mar 31 12:38:08 PM PDT 24
Peak memory 196728 kb
Host smart-d4512279-bfda-4a2b-9614-a12811cf14b1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477689882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.1477689882
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.2470336458
Short name T293
Test name
Test status
Simulation time 47761502 ps
CPU time 1.46 seconds
Started Mar 31 12:37:39 PM PDT 24
Finished Mar 31 12:37:41 PM PDT 24
Peak memory 197180 kb
Host smart-e579f637-f34b-4c85-a45b-9f92b18c759c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470336458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.2470336458
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.3649568965
Short name T366
Test name
Test status
Simulation time 167422777 ps
CPU time 1.93 seconds
Started Mar 31 12:37:41 PM PDT 24
Finished Mar 31 12:37:43 PM PDT 24
Peak memory 197784 kb
Host smart-db7d0fe4-ea41-4789-b3f0-73ab1df2bcf9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649568965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.3649568965
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.139675683
Short name T716
Test name
Test status
Simulation time 168695517 ps
CPU time 3.67 seconds
Started Mar 31 12:37:52 PM PDT 24
Finished Mar 31 12:37:57 PM PDT 24
Peak memory 197988 kb
Host smart-7252dc9b-8e6b-40e4-a90a-80997be3f0c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139675683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.139675683
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.3752740221
Short name T189
Test name
Test status
Simulation time 70375764 ps
CPU time 0.61 seconds
Started Mar 31 12:37:40 PM PDT 24
Finished Mar 31 12:37:41 PM PDT 24
Peak memory 194364 kb
Host smart-0daf785f-49e8-49d6-a366-8c2ae5444107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752740221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.3752740221
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.2553207877
Short name T430
Test name
Test status
Simulation time 65966919 ps
CPU time 0.92 seconds
Started Mar 31 12:38:02 PM PDT 24
Finished Mar 31 12:38:03 PM PDT 24
Peak memory 196564 kb
Host smart-d542652b-2651-4e63-9e65-1d501777b326
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553207877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.2553207877
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.4086338713
Short name T250
Test name
Test status
Simulation time 141770680 ps
CPU time 1.87 seconds
Started Mar 31 12:37:51 PM PDT 24
Finished Mar 31 12:37:53 PM PDT 24
Peak memory 197920 kb
Host smart-e89b3ea1-eaf6-4846-b3d3-1e86d0f41d32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086338713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.4086338713
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.599831053
Short name T49
Test name
Test status
Simulation time 1017611808 ps
CPU time 0.99 seconds
Started Mar 31 12:37:54 PM PDT 24
Finished Mar 31 12:37:56 PM PDT 24
Peak memory 214916 kb
Host smart-5159afe0-6ffa-463b-bf5b-a0fe76d0adcc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599831053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.599831053
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.281970864
Short name T670
Test name
Test status
Simulation time 26174214 ps
CPU time 0.76 seconds
Started Mar 31 12:38:00 PM PDT 24
Finished Mar 31 12:38:01 PM PDT 24
Peak memory 194156 kb
Host smart-0e6ebc93-9256-4105-a990-aea29fffd3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281970864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.281970864
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.2941790277
Short name T510
Test name
Test status
Simulation time 121727197 ps
CPU time 1.02 seconds
Started Mar 31 12:37:54 PM PDT 24
Finished Mar 31 12:37:55 PM PDT 24
Peak memory 195800 kb
Host smart-e9377969-b49d-488b-8a62-5b17cd768377
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941790277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.2941790277
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.1001035378
Short name T462
Test name
Test status
Simulation time 46776826850 ps
CPU time 75.71 seconds
Started Mar 31 12:37:50 PM PDT 24
Finished Mar 31 12:39:06 PM PDT 24
Peak memory 197992 kb
Host smart-7ef13ed5-646d-4684-be52-e319a0e4da3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001035378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.1001035378
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.1699134300
Short name T310
Test name
Test status
Simulation time 11851617 ps
CPU time 0.57 seconds
Started Mar 31 12:38:17 PM PDT 24
Finished Mar 31 12:38:18 PM PDT 24
Peak memory 193824 kb
Host smart-3dcedaa4-c231-4ee9-b3d6-76af08083b57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699134300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.1699134300
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.1175793883
Short name T186
Test name
Test status
Simulation time 100203749 ps
CPU time 1.03 seconds
Started Mar 31 12:38:16 PM PDT 24
Finished Mar 31 12:38:17 PM PDT 24
Peak memory 196620 kb
Host smart-4fbda97f-d589-4bab-8beb-7947d32645da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175793883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.1175793883
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.1247573181
Short name T558
Test name
Test status
Simulation time 136176571 ps
CPU time 4.29 seconds
Started Mar 31 12:38:28 PM PDT 24
Finished Mar 31 12:38:33 PM PDT 24
Peak memory 195568 kb
Host smart-20bb589f-0924-4bd0-9363-cee1e4729469
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247573181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.1247573181
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.4090352327
Short name T547
Test name
Test status
Simulation time 132267426 ps
CPU time 0.96 seconds
Started Mar 31 12:38:15 PM PDT 24
Finished Mar 31 12:38:16 PM PDT 24
Peak memory 197784 kb
Host smart-ea93c232-d276-4947-ae9a-63b40403110f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090352327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.4090352327
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.1150062545
Short name T14
Test name
Test status
Simulation time 45482958 ps
CPU time 1.22 seconds
Started Mar 31 12:38:15 PM PDT 24
Finished Mar 31 12:38:17 PM PDT 24
Peak memory 195988 kb
Host smart-1eaa7590-c152-4a50-8257-0a924e865861
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150062545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.1150062545
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.1581903858
Short name T549
Test name
Test status
Simulation time 154688176 ps
CPU time 2.95 seconds
Started Mar 31 12:38:20 PM PDT 24
Finished Mar 31 12:38:23 PM PDT 24
Peak memory 198068 kb
Host smart-e751ffa9-efd4-4fa8-8b17-451f8ce9a57b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581903858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.1581903858
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.121740760
Short name T628
Test name
Test status
Simulation time 547628030 ps
CPU time 2.72 seconds
Started Mar 31 12:38:31 PM PDT 24
Finished Mar 31 12:38:33 PM PDT 24
Peak memory 196756 kb
Host smart-b5b9f5cf-31f1-4692-b65b-e09aedb72d34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121740760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger.
121740760
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.1715561384
Short name T133
Test name
Test status
Simulation time 62440470 ps
CPU time 0.68 seconds
Started Mar 31 12:38:18 PM PDT 24
Finished Mar 31 12:38:18 PM PDT 24
Peak memory 195284 kb
Host smart-b184df20-9d26-4557-b8f8-978e7552bd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715561384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.1715561384
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.4259889725
Short name T569
Test name
Test status
Simulation time 154407418 ps
CPU time 0.94 seconds
Started Mar 31 12:38:19 PM PDT 24
Finished Mar 31 12:38:20 PM PDT 24
Peak memory 195740 kb
Host smart-46837c92-6b94-4497-bc4f-8e592301bcc5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259889725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.4259889725
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.1432679625
Short name T399
Test name
Test status
Simulation time 729212862 ps
CPU time 4.88 seconds
Started Mar 31 12:38:13 PM PDT 24
Finished Mar 31 12:38:18 PM PDT 24
Peak memory 197964 kb
Host smart-f5a32012-e249-442d-a283-a92c921a6e17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432679625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.1432679625
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.2877637169
Short name T187
Test name
Test status
Simulation time 91174551 ps
CPU time 1.16 seconds
Started Mar 31 12:38:14 PM PDT 24
Finished Mar 31 12:38:15 PM PDT 24
Peak memory 196828 kb
Host smart-28675b4a-e504-437f-ac20-507379b8434c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877637169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.2877637169
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.2428570308
Short name T199
Test name
Test status
Simulation time 73243096 ps
CPU time 1.3 seconds
Started Mar 31 12:38:15 PM PDT 24
Finished Mar 31 12:38:17 PM PDT 24
Peak memory 196768 kb
Host smart-3bc2729e-1ff3-4667-bee4-eeca45eae8f7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428570308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.2428570308
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.3044527732
Short name T6
Test name
Test status
Simulation time 62401121730 ps
CPU time 176.79 seconds
Started Mar 31 12:38:18 PM PDT 24
Finished Mar 31 12:41:15 PM PDT 24
Peak memory 198220 kb
Host smart-0602b602-79f4-4a5e-9640-e20b1620de75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044527732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.3044527732
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.2224903360
Short name T509
Test name
Test status
Simulation time 80260227618 ps
CPU time 456.04 seconds
Started Mar 31 12:38:28 PM PDT 24
Finished Mar 31 12:46:04 PM PDT 24
Peak memory 198128 kb
Host smart-4236cb48-4233-480c-a44a-4ea5a7754472
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2224903360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.2224903360
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.1165155082
Short name T610
Test name
Test status
Simulation time 11583479 ps
CPU time 0.58 seconds
Started Mar 31 12:38:38 PM PDT 24
Finished Mar 31 12:38:39 PM PDT 24
Peak memory 194660 kb
Host smart-1d7e8631-afa5-41b1-b9d8-a17bce10e2de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165155082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.1165155082
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.2889282815
Short name T259
Test name
Test status
Simulation time 163898004 ps
CPU time 0.96 seconds
Started Mar 31 12:38:25 PM PDT 24
Finished Mar 31 12:38:26 PM PDT 24
Peak memory 196664 kb
Host smart-b04a9cd8-35bc-4d9c-bc4a-022b27444797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889282815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.2889282815
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.2260451313
Short name T452
Test name
Test status
Simulation time 2871274300 ps
CPU time 14.48 seconds
Started Mar 31 12:38:25 PM PDT 24
Finished Mar 31 12:38:40 PM PDT 24
Peak memory 197024 kb
Host smart-47603604-128b-4f7e-a3bd-2661e545ab98
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260451313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.2260451313
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.4275466507
Short name T302
Test name
Test status
Simulation time 111494210 ps
CPU time 0.98 seconds
Started Mar 31 12:38:23 PM PDT 24
Finished Mar 31 12:38:24 PM PDT 24
Peak memory 196360 kb
Host smart-a6721484-1d3b-47b2-a51e-2dcb58418f66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275466507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.4275466507
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.1872753784
Short name T157
Test name
Test status
Simulation time 18714156 ps
CPU time 0.72 seconds
Started Mar 31 12:38:19 PM PDT 24
Finished Mar 31 12:38:20 PM PDT 24
Peak memory 194332 kb
Host smart-56647788-2cbd-406b-9448-837f3b17c8f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872753784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.1872753784
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.3770822798
Short name T714
Test name
Test status
Simulation time 61241249 ps
CPU time 1.86 seconds
Started Mar 31 12:38:29 PM PDT 24
Finished Mar 31 12:38:31 PM PDT 24
Peak memory 198016 kb
Host smart-fbce056a-af99-45e2-821b-ecfd11e3fdf9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770822798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.3770822798
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.2413720456
Short name T620
Test name
Test status
Simulation time 260539958 ps
CPU time 2.38 seconds
Started Mar 31 12:38:24 PM PDT 24
Finished Mar 31 12:38:27 PM PDT 24
Peak memory 196972 kb
Host smart-aba93268-118a-4206-a19f-bce1998853b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413720456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.2413720456
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.2329479891
Short name T444
Test name
Test status
Simulation time 61867983 ps
CPU time 1.08 seconds
Started Mar 31 12:38:24 PM PDT 24
Finished Mar 31 12:38:26 PM PDT 24
Peak memory 195892 kb
Host smart-f0b95536-8cce-4f10-9e73-b6f1ce231538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329479891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.2329479891
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.534114615
Short name T167
Test name
Test status
Simulation time 153067899 ps
CPU time 1.2 seconds
Started Mar 31 12:38:23 PM PDT 24
Finished Mar 31 12:38:24 PM PDT 24
Peak memory 197152 kb
Host smart-80d2e50d-8b23-48fe-bb5d-827270b6d06a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534114615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullup
_pulldown.534114615
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.4268711352
Short name T207
Test name
Test status
Simulation time 681229405 ps
CPU time 5.48 seconds
Started Mar 31 12:38:23 PM PDT 24
Finished Mar 31 12:38:34 PM PDT 24
Peak memory 197976 kb
Host smart-93e88ab1-e38f-4735-9608-a43e90ac1a68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268711352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.4268711352
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.4063457637
Short name T195
Test name
Test status
Simulation time 76480561 ps
CPU time 1.24 seconds
Started Mar 31 12:38:25 PM PDT 24
Finished Mar 31 12:38:26 PM PDT 24
Peak memory 195792 kb
Host smart-04d25dd8-3f54-42a2-9d08-2b70c9d088ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063457637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.4063457637
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.622312360
Short name T116
Test name
Test status
Simulation time 99298545 ps
CPU time 0.83 seconds
Started Mar 31 12:38:23 PM PDT 24
Finished Mar 31 12:38:24 PM PDT 24
Peak memory 195364 kb
Host smart-2dec35ef-1be5-4053-afaf-0b5b8cddebbb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622312360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.622312360
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.4211331191
Short name T102
Test name
Test status
Simulation time 24141014004 ps
CPU time 95.21 seconds
Started Mar 31 12:38:24 PM PDT 24
Finished Mar 31 12:39:59 PM PDT 24
Peak memory 198104 kb
Host smart-e62f0833-634a-4fd5-b399-99e80071f938
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211331191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.4211331191
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.623110063
Short name T400
Test name
Test status
Simulation time 212702802281 ps
CPU time 1277.71 seconds
Started Mar 31 12:38:21 PM PDT 24
Finished Mar 31 12:59:39 PM PDT 24
Peak memory 198184 kb
Host smart-71355118-f6ad-42df-9088-c85e7f728ac4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=623110063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.623110063
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.1394854311
Short name T513
Test name
Test status
Simulation time 33539476 ps
CPU time 0.57 seconds
Started Mar 31 12:38:22 PM PDT 24
Finished Mar 31 12:38:22 PM PDT 24
Peak memory 193936 kb
Host smart-2b470fc6-f46a-4b88-ba04-961688682e5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394854311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.1394854311
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.4000526212
Short name T240
Test name
Test status
Simulation time 28386831 ps
CPU time 0.62 seconds
Started Mar 31 12:38:24 PM PDT 24
Finished Mar 31 12:38:28 PM PDT 24
Peak memory 194740 kb
Host smart-0e6423c9-5e7f-408e-b4b1-b7673fe6a163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000526212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.4000526212
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.1800162473
Short name T617
Test name
Test status
Simulation time 833501901 ps
CPU time 8.45 seconds
Started Mar 31 12:38:22 PM PDT 24
Finished Mar 31 12:38:30 PM PDT 24
Peak memory 196808 kb
Host smart-3c6c7573-1310-4395-a8a7-1b1887338dd6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800162473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.1800162473
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.726591627
Short name T648
Test name
Test status
Simulation time 99368567 ps
CPU time 1 seconds
Started Mar 31 12:38:26 PM PDT 24
Finished Mar 31 12:38:27 PM PDT 24
Peak memory 197204 kb
Host smart-46aca5c1-cdd1-4f1e-8f6b-9fc0375a6509
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726591627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.726591627
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.2614286033
Short name T198
Test name
Test status
Simulation time 143096886 ps
CPU time 1.31 seconds
Started Mar 31 12:38:19 PM PDT 24
Finished Mar 31 12:38:20 PM PDT 24
Peak memory 197408 kb
Host smart-a9bf26bd-b37d-4b75-86f8-305428128675
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614286033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.2614286033
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.1885688759
Short name T683
Test name
Test status
Simulation time 94874071 ps
CPU time 2.04 seconds
Started Mar 31 12:38:25 PM PDT 24
Finished Mar 31 12:38:27 PM PDT 24
Peak memory 198060 kb
Host smart-dfb243d7-7a73-437a-a56e-bf7829af2f87
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885688759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.1885688759
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.3388667266
Short name T114
Test name
Test status
Simulation time 552892490 ps
CPU time 2.62 seconds
Started Mar 31 12:38:36 PM PDT 24
Finished Mar 31 12:38:39 PM PDT 24
Peak memory 197084 kb
Host smart-6858c380-ed78-4b3d-ba73-126b16069175
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388667266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.3388667266
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.769114615
Short name T393
Test name
Test status
Simulation time 119578726 ps
CPU time 1.31 seconds
Started Mar 31 12:38:24 PM PDT 24
Finished Mar 31 12:38:26 PM PDT 24
Peak memory 195792 kb
Host smart-36c74ea9-06b7-4425-a65a-a57d3b8af6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769114615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.769114615
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.3069241062
Short name T396
Test name
Test status
Simulation time 33175500 ps
CPU time 1.13 seconds
Started Mar 31 12:38:24 PM PDT 24
Finished Mar 31 12:38:29 PM PDT 24
Peak memory 198076 kb
Host smart-4dc45f97-0fdc-4f88-97ff-d23d36fa95a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069241062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.3069241062
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.2697647308
Short name T711
Test name
Test status
Simulation time 360588235 ps
CPU time 4.15 seconds
Started Mar 31 12:38:19 PM PDT 24
Finished Mar 31 12:38:23 PM PDT 24
Peak memory 197972 kb
Host smart-a26a2f94-7995-4f92-ab6a-4c7569c8e2af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697647308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.2697647308
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.2990586442
Short name T644
Test name
Test status
Simulation time 159279792 ps
CPU time 1.09 seconds
Started Mar 31 12:38:17 PM PDT 24
Finished Mar 31 12:38:18 PM PDT 24
Peak memory 195776 kb
Host smart-1cf2831a-86a8-4fc7-8006-2f6e768ca5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990586442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.2990586442
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.3096190694
Short name T545
Test name
Test status
Simulation time 46556901 ps
CPU time 0.96 seconds
Started Mar 31 12:38:16 PM PDT 24
Finished Mar 31 12:38:18 PM PDT 24
Peak memory 196432 kb
Host smart-dad7f28e-3955-4cc4-9725-78acb0a16599
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096190694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.3096190694
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.897256807
Short name T431
Test name
Test status
Simulation time 13731977317 ps
CPU time 149.83 seconds
Started Mar 31 12:38:22 PM PDT 24
Finished Mar 31 12:40:52 PM PDT 24
Peak memory 198180 kb
Host smart-9100565b-77c2-44a0-a087-fe5ee4709c1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897256807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.g
pio_stress_all.897256807
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.187157057
Short name T176
Test name
Test status
Simulation time 36303352 ps
CPU time 0.58 seconds
Started Mar 31 12:38:23 PM PDT 24
Finished Mar 31 12:38:24 PM PDT 24
Peak memory 193944 kb
Host smart-a3f4d1f8-7bfb-4bc9-b0fe-2a0637d4b97d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187157057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.187157057
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.1711690977
Short name T209
Test name
Test status
Simulation time 18590365 ps
CPU time 0.67 seconds
Started Mar 31 12:38:19 PM PDT 24
Finished Mar 31 12:38:20 PM PDT 24
Peak memory 194828 kb
Host smart-b261cc2c-0c14-48ba-9556-19c6a25a2baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711690977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.1711690977
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.301886718
Short name T324
Test name
Test status
Simulation time 1017341173 ps
CPU time 7.21 seconds
Started Mar 31 12:38:22 PM PDT 24
Finished Mar 31 12:38:29 PM PDT 24
Peak memory 197136 kb
Host smart-c65c9fda-bf37-4b63-acdf-324219a2e862
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301886718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stres
s.301886718
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.299256404
Short name T624
Test name
Test status
Simulation time 220754184 ps
CPU time 0.81 seconds
Started Mar 31 12:38:25 PM PDT 24
Finished Mar 31 12:38:28 PM PDT 24
Peak memory 196956 kb
Host smart-6d1c5368-c7af-4ea3-be81-8b486fe1cac6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299256404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.299256404
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.2144948620
Short name T368
Test name
Test status
Simulation time 120530083 ps
CPU time 1.17 seconds
Started Mar 31 12:38:25 PM PDT 24
Finished Mar 31 12:38:26 PM PDT 24
Peak memory 196832 kb
Host smart-98185bee-e7a7-4740-9188-2f9273a3ece1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144948620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.2144948620
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.1878953153
Short name T160
Test name
Test status
Simulation time 74044392 ps
CPU time 2.77 seconds
Started Mar 31 12:38:23 PM PDT 24
Finished Mar 31 12:38:26 PM PDT 24
Peak memory 198052 kb
Host smart-2c873308-ad36-49ef-8f96-94a7c7dd4359
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878953153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.1878953153
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.442427005
Short name T424
Test name
Test status
Simulation time 337984193 ps
CPU time 2.73 seconds
Started Mar 31 12:38:21 PM PDT 24
Finished Mar 31 12:38:24 PM PDT 24
Peak memory 197240 kb
Host smart-5c77b628-6120-4c62-a86a-b58f4ec099d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442427005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger.
442427005
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.2893674192
Short name T668
Test name
Test status
Simulation time 26889501 ps
CPU time 0.86 seconds
Started Mar 31 12:38:18 PM PDT 24
Finished Mar 31 12:38:19 PM PDT 24
Peak memory 196684 kb
Host smart-e179089d-5e1e-40e9-a5c0-422f68611341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893674192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.2893674192
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.2381204203
Short name T225
Test name
Test status
Simulation time 103274124 ps
CPU time 0.84 seconds
Started Mar 31 12:38:27 PM PDT 24
Finished Mar 31 12:38:28 PM PDT 24
Peak memory 196300 kb
Host smart-101213d4-abea-4a96-a5ca-0959bc287d71
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381204203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.2381204203
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.1335724641
Short name T276
Test name
Test status
Simulation time 265279134 ps
CPU time 1.84 seconds
Started Mar 31 12:38:26 PM PDT 24
Finished Mar 31 12:38:28 PM PDT 24
Peak memory 197908 kb
Host smart-be4b5726-bbe3-4903-9998-8f1e9bc9adfc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335724641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.1335724641
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.3356671725
Short name T691
Test name
Test status
Simulation time 55248424 ps
CPU time 0.93 seconds
Started Mar 31 12:38:21 PM PDT 24
Finished Mar 31 12:38:22 PM PDT 24
Peak memory 196268 kb
Host smart-e09f80e4-fceb-4070-bbcb-b0da0e0b85bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356671725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.3356671725
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.55548212
Short name T56
Test name
Test status
Simulation time 98681451 ps
CPU time 0.79 seconds
Started Mar 31 12:38:24 PM PDT 24
Finished Mar 31 12:38:24 PM PDT 24
Peak memory 196016 kb
Host smart-240a5773-2b82-42ac-9d4d-60bfaca08be7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55548212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.55548212
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.350165238
Short name T4
Test name
Test status
Simulation time 17295250826 ps
CPU time 186.42 seconds
Started Mar 31 12:38:24 PM PDT 24
Finished Mar 31 12:41:30 PM PDT 24
Peak memory 198124 kb
Host smart-9b9d110e-1ede-4809-aa99-ca9026e1eb4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350165238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.g
pio_stress_all.350165238
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.1136629423
Short name T165
Test name
Test status
Simulation time 115971893 ps
CPU time 0.59 seconds
Started Mar 31 12:38:24 PM PDT 24
Finished Mar 31 12:38:25 PM PDT 24
Peak memory 194884 kb
Host smart-1d321a34-0999-4ac4-99cc-85cf9764f82e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136629423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.1136629423
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.1380695030
Short name T319
Test name
Test status
Simulation time 21078363 ps
CPU time 0.77 seconds
Started Mar 31 12:38:25 PM PDT 24
Finished Mar 31 12:38:26 PM PDT 24
Peak memory 195340 kb
Host smart-fb014463-86eb-4498-a307-d0f48ee7b9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380695030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.1380695030
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.2498830722
Short name T241
Test name
Test status
Simulation time 170106648 ps
CPU time 6.08 seconds
Started Mar 31 12:38:16 PM PDT 24
Finished Mar 31 12:38:23 PM PDT 24
Peak memory 197988 kb
Host smart-c29d2142-175d-426c-b735-a51a7a4f1fc8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498830722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.2498830722
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.3258631633
Short name T235
Test name
Test status
Simulation time 230025461 ps
CPU time 0.89 seconds
Started Mar 31 12:38:20 PM PDT 24
Finished Mar 31 12:38:21 PM PDT 24
Peak memory 197772 kb
Host smart-22129816-cb0c-44f5-9712-b0002ab13e04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258631633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.3258631633
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.526266019
Short name T564
Test name
Test status
Simulation time 132637680 ps
CPU time 0.78 seconds
Started Mar 31 12:38:25 PM PDT 24
Finished Mar 31 12:38:26 PM PDT 24
Peak memory 195448 kb
Host smart-2d7fe96e-a4e6-4487-8ba8-3c942e4a1178
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526266019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.526266019
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.2388689819
Short name T586
Test name
Test status
Simulation time 75100814 ps
CPU time 2.81 seconds
Started Mar 31 12:38:20 PM PDT 24
Finished Mar 31 12:38:23 PM PDT 24
Peak memory 196344 kb
Host smart-18145df0-12ca-46da-94c1-0007eb3dd723
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388689819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.2388689819
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.3130642521
Short name T173
Test name
Test status
Simulation time 251569931 ps
CPU time 2.81 seconds
Started Mar 31 12:38:18 PM PDT 24
Finished Mar 31 12:38:21 PM PDT 24
Peak memory 198048 kb
Host smart-d589b845-9336-4599-9bb4-2166261ea94e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130642521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.3130642521
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.2657062531
Short name T611
Test name
Test status
Simulation time 51784148 ps
CPU time 1.06 seconds
Started Mar 31 12:38:19 PM PDT 24
Finished Mar 31 12:38:20 PM PDT 24
Peak memory 196668 kb
Host smart-df592223-6f63-4f52-96b5-5b1eb8f837bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657062531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.2657062531
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.176071965
Short name T661
Test name
Test status
Simulation time 33353479 ps
CPU time 0.66 seconds
Started Mar 31 12:38:19 PM PDT 24
Finished Mar 31 12:38:20 PM PDT 24
Peak memory 195104 kb
Host smart-8a3b4a25-6597-4787-99ee-9cb0cd1598f1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176071965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.176071965
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.3797410032
Short name T172
Test name
Test status
Simulation time 30280270 ps
CPU time 1.33 seconds
Started Mar 31 12:38:16 PM PDT 24
Finished Mar 31 12:38:18 PM PDT 24
Peak memory 197904 kb
Host smart-1bd06ca8-fbfc-4be6-b40d-85e709dfdfc0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797410032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.3797410032
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.2149648404
Short name T533
Test name
Test status
Simulation time 178130026 ps
CPU time 0.99 seconds
Started Mar 31 12:38:29 PM PDT 24
Finished Mar 31 12:38:30 PM PDT 24
Peak memory 195836 kb
Host smart-1a97615b-0905-4919-a147-988107b0806e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149648404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.2149648404
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.1122981604
Short name T345
Test name
Test status
Simulation time 78085587 ps
CPU time 1.33 seconds
Started Mar 31 12:38:20 PM PDT 24
Finished Mar 31 12:38:21 PM PDT 24
Peak memory 196552 kb
Host smart-f652a8e1-0840-4ce7-9cf1-c5ebe6493e14
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122981604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.1122981604
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.723754667
Short name T3
Test name
Test status
Simulation time 27231812863 ps
CPU time 172.46 seconds
Started Mar 31 12:38:23 PM PDT 24
Finished Mar 31 12:41:15 PM PDT 24
Peak memory 198176 kb
Host smart-0ae5ce83-d8b7-4655-a9a8-e1c934865571
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723754667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.g
pio_stress_all.723754667
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.1569662375
Short name T381
Test name
Test status
Simulation time 12769707 ps
CPU time 0.6 seconds
Started Mar 31 12:38:52 PM PDT 24
Finished Mar 31 12:38:53 PM PDT 24
Peak memory 194752 kb
Host smart-b3e66dc2-6740-4ccb-9b8e-ee7fcbaf3bcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569662375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.1569662375
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.4029497993
Short name T479
Test name
Test status
Simulation time 38410203 ps
CPU time 0.91 seconds
Started Mar 31 12:38:30 PM PDT 24
Finished Mar 31 12:38:31 PM PDT 24
Peak memory 197324 kb
Host smart-137d8df5-3b53-4ba1-a687-a4b169e54a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029497993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.4029497993
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.1307334152
Short name T212
Test name
Test status
Simulation time 229313074 ps
CPU time 11.01 seconds
Started Mar 31 12:38:59 PM PDT 24
Finished Mar 31 12:39:11 PM PDT 24
Peak memory 195504 kb
Host smart-9330b6fd-92c1-4150-9df5-1b3abc243b50
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307334152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.1307334152
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.152621182
Short name T303
Test name
Test status
Simulation time 309036919 ps
CPU time 1.01 seconds
Started Mar 31 12:38:22 PM PDT 24
Finished Mar 31 12:38:23 PM PDT 24
Peak memory 197788 kb
Host smart-6ae612a3-acb1-41a5-8a05-f179c773c303
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152621182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.152621182
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.3353558901
Short name T287
Test name
Test status
Simulation time 33728789 ps
CPU time 0.94 seconds
Started Mar 31 12:38:23 PM PDT 24
Finished Mar 31 12:38:24 PM PDT 24
Peak memory 196052 kb
Host smart-536dd2fb-95dc-4a16-a46f-bc42d2419ee8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353558901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.3353558901
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.812852366
Short name T498
Test name
Test status
Simulation time 262319891 ps
CPU time 1.15 seconds
Started Mar 31 12:38:50 PM PDT 24
Finished Mar 31 12:38:51 PM PDT 24
Peak memory 196796 kb
Host smart-20ffbbba-03fc-4dae-9eac-1d80d20e7d9a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812852366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.gpio_intr_with_filter_rand_intr_event.812852366
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.4198723177
Short name T278
Test name
Test status
Simulation time 141986270 ps
CPU time 1.23 seconds
Started Mar 31 12:38:57 PM PDT 24
Finished Mar 31 12:38:59 PM PDT 24
Peak memory 196460 kb
Host smart-383ca787-82a2-4f6d-aa04-d5a539b826b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198723177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.4198723177
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.929068581
Short name T409
Test name
Test status
Simulation time 89551688 ps
CPU time 1.05 seconds
Started Mar 31 12:38:27 PM PDT 24
Finished Mar 31 12:38:28 PM PDT 24
Peak memory 196740 kb
Host smart-69956241-ac06-4878-bbe3-47666a5137ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929068581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.929068581
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.3317742401
Short name T697
Test name
Test status
Simulation time 70898186 ps
CPU time 1.22 seconds
Started Mar 31 12:38:25 PM PDT 24
Finished Mar 31 12:38:26 PM PDT 24
Peak memory 195972 kb
Host smart-07f2c083-5cd6-4374-8e10-5f60e8c7d9b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317742401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.3317742401
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.1495263963
Short name T480
Test name
Test status
Simulation time 128180279 ps
CPU time 1.81 seconds
Started Mar 31 12:38:57 PM PDT 24
Finished Mar 31 12:38:59 PM PDT 24
Peak memory 197308 kb
Host smart-010c04ed-9bf7-4916-886e-2dd9c6c881e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495263963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.1495263963
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.3669387300
Short name T694
Test name
Test status
Simulation time 67363173 ps
CPU time 1.15 seconds
Started Mar 31 12:38:24 PM PDT 24
Finished Mar 31 12:38:25 PM PDT 24
Peak memory 195748 kb
Host smart-5fb3afb3-c427-427c-b998-cf2a568b67ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669387300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.3669387300
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.2351710717
Short name T20
Test name
Test status
Simulation time 80243604 ps
CPU time 0.79 seconds
Started Mar 31 12:39:04 PM PDT 24
Finished Mar 31 12:39:04 PM PDT 24
Peak memory 195156 kb
Host smart-ea88701f-55aa-4feb-becd-d50b2f4dc8d7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351710717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.2351710717
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.3737542576
Short name T382
Test name
Test status
Simulation time 7661030703 ps
CPU time 201.98 seconds
Started Mar 31 12:38:35 PM PDT 24
Finished Mar 31 12:41:57 PM PDT 24
Peak memory 198136 kb
Host smart-83a4a593-6d40-41a3-bf2b-417443f143f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737542576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.3737542576
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.3415856987
Short name T392
Test name
Test status
Simulation time 668075350991 ps
CPU time 1298.36 seconds
Started Mar 31 12:38:26 PM PDT 24
Finished Mar 31 01:00:04 PM PDT 24
Peak memory 198128 kb
Host smart-8ccd5654-a05d-4b27-9c4e-c6454c1d4a8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3415856987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.3415856987
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.1434493481
Short name T682
Test name
Test status
Simulation time 12246091 ps
CPU time 0.57 seconds
Started Mar 31 12:38:33 PM PDT 24
Finished Mar 31 12:38:34 PM PDT 24
Peak memory 193936 kb
Host smart-acb2ef1e-9530-4ff6-b819-325d5f6eada1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434493481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.1434493481
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.3992882010
Short name T653
Test name
Test status
Simulation time 87031388 ps
CPU time 0.87 seconds
Started Mar 31 12:38:23 PM PDT 24
Finished Mar 31 12:38:24 PM PDT 24
Peak memory 196360 kb
Host smart-16ab2174-5ea9-455c-874a-c13fc236725e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992882010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.3992882010
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.4122118645
Short name T353
Test name
Test status
Simulation time 61127806 ps
CPU time 3.43 seconds
Started Mar 31 12:38:34 PM PDT 24
Finished Mar 31 12:38:43 PM PDT 24
Peak memory 196256 kb
Host smart-8171460b-c6c5-4429-bbfd-0e5a21161b8b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122118645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.4122118645
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.3825833559
Short name T318
Test name
Test status
Simulation time 33954748 ps
CPU time 0.77 seconds
Started Mar 31 12:38:24 PM PDT 24
Finished Mar 31 12:38:24 PM PDT 24
Peak memory 194728 kb
Host smart-785fb653-c950-48b8-b0f1-390abbe025a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825833559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.3825833559
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.506745231
Short name T579
Test name
Test status
Simulation time 41930281 ps
CPU time 0.81 seconds
Started Mar 31 12:38:47 PM PDT 24
Finished Mar 31 12:38:48 PM PDT 24
Peak memory 195460 kb
Host smart-f666b1cc-9de7-4763-abf5-475528453f02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506745231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.506745231
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.1934809081
Short name T98
Test name
Test status
Simulation time 302411976 ps
CPU time 3.02 seconds
Started Mar 31 12:38:35 PM PDT 24
Finished Mar 31 12:38:38 PM PDT 24
Peak memory 197948 kb
Host smart-94be5ab2-964e-4b5d-b3d8-f3c56fd5bba9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934809081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.1934809081
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.4099594689
Short name T387
Test name
Test status
Simulation time 355230067 ps
CPU time 2.76 seconds
Started Mar 31 12:38:35 PM PDT 24
Finished Mar 31 12:38:38 PM PDT 24
Peak memory 198056 kb
Host smart-148eb357-8ddd-44c6-9644-d1da4834e1c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099594689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.4099594689
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.2681525618
Short name T168
Test name
Test status
Simulation time 79166156 ps
CPU time 1.07 seconds
Started Mar 31 12:38:40 PM PDT 24
Finished Mar 31 12:38:41 PM PDT 24
Peak memory 195720 kb
Host smart-3b995db0-3db0-4d5e-b0c5-2ab9f6b936d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681525618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2681525618
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.2800064850
Short name T521
Test name
Test status
Simulation time 136221578 ps
CPU time 1.07 seconds
Started Mar 31 12:38:41 PM PDT 24
Finished Mar 31 12:38:43 PM PDT 24
Peak memory 196008 kb
Host smart-4bc4cc7d-2b07-47a3-ae15-f4ae5156bf0f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800064850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.2800064850
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.3009730225
Short name T495
Test name
Test status
Simulation time 2003264917 ps
CPU time 4.66 seconds
Started Mar 31 12:38:24 PM PDT 24
Finished Mar 31 12:38:32 PM PDT 24
Peak memory 197844 kb
Host smart-43a51c30-3fa8-4230-84c1-74947c555150
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009730225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.3009730225
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.3075472962
Short name T517
Test name
Test status
Simulation time 72488863 ps
CPU time 1.23 seconds
Started Mar 31 12:38:24 PM PDT 24
Finished Mar 31 12:38:25 PM PDT 24
Peak memory 198028 kb
Host smart-5f8b9b12-8d3e-420e-b813-d31ce09bedb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075472962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.3075472962
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.4232794388
Short name T220
Test name
Test status
Simulation time 841596284 ps
CPU time 1.41 seconds
Started Mar 31 12:38:26 PM PDT 24
Finished Mar 31 12:38:27 PM PDT 24
Peak memory 196308 kb
Host smart-48721709-c43f-44f3-8a85-e83b7b77746f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232794388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.4232794388
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.4223602358
Short name T215
Test name
Test status
Simulation time 6661702024 ps
CPU time 158.67 seconds
Started Mar 31 12:38:52 PM PDT 24
Finished Mar 31 12:41:31 PM PDT 24
Peak memory 198260 kb
Host smart-3640fda0-717c-4c2a-8aa6-dc39209b27a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223602358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.4223602358
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.3180077481
Short name T649
Test name
Test status
Simulation time 10746786 ps
CPU time 0.56 seconds
Started Mar 31 12:38:37 PM PDT 24
Finished Mar 31 12:38:38 PM PDT 24
Peak memory 193932 kb
Host smart-cdf75cb3-177e-4908-853b-85c992e03766
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180077481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.3180077481
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.1080079208
Short name T703
Test name
Test status
Simulation time 18118763 ps
CPU time 0.65 seconds
Started Mar 31 12:38:31 PM PDT 24
Finished Mar 31 12:38:32 PM PDT 24
Peak memory 194592 kb
Host smart-c2094dfe-7143-4009-8deb-aa0f06e25b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080079208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.1080079208
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.855227311
Short name T118
Test name
Test status
Simulation time 288302890 ps
CPU time 3.57 seconds
Started Mar 31 12:38:57 PM PDT 24
Finished Mar 31 12:39:01 PM PDT 24
Peak memory 195416 kb
Host smart-2fd4219f-d82a-4ee1-8650-c4146a754c0d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855227311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stres
s.855227311
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.802324668
Short name T375
Test name
Test status
Simulation time 259900167 ps
CPU time 0.93 seconds
Started Mar 31 12:38:37 PM PDT 24
Finished Mar 31 12:38:38 PM PDT 24
Peak memory 197124 kb
Host smart-0d62e482-94e8-46b1-9042-f6a22c2488b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802324668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.802324668
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.1023981956
Short name T531
Test name
Test status
Simulation time 28843773 ps
CPU time 0.82 seconds
Started Mar 31 12:38:31 PM PDT 24
Finished Mar 31 12:38:32 PM PDT 24
Peak memory 197576 kb
Host smart-aeb190e5-d673-41ab-b1ca-44ba7ac77c92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023981956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.1023981956
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.1790515890
Short name T142
Test name
Test status
Simulation time 50433822 ps
CPU time 2.02 seconds
Started Mar 31 12:38:46 PM PDT 24
Finished Mar 31 12:38:49 PM PDT 24
Peak memory 197980 kb
Host smart-bae7cf1d-2415-4153-acf5-73baf6dea547
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790515890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.1790515890
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.3993832574
Short name T673
Test name
Test status
Simulation time 82820635 ps
CPU time 2.02 seconds
Started Mar 31 12:38:56 PM PDT 24
Finished Mar 31 12:38:58 PM PDT 24
Peak memory 196668 kb
Host smart-2c05c00c-073d-4c10-98b9-40e34d51a8c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993832574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.3993832574
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.4106998592
Short name T689
Test name
Test status
Simulation time 57778602 ps
CPU time 1.17 seconds
Started Mar 31 12:38:29 PM PDT 24
Finished Mar 31 12:38:31 PM PDT 24
Peak memory 196600 kb
Host smart-822e28d7-b654-4ebb-9f71-655373e957e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106998592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.4106998592
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.2505627717
Short name T499
Test name
Test status
Simulation time 267295283 ps
CPU time 1.18 seconds
Started Mar 31 12:38:32 PM PDT 24
Finished Mar 31 12:38:33 PM PDT 24
Peak memory 195780 kb
Host smart-cae6c109-7ee9-458b-a3d7-7eb563c879df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505627717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.2505627717
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.1368196442
Short name T529
Test name
Test status
Simulation time 114298154 ps
CPU time 2.69 seconds
Started Mar 31 12:38:37 PM PDT 24
Finished Mar 31 12:38:40 PM PDT 24
Peak memory 198044 kb
Host smart-ef43303d-45f3-4532-af20-cba1071058b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368196442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.1368196442
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.1285625266
Short name T578
Test name
Test status
Simulation time 92192956 ps
CPU time 1.46 seconds
Started Mar 31 12:38:26 PM PDT 24
Finished Mar 31 12:38:27 PM PDT 24
Peak memory 197860 kb
Host smart-c0b9f0d3-8897-46ab-942e-72196042793d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285625266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.1285625266
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.110051461
Short name T562
Test name
Test status
Simulation time 110063992 ps
CPU time 1.06 seconds
Started Mar 31 12:38:27 PM PDT 24
Finished Mar 31 12:38:28 PM PDT 24
Peak memory 195488 kb
Host smart-63657580-292d-405f-8b6d-72f62dfaad32
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110051461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.110051461
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.1511893979
Short name T469
Test name
Test status
Simulation time 3034181008 ps
CPU time 39.65 seconds
Started Mar 31 12:38:34 PM PDT 24
Finished Mar 31 12:39:14 PM PDT 24
Peak memory 198124 kb
Host smart-7e68e429-1294-447f-bf01-67f698e0c6ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511893979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.1511893979
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.2479163389
Short name T31
Test name
Test status
Simulation time 17599449241 ps
CPU time 460.7 seconds
Started Mar 31 12:38:31 PM PDT 24
Finished Mar 31 12:46:12 PM PDT 24
Peak memory 198316 kb
Host smart-606daf39-ec3a-4e8e-88a4-57855e96167c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2479163389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.2479163389
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.2397116686
Short name T401
Test name
Test status
Simulation time 14832210 ps
CPU time 0.58 seconds
Started Mar 31 12:38:30 PM PDT 24
Finished Mar 31 12:38:30 PM PDT 24
Peak memory 194644 kb
Host smart-3c080d31-ce71-44e8-810a-91ee64791429
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397116686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.2397116686
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.1264796493
Short name T497
Test name
Test status
Simulation time 23925900 ps
CPU time 0.87 seconds
Started Mar 31 12:39:00 PM PDT 24
Finished Mar 31 12:39:02 PM PDT 24
Peak memory 196160 kb
Host smart-5aa00cf1-5f02-4afc-abfe-f5b5fcde2ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264796493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.1264796493
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.3290763106
Short name T22
Test name
Test status
Simulation time 1778628554 ps
CPU time 15.57 seconds
Started Mar 31 12:38:33 PM PDT 24
Finished Mar 31 12:38:49 PM PDT 24
Peak memory 196704 kb
Host smart-e8851dee-ea2b-4175-be99-cf4f6527f07a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290763106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.3290763106
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.1845871860
Short name T666
Test name
Test status
Simulation time 54380357 ps
CPU time 0.9 seconds
Started Mar 31 12:38:42 PM PDT 24
Finished Mar 31 12:38:43 PM PDT 24
Peak memory 196720 kb
Host smart-e8bc28a2-37d0-45e4-8118-471f9f11f2ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845871860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.1845871860
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.3624632417
Short name T410
Test name
Test status
Simulation time 60922434 ps
CPU time 0.96 seconds
Started Mar 31 12:38:53 PM PDT 24
Finished Mar 31 12:38:55 PM PDT 24
Peak memory 196084 kb
Host smart-577b7436-2c1b-44e6-8569-cd72a630b068
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624632417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.3624632417
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.1615363219
Short name T660
Test name
Test status
Simulation time 712968398 ps
CPU time 3.59 seconds
Started Mar 31 12:38:55 PM PDT 24
Finished Mar 31 12:38:59 PM PDT 24
Peak memory 198044 kb
Host smart-7bf90264-7c94-4916-b27c-9354db0fd224
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615363219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.1615363219
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.1906352747
Short name T700
Test name
Test status
Simulation time 241152185 ps
CPU time 2.75 seconds
Started Mar 31 12:38:56 PM PDT 24
Finished Mar 31 12:38:59 PM PDT 24
Peak memory 197176 kb
Host smart-030edfe7-6440-47df-90d9-92faa59cee67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906352747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.1906352747
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.1125513131
Short name T475
Test name
Test status
Simulation time 180753093 ps
CPU time 0.86 seconds
Started Mar 31 12:38:28 PM PDT 24
Finished Mar 31 12:38:29 PM PDT 24
Peak memory 195964 kb
Host smart-77469fab-4bcf-4d5d-be0b-ca5e89af0402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125513131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.1125513131
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.2453759736
Short name T300
Test name
Test status
Simulation time 57357512 ps
CPU time 1.14 seconds
Started Mar 31 12:39:06 PM PDT 24
Finished Mar 31 12:39:07 PM PDT 24
Peak memory 196772 kb
Host smart-ee34c551-6b6c-4925-b2f1-95b910e409bc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453759736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.2453759736
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.3299438228
Short name T5
Test name
Test status
Simulation time 440263963 ps
CPU time 1.76 seconds
Started Mar 31 12:38:32 PM PDT 24
Finished Mar 31 12:38:34 PM PDT 24
Peak memory 197972 kb
Host smart-7a391cd5-f003-489d-88a5-cb5931365716
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299438228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.3299438228
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.2137963848
Short name T262
Test name
Test status
Simulation time 167786177 ps
CPU time 0.97 seconds
Started Mar 31 12:38:38 PM PDT 24
Finished Mar 31 12:38:40 PM PDT 24
Peak memory 196220 kb
Host smart-0a67646e-55c9-41e7-81bc-53579f5317d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137963848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.2137963848
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.3220899243
Short name T52
Test name
Test status
Simulation time 80477180 ps
CPU time 1.44 seconds
Started Mar 31 12:38:55 PM PDT 24
Finished Mar 31 12:38:57 PM PDT 24
Peak memory 196800 kb
Host smart-9559f131-811d-4341-974d-2b7ed715f4ec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220899243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.3220899243
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.327974581
Short name T681
Test name
Test status
Simulation time 3647383707 ps
CPU time 91.75 seconds
Started Mar 31 12:38:37 PM PDT 24
Finished Mar 31 12:40:09 PM PDT 24
Peak memory 198188 kb
Host smart-ba9a4dc6-4013-4351-a4fe-a109f2627dc4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327974581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.g
pio_stress_all.327974581
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.3742767590
Short name T427
Test name
Test status
Simulation time 80326817255 ps
CPU time 624.85 seconds
Started Mar 31 12:38:55 PM PDT 24
Finished Mar 31 12:49:21 PM PDT 24
Peak memory 198272 kb
Host smart-fcac841a-60ae-43c8-b7e7-1684b83eae86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3742767590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.3742767590
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.4088531395
Short name T143
Test name
Test status
Simulation time 12829619 ps
CPU time 0.6 seconds
Started Mar 31 12:38:42 PM PDT 24
Finished Mar 31 12:38:43 PM PDT 24
Peak memory 193936 kb
Host smart-a9fd57f8-9473-4220-841d-d6eeadb4861f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088531395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.4088531395
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.3617091185
Short name T580
Test name
Test status
Simulation time 85773719 ps
CPU time 0.68 seconds
Started Mar 31 12:38:53 PM PDT 24
Finished Mar 31 12:38:54 PM PDT 24
Peak memory 193904 kb
Host smart-3815184c-33e6-459e-9194-53aade45408d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617091185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.3617091185
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.858366200
Short name T202
Test name
Test status
Simulation time 489430035 ps
CPU time 12.5 seconds
Started Mar 31 12:38:31 PM PDT 24
Finished Mar 31 12:38:44 PM PDT 24
Peak memory 196820 kb
Host smart-d7e3c4d1-a787-4483-9145-e13406abdf9f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858366200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stres
s.858366200
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.3024351151
Short name T161
Test name
Test status
Simulation time 258003258 ps
CPU time 0.94 seconds
Started Mar 31 12:38:37 PM PDT 24
Finished Mar 31 12:38:38 PM PDT 24
Peak memory 196604 kb
Host smart-b0221323-9d6a-48f6-a196-879548cf700f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024351151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.3024351151
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.981976298
Short name T304
Test name
Test status
Simulation time 110991938 ps
CPU time 0.93 seconds
Started Mar 31 12:38:29 PM PDT 24
Finished Mar 31 12:38:30 PM PDT 24
Peak memory 196892 kb
Host smart-3d11cd89-cfe5-456c-bf45-3285f829eaa0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981976298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.981976298
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.4162083963
Short name T408
Test name
Test status
Simulation time 80273068 ps
CPU time 1.74 seconds
Started Mar 31 12:38:53 PM PDT 24
Finished Mar 31 12:38:55 PM PDT 24
Peak memory 196640 kb
Host smart-e26be04f-ccdf-47c0-a16c-f35ed795d50c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162083963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.4162083963
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.584821776
Short name T388
Test name
Test status
Simulation time 59653520 ps
CPU time 1.94 seconds
Started Mar 31 12:38:57 PM PDT 24
Finished Mar 31 12:38:59 PM PDT 24
Peak memory 196128 kb
Host smart-4f42d25a-bee3-4c4b-8929-2a45b2671204
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584821776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger.
584821776
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.3345923670
Short name T371
Test name
Test status
Simulation time 428678038 ps
CPU time 1.32 seconds
Started Mar 31 12:38:52 PM PDT 24
Finished Mar 31 12:38:53 PM PDT 24
Peak memory 197992 kb
Host smart-e793eb35-26f0-4516-b631-0c633d0b9b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345923670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.3345923670
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.2291457869
Short name T489
Test name
Test status
Simulation time 49000055 ps
CPU time 1.04 seconds
Started Mar 31 12:38:31 PM PDT 24
Finished Mar 31 12:38:32 PM PDT 24
Peak memory 195944 kb
Host smart-87f951c3-cbda-4ff4-8595-757459fb00f5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291457869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.2291457869
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.1905901393
Short name T7
Test name
Test status
Simulation time 1601722011 ps
CPU time 5.34 seconds
Started Mar 31 12:38:34 PM PDT 24
Finished Mar 31 12:38:39 PM PDT 24
Peak memory 197948 kb
Host smart-5fa3aec2-4593-4152-9e0b-f3bc714a1ba2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905901393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.1905901393
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.1626406413
Short name T109
Test name
Test status
Simulation time 140689675 ps
CPU time 0.85 seconds
Started Mar 31 12:38:35 PM PDT 24
Finished Mar 31 12:38:36 PM PDT 24
Peak memory 196024 kb
Host smart-07204597-11d6-4fd4-bd57-c3d992d4e549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626406413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.1626406413
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.2195318979
Short name T13
Test name
Test status
Simulation time 134486149 ps
CPU time 1.22 seconds
Started Mar 31 12:38:56 PM PDT 24
Finished Mar 31 12:38:58 PM PDT 24
Peak memory 196772 kb
Host smart-7b300e39-de03-4b84-bfd2-4d7d6868e07f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195318979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.2195318979
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.1612133088
Short name T308
Test name
Test status
Simulation time 3941500421 ps
CPU time 44.29 seconds
Started Mar 31 12:39:10 PM PDT 24
Finished Mar 31 12:39:55 PM PDT 24
Peak memory 198116 kb
Host smart-631a97ef-c315-43f3-971f-00e4363bfe36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612133088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.1612133088
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.3270070335
Short name T59
Test name
Test status
Simulation time 218832737893 ps
CPU time 1244.16 seconds
Started Mar 31 12:38:56 PM PDT 24
Finished Mar 31 12:59:41 PM PDT 24
Peak memory 198252 kb
Host smart-6f136446-9112-4472-a140-8b47b344e076
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3270070335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.3270070335
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.3333516356
Short name T524
Test name
Test status
Simulation time 13103219 ps
CPU time 0.58 seconds
Started Mar 31 12:38:02 PM PDT 24
Finished Mar 31 12:38:03 PM PDT 24
Peak memory 193928 kb
Host smart-977588b8-96da-4c31-b89b-a7c4a6698230
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333516356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.3333516356
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.3285928240
Short name T654
Test name
Test status
Simulation time 23570919 ps
CPU time 0.81 seconds
Started Mar 31 12:37:50 PM PDT 24
Finished Mar 31 12:37:51 PM PDT 24
Peak memory 195312 kb
Host smart-f5a05e37-cda3-43b9-9d66-d2148849185d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285928240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.3285928240
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.1189829414
Short name T530
Test name
Test status
Simulation time 2162753477 ps
CPU time 27.3 seconds
Started Mar 31 12:37:41 PM PDT 24
Finished Mar 31 12:38:08 PM PDT 24
Peak memory 195536 kb
Host smart-5ebe1994-44a6-4f4b-9ece-631290ba1eba
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189829414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.1189829414
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.3238071070
Short name T709
Test name
Test status
Simulation time 36865863 ps
CPU time 0.71 seconds
Started Mar 31 12:37:49 PM PDT 24
Finished Mar 31 12:37:50 PM PDT 24
Peak memory 195420 kb
Host smart-6e8fb116-6b85-4bcc-8390-ac31f3d0fb0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238071070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.3238071070
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.4101676283
Short name T180
Test name
Test status
Simulation time 89359057 ps
CPU time 1.38 seconds
Started Mar 31 12:37:57 PM PDT 24
Finished Mar 31 12:37:59 PM PDT 24
Peak memory 198016 kb
Host smart-55802073-60fe-4482-8158-aea9ddb0ad15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101676283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.4101676283
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.4140308338
Short name T550
Test name
Test status
Simulation time 28221574 ps
CPU time 1.18 seconds
Started Mar 31 12:37:45 PM PDT 24
Finished Mar 31 12:37:46 PM PDT 24
Peak memory 198020 kb
Host smart-938abd66-2fe1-4224-9f3d-a0008350b728
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140308338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.4140308338
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.122363890
Short name T657
Test name
Test status
Simulation time 70067943 ps
CPU time 2.05 seconds
Started Mar 31 12:38:01 PM PDT 24
Finished Mar 31 12:38:04 PM PDT 24
Peak memory 196460 kb
Host smart-055d6854-53bc-4df5-8c43-a24b3c416495
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122363890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.122363890
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.2899195622
Short name T117
Test name
Test status
Simulation time 20792899 ps
CPU time 0.66 seconds
Started Mar 31 12:37:50 PM PDT 24
Finished Mar 31 12:37:51 PM PDT 24
Peak memory 194320 kb
Host smart-928cca31-7203-493f-8c76-5dd8b55d9602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899195622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.2899195622
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.2709439429
Short name T183
Test name
Test status
Simulation time 113699695 ps
CPU time 1.17 seconds
Started Mar 31 12:38:00 PM PDT 24
Finished Mar 31 12:38:01 PM PDT 24
Peak memory 196108 kb
Host smart-9441d402-28d6-433b-9473-c3c0b40cf2ff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709439429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.2709439429
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.1789404900
Short name T519
Test name
Test status
Simulation time 301206750 ps
CPU time 4.16 seconds
Started Mar 31 12:37:44 PM PDT 24
Finished Mar 31 12:37:48 PM PDT 24
Peak memory 198016 kb
Host smart-03c1a6fd-afe5-42e6-a19e-1b43772c1ebc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789404900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.1789404900
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.83807660
Short name T50
Test name
Test status
Simulation time 121748453 ps
CPU time 0.98 seconds
Started Mar 31 12:37:43 PM PDT 24
Finished Mar 31 12:37:44 PM PDT 24
Peak memory 214960 kb
Host smart-7ff3f07a-12d6-4a3c-affc-a6014c2860da
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83807660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.83807660
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.3876991464
Short name T370
Test name
Test status
Simulation time 27850238 ps
CPU time 1 seconds
Started Mar 31 12:38:06 PM PDT 24
Finished Mar 31 12:38:07 PM PDT 24
Peak memory 196372 kb
Host smart-71ab0119-83ed-44cd-9373-9b41c0a51516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876991464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.3876991464
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.3872987851
Short name T438
Test name
Test status
Simulation time 46489649 ps
CPU time 1.1 seconds
Started Mar 31 12:38:02 PM PDT 24
Finished Mar 31 12:38:03 PM PDT 24
Peak memory 196680 kb
Host smart-cbe60c80-86ba-48ba-80b7-67bd0df5a469
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872987851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.3872987851
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_alert_test.592253077
Short name T245
Test name
Test status
Simulation time 11950685 ps
CPU time 0.59 seconds
Started Mar 31 12:38:53 PM PDT 24
Finished Mar 31 12:38:54 PM PDT 24
Peak memory 193812 kb
Host smart-2b2028ae-2d7e-46cb-9833-2ebe97b7e716
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592253077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.592253077
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.4002216139
Short name T155
Test name
Test status
Simulation time 81498352 ps
CPU time 0.95 seconds
Started Mar 31 12:38:42 PM PDT 24
Finished Mar 31 12:38:43 PM PDT 24
Peak memory 196360 kb
Host smart-5e741cf6-76d2-4ac3-aa88-ed95f96439a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002216139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.4002216139
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.3641471193
Short name T621
Test name
Test status
Simulation time 296251273 ps
CPU time 10.44 seconds
Started Mar 31 12:38:42 PM PDT 24
Finished Mar 31 12:38:52 PM PDT 24
Peak memory 196684 kb
Host smart-10543c2d-4b8f-4683-9727-5e5ac41d2929
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641471193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.3641471193
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.3979335419
Short name T317
Test name
Test status
Simulation time 197899279 ps
CPU time 1.04 seconds
Started Mar 31 12:38:56 PM PDT 24
Finished Mar 31 12:38:57 PM PDT 24
Peak memory 197068 kb
Host smart-729eeed3-c270-47f4-883d-dcd777e73a68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979335419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.3979335419
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.2892486654
Short name T465
Test name
Test status
Simulation time 25383778 ps
CPU time 0.69 seconds
Started Mar 31 12:38:55 PM PDT 24
Finished Mar 31 12:38:55 PM PDT 24
Peak memory 194384 kb
Host smart-f76a410a-aaf0-4015-887a-0513d0dc99c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892486654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.2892486654
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.3413510390
Short name T124
Test name
Test status
Simulation time 37902147 ps
CPU time 1.6 seconds
Started Mar 31 12:39:05 PM PDT 24
Finished Mar 31 12:39:06 PM PDT 24
Peak memory 197976 kb
Host smart-53b7cb7b-a0aa-480e-bc5d-45757082abeb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413510390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.3413510390
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.3133379069
Short name T548
Test name
Test status
Simulation time 80005576 ps
CPU time 1.72 seconds
Started Mar 31 12:38:42 PM PDT 24
Finished Mar 31 12:38:44 PM PDT 24
Peak memory 195844 kb
Host smart-c66566fe-39e0-4f71-8692-188a3d56ebfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133379069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.3133379069
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.898816305
Short name T429
Test name
Test status
Simulation time 59785674 ps
CPU time 0.98 seconds
Started Mar 31 12:38:55 PM PDT 24
Finished Mar 31 12:38:57 PM PDT 24
Peak memory 196380 kb
Host smart-aba257a8-c3a5-4be8-9790-1dd33ddc2414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898816305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.898816305
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2811568727
Short name T347
Test name
Test status
Simulation time 22547778 ps
CPU time 0.85 seconds
Started Mar 31 12:38:44 PM PDT 24
Finished Mar 31 12:38:46 PM PDT 24
Peak memory 197220 kb
Host smart-bf4963bb-119e-4cff-be63-b8a273610114
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811568727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2811568727
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.2334132191
Short name T684
Test name
Test status
Simulation time 167055457 ps
CPU time 1.32 seconds
Started Mar 31 12:38:56 PM PDT 24
Finished Mar 31 12:38:57 PM PDT 24
Peak memory 197956 kb
Host smart-6b5da411-8d66-4eb2-bfa2-df818b86c0a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334132191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.2334132191
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.3024296198
Short name T494
Test name
Test status
Simulation time 31512256 ps
CPU time 0.9 seconds
Started Mar 31 12:38:39 PM PDT 24
Finished Mar 31 12:38:41 PM PDT 24
Peak memory 196404 kb
Host smart-dc57cbfd-a559-4516-a596-95ffa4bb9180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024296198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.3024296198
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.1409314930
Short name T185
Test name
Test status
Simulation time 65019164 ps
CPU time 1.23 seconds
Started Mar 31 12:38:41 PM PDT 24
Finished Mar 31 12:38:42 PM PDT 24
Peak memory 196664 kb
Host smart-21360822-cbd9-48eb-957d-e5c65406df05
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409314930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.1409314930
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.2152029095
Short name T372
Test name
Test status
Simulation time 10802420414 ps
CPU time 145.98 seconds
Started Mar 31 12:39:07 PM PDT 24
Finished Mar 31 12:41:34 PM PDT 24
Peak memory 198196 kb
Host smart-97bd970b-9330-48f8-9af6-1dc084c93d5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152029095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.2152029095
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.35400608
Short name T538
Test name
Test status
Simulation time 85836875786 ps
CPU time 568.79 seconds
Started Mar 31 12:38:59 PM PDT 24
Finished Mar 31 12:48:28 PM PDT 24
Peak memory 198144 kb
Host smart-955cce62-11db-4ac9-8e1c-15068aa08840
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=35400608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.35400608
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.235103845
Short name T595
Test name
Test status
Simulation time 11637699 ps
CPU time 0.57 seconds
Started Mar 31 12:38:37 PM PDT 24
Finished Mar 31 12:38:38 PM PDT 24
Peak memory 193876 kb
Host smart-a4b6c3e0-0047-4dc3-9dcf-fc74996d52e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235103845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.235103845
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.1309579153
Short name T467
Test name
Test status
Simulation time 18008038 ps
CPU time 0.68 seconds
Started Mar 31 12:38:40 PM PDT 24
Finished Mar 31 12:38:41 PM PDT 24
Peak memory 194756 kb
Host smart-b566347d-0d30-4b92-b775-46af637d4ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309579153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.1309579153
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.4149941658
Short name T315
Test name
Test status
Simulation time 3206999582 ps
CPU time 24.3 seconds
Started Mar 31 12:39:07 PM PDT 24
Finished Mar 31 12:39:32 PM PDT 24
Peak memory 197044 kb
Host smart-6437a042-13ec-40d7-9fa2-090b572b38c3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149941658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.4149941658
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.3099198867
Short name T203
Test name
Test status
Simulation time 49785392 ps
CPU time 0.81 seconds
Started Mar 31 12:38:44 PM PDT 24
Finished Mar 31 12:38:45 PM PDT 24
Peak memory 195908 kb
Host smart-dffe6a12-cbc7-41d4-aa6c-a07f42ae8448
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099198867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.3099198867
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.3910640261
Short name T295
Test name
Test status
Simulation time 524136718 ps
CPU time 1.47 seconds
Started Mar 31 12:38:53 PM PDT 24
Finished Mar 31 12:38:54 PM PDT 24
Peak memory 197248 kb
Host smart-a78a72f5-2940-4701-9f7a-48440ce0a384
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910640261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.3910640261
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.536470149
Short name T693
Test name
Test status
Simulation time 101610135 ps
CPU time 1.4 seconds
Started Mar 31 12:38:57 PM PDT 24
Finished Mar 31 12:38:58 PM PDT 24
Peak memory 196572 kb
Host smart-4f50b7a7-1823-46e9-b50c-c9c01b1d2060
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536470149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.gpio_intr_with_filter_rand_intr_event.536470149
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.2805357223
Short name T447
Test name
Test status
Simulation time 94602109 ps
CPU time 1.85 seconds
Started Mar 31 12:38:41 PM PDT 24
Finished Mar 31 12:38:43 PM PDT 24
Peak memory 196076 kb
Host smart-bf003eaa-500c-4992-9f93-6fd0f6f7056d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805357223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.2805357223
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.790611255
Short name T145
Test name
Test status
Simulation time 45433053 ps
CPU time 0.65 seconds
Started Mar 31 12:38:41 PM PDT 24
Finished Mar 31 12:38:42 PM PDT 24
Peak memory 194964 kb
Host smart-e7d85bd1-d83e-4160-8bda-4aeb5d99931a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790611255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.790611255
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.4057990822
Short name T281
Test name
Test status
Simulation time 118445010 ps
CPU time 1.1 seconds
Started Mar 31 12:38:42 PM PDT 24
Finished Mar 31 12:38:43 PM PDT 24
Peak memory 196692 kb
Host smart-dc322550-d550-462b-9e9a-a16143f084ed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057990822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.4057990822
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.426788811
Short name T404
Test name
Test status
Simulation time 106630248 ps
CPU time 4.57 seconds
Started Mar 31 12:38:50 PM PDT 24
Finished Mar 31 12:38:55 PM PDT 24
Peak memory 197904 kb
Host smart-1066fbec-354a-4880-b682-bfac0b5a9187
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426788811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ran
dom_long_reg_writes_reg_reads.426788811
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.3813650890
Short name T526
Test name
Test status
Simulation time 180379670 ps
CPU time 1.22 seconds
Started Mar 31 12:39:08 PM PDT 24
Finished Mar 31 12:39:10 PM PDT 24
Peak memory 196436 kb
Host smart-e8715fef-8827-44af-b159-f86dbc2a7ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813650890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.3813650890
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2396853634
Short name T223
Test name
Test status
Simulation time 135520114 ps
CPU time 0.92 seconds
Started Mar 31 12:38:54 PM PDT 24
Finished Mar 31 12:38:55 PM PDT 24
Peak memory 197160 kb
Host smart-6e25b2a0-9680-43fa-b875-26d409611b31
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396853634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2396853634
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.1160521087
Short name T485
Test name
Test status
Simulation time 334719875595 ps
CPU time 183.61 seconds
Started Mar 31 12:38:57 PM PDT 24
Finished Mar 31 12:42:00 PM PDT 24
Peak memory 198140 kb
Host smart-8ce4ecbf-98da-4683-87d8-d73233265a04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160521087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.1160521087
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.428417561
Short name T32
Test name
Test status
Simulation time 307150716602 ps
CPU time 1363.66 seconds
Started Mar 31 12:39:05 PM PDT 24
Finished Mar 31 01:01:49 PM PDT 24
Peak memory 198112 kb
Host smart-2b5e8ad4-3b8c-4f09-ae5f-e58b20e55725
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=428417561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.428417561
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.4221510886
Short name T575
Test name
Test status
Simulation time 43224875 ps
CPU time 0.57 seconds
Started Mar 31 12:38:46 PM PDT 24
Finished Mar 31 12:38:47 PM PDT 24
Peak memory 193932 kb
Host smart-6f309cf2-7461-4d3a-a676-614e6f9d9f03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221510886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.4221510886
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.4224456044
Short name T134
Test name
Test status
Simulation time 46398675 ps
CPU time 0.73 seconds
Started Mar 31 12:38:59 PM PDT 24
Finished Mar 31 12:39:00 PM PDT 24
Peak memory 194792 kb
Host smart-7821d45e-c928-42af-8707-cb7ef5eb081a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224456044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.4224456044
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.3775110205
Short name T19
Test name
Test status
Simulation time 2698604310 ps
CPU time 19.84 seconds
Started Mar 31 12:38:58 PM PDT 24
Finished Mar 31 12:39:18 PM PDT 24
Peak memory 196656 kb
Host smart-4aa64842-54f1-4983-abd8-c7b69535920a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775110205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.3775110205
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.1828730019
Short name T386
Test name
Test status
Simulation time 178670663 ps
CPU time 1.3 seconds
Started Mar 31 12:38:39 PM PDT 24
Finished Mar 31 12:38:41 PM PDT 24
Peak memory 196336 kb
Host smart-cf3961b5-0904-4110-bece-46f3307cce2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828730019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.1828730019
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.3132731469
Short name T539
Test name
Test status
Simulation time 39889915 ps
CPU time 0.9 seconds
Started Mar 31 12:38:56 PM PDT 24
Finished Mar 31 12:38:57 PM PDT 24
Peak memory 197496 kb
Host smart-d29b9706-e95f-434c-ba28-fe29a279ecb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132731469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.3132731469
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.1619644745
Short name T96
Test name
Test status
Simulation time 119084938 ps
CPU time 2.36 seconds
Started Mar 31 12:38:40 PM PDT 24
Finished Mar 31 12:38:43 PM PDT 24
Peak memory 198020 kb
Host smart-f71361b8-4719-4996-ab99-ecda0890a910
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619644745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.1619644745
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.4070042794
Short name T24
Test name
Test status
Simulation time 51296945 ps
CPU time 1.61 seconds
Started Mar 31 12:38:38 PM PDT 24
Finished Mar 31 12:38:40 PM PDT 24
Peak memory 195968 kb
Host smart-81961399-faa8-4990-8f20-8974c0438ccc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070042794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.4070042794
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3530026450
Short name T312
Test name
Test status
Simulation time 328400681 ps
CPU time 1.38 seconds
Started Mar 31 12:38:42 PM PDT 24
Finished Mar 31 12:38:43 PM PDT 24
Peak memory 196912 kb
Host smart-14377249-c9ad-4c82-a349-27b337562132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530026450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3530026450
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.1852858265
Short name T623
Test name
Test status
Simulation time 28963150 ps
CPU time 1.05 seconds
Started Mar 31 12:39:16 PM PDT 24
Finished Mar 31 12:39:18 PM PDT 24
Peak memory 196052 kb
Host smart-f6cfb030-4102-400c-b79a-ca6604fa87c7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852858265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.1852858265
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.4191672862
Short name T10
Test name
Test status
Simulation time 788613408 ps
CPU time 4.75 seconds
Started Mar 31 12:38:54 PM PDT 24
Finished Mar 31 12:38:59 PM PDT 24
Peak memory 198000 kb
Host smart-2bd3e82f-6e5b-4150-979c-ab8341f8c22b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191672862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.4191672862
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.1725870498
Short name T555
Test name
Test status
Simulation time 64990273 ps
CPU time 0.93 seconds
Started Mar 31 12:38:39 PM PDT 24
Finished Mar 31 12:38:40 PM PDT 24
Peak memory 196528 kb
Host smart-2d6b29a9-c795-401f-aa25-09fea33b7154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725870498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.1725870498
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.693608652
Short name T667
Test name
Test status
Simulation time 794513035 ps
CPU time 1.27 seconds
Started Mar 31 12:38:40 PM PDT 24
Finished Mar 31 12:38:42 PM PDT 24
Peak memory 196680 kb
Host smart-f9411db3-9a62-4000-9a59-0f80ace648d0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693608652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.693608652
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.3672304747
Short name T448
Test name
Test status
Simulation time 69497138233 ps
CPU time 135.01 seconds
Started Mar 31 12:39:04 PM PDT 24
Finished Mar 31 12:41:19 PM PDT 24
Peak memory 198220 kb
Host smart-78191342-497e-4dae-a089-c350b3432898
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672304747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.3672304747
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.1839930141
Short name T63
Test name
Test status
Simulation time 305068094321 ps
CPU time 2066.99 seconds
Started Mar 31 12:38:41 PM PDT 24
Finished Mar 31 01:13:09 PM PDT 24
Peak memory 198260 kb
Host smart-ea319452-c26d-480d-860d-74880e696845
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1839930141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.1839930141
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.2369355021
Short name T528
Test name
Test status
Simulation time 41087225 ps
CPU time 0.57 seconds
Started Mar 31 12:38:57 PM PDT 24
Finished Mar 31 12:38:58 PM PDT 24
Peak memory 193488 kb
Host smart-97309ec4-ee55-4d35-8ad4-1c8943a94c74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369355021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.2369355021
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.2810720416
Short name T330
Test name
Test status
Simulation time 31324487 ps
CPU time 0.78 seconds
Started Mar 31 12:39:01 PM PDT 24
Finished Mar 31 12:39:02 PM PDT 24
Peak memory 196112 kb
Host smart-49b1e00e-2eb1-4013-a495-070821fa5a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810720416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.2810720416
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.2644920903
Short name T291
Test name
Test status
Simulation time 520507870 ps
CPU time 13.89 seconds
Started Mar 31 12:39:07 PM PDT 24
Finished Mar 31 12:39:21 PM PDT 24
Peak memory 196908 kb
Host smart-34b45d43-e77b-4d61-be10-48fd97031be0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644920903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.2644920903
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.692861273
Short name T516
Test name
Test status
Simulation time 202226685 ps
CPU time 0.82 seconds
Started Mar 31 12:38:58 PM PDT 24
Finished Mar 31 12:38:59 PM PDT 24
Peak memory 196088 kb
Host smart-93ee4d52-6f68-43de-ac63-460166740838
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692861273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.692861273
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.1912511339
Short name T336
Test name
Test status
Simulation time 110369721 ps
CPU time 1.15 seconds
Started Mar 31 12:38:47 PM PDT 24
Finished Mar 31 12:38:49 PM PDT 24
Peak memory 196756 kb
Host smart-179f1dda-a62b-4946-b8fb-27a573e7eeef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912511339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.1912511339
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.134868812
Short name T390
Test name
Test status
Simulation time 69048096 ps
CPU time 2.8 seconds
Started Mar 31 12:39:01 PM PDT 24
Finished Mar 31 12:39:04 PM PDT 24
Peak memory 198228 kb
Host smart-bdde9477-4361-4c12-887a-d9371c10f73e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134868812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.gpio_intr_with_filter_rand_intr_event.134868812
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.1966919810
Short name T299
Test name
Test status
Simulation time 151054619 ps
CPU time 2.22 seconds
Started Mar 31 12:39:04 PM PDT 24
Finished Mar 31 12:39:07 PM PDT 24
Peak memory 195804 kb
Host smart-ec1500f6-5b02-46dc-b2d6-0711f7f1cf73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966919810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.1966919810
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.804116264
Short name T652
Test name
Test status
Simulation time 609596013 ps
CPU time 1.34 seconds
Started Mar 31 12:39:07 PM PDT 24
Finished Mar 31 12:39:08 PM PDT 24
Peak memory 197104 kb
Host smart-01593bf5-8a8e-4b40-a53f-12cf82fac9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804116264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.804116264
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.28684923
Short name T171
Test name
Test status
Simulation time 49496405 ps
CPU time 1.06 seconds
Started Mar 31 12:38:49 PM PDT 24
Finished Mar 31 12:38:50 PM PDT 24
Peak memory 196748 kb
Host smart-7c0799f1-e0b7-4cfc-a9cd-ff7ef401ed60
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28684923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullup_
pulldown.28684923
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.372074641
Short name T137
Test name
Test status
Simulation time 50989585 ps
CPU time 2.32 seconds
Started Mar 31 12:38:52 PM PDT 24
Finished Mar 31 12:38:55 PM PDT 24
Peak memory 198004 kb
Host smart-32a721ef-b65b-446c-b184-2f5e4c4bf620
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372074641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ran
dom_long_reg_writes_reg_reads.372074641
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.3486635394
Short name T643
Test name
Test status
Simulation time 70385199 ps
CPU time 1.17 seconds
Started Mar 31 12:38:52 PM PDT 24
Finished Mar 31 12:38:54 PM PDT 24
Peak memory 195560 kb
Host smart-3653d431-ef21-4038-8e5b-ad8a7e0ad541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486635394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.3486635394
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.1637560705
Short name T641
Test name
Test status
Simulation time 40048102 ps
CPU time 1.15 seconds
Started Mar 31 12:39:04 PM PDT 24
Finished Mar 31 12:39:05 PM PDT 24
Peak memory 195804 kb
Host smart-b7c5323d-ede3-4570-a62c-a12f382e75a7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637560705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.1637560705
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.3107178305
Short name T600
Test name
Test status
Simulation time 7337981701 ps
CPU time 95.02 seconds
Started Mar 31 12:39:14 PM PDT 24
Finished Mar 31 12:40:50 PM PDT 24
Peak memory 198152 kb
Host smart-2b24afc1-d2f0-435b-8759-6e3226791699
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107178305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.3107178305
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.716795149
Short name T94
Test name
Test status
Simulation time 523173735494 ps
CPU time 2560.74 seconds
Started Mar 31 12:39:05 PM PDT 24
Finished Mar 31 01:21:46 PM PDT 24
Peak memory 198204 kb
Host smart-e007621d-0e96-429c-9bf5-86f69aba71e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=716795149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.716795149
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.2256445511
Short name T459
Test name
Test status
Simulation time 31625658 ps
CPU time 0.55 seconds
Started Mar 31 12:39:06 PM PDT 24
Finished Mar 31 12:39:06 PM PDT 24
Peak memory 193952 kb
Host smart-b92dc73d-9f01-4880-9b56-69386d5f4406
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256445511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.2256445511
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.2141100072
Short name T416
Test name
Test status
Simulation time 50810150 ps
CPU time 0.82 seconds
Started Mar 31 12:38:47 PM PDT 24
Finished Mar 31 12:38:48 PM PDT 24
Peak memory 195560 kb
Host smart-e783dd57-f1b8-428f-b903-4a85094c403d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141100072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.2141100072
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.3816669740
Short name T473
Test name
Test status
Simulation time 258879385 ps
CPU time 12.67 seconds
Started Mar 31 12:39:02 PM PDT 24
Finished Mar 31 12:39:15 PM PDT 24
Peak memory 195456 kb
Host smart-dbd83a7c-c8a6-42b6-9e10-0a30fc3d649e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816669740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.3816669740
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.671568663
Short name T174
Test name
Test status
Simulation time 73467565 ps
CPU time 0.94 seconds
Started Mar 31 12:39:02 PM PDT 24
Finished Mar 31 12:39:03 PM PDT 24
Peak memory 197736 kb
Host smart-e977e81f-9b9b-497b-a6d6-722dda49672a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671568663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.671568663
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.3423190926
Short name T36
Test name
Test status
Simulation time 54024052 ps
CPU time 0.77 seconds
Started Mar 31 12:39:12 PM PDT 24
Finished Mar 31 12:39:13 PM PDT 24
Peak memory 196164 kb
Host smart-58813caf-9b20-40f1-a0a1-1be0b188ce1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423190926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.3423190926
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.672878411
Short name T389
Test name
Test status
Simulation time 40704134 ps
CPU time 1.65 seconds
Started Mar 31 12:39:07 PM PDT 24
Finished Mar 31 12:39:09 PM PDT 24
Peak memory 196760 kb
Host smart-a45853f5-689d-4b72-ab70-373451e91203
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672878411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.gpio_intr_with_filter_rand_intr_event.672878411
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.40322586
Short name T605
Test name
Test status
Simulation time 76984023 ps
CPU time 2.01 seconds
Started Mar 31 12:39:11 PM PDT 24
Finished Mar 31 12:39:15 PM PDT 24
Peak memory 196152 kb
Host smart-04f91585-76c5-4cd9-aeea-a605da28ca50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40322586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger.40322586
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.2495114174
Short name T655
Test name
Test status
Simulation time 18141364 ps
CPU time 0.77 seconds
Started Mar 31 12:39:11 PM PDT 24
Finished Mar 31 12:39:13 PM PDT 24
Peak memory 195532 kb
Host smart-06e28b79-0d41-4536-8e66-826c2120c27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495114174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.2495114174
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.4156128600
Short name T53
Test name
Test status
Simulation time 350395477 ps
CPU time 1.01 seconds
Started Mar 31 12:39:05 PM PDT 24
Finished Mar 31 12:39:06 PM PDT 24
Peak memory 195972 kb
Host smart-48321de5-00fa-416e-8b37-1976881efe8c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156128600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.4156128600
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.2450140323
Short name T331
Test name
Test status
Simulation time 724895552 ps
CPU time 5.02 seconds
Started Mar 31 12:39:06 PM PDT 24
Finished Mar 31 12:39:11 PM PDT 24
Peak memory 197960 kb
Host smart-65326253-9407-41eb-8986-13762083c23c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450140323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.2450140323
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.474310759
Short name T567
Test name
Test status
Simulation time 107903139 ps
CPU time 1.03 seconds
Started Mar 31 12:38:47 PM PDT 24
Finished Mar 31 12:38:49 PM PDT 24
Peak memory 195712 kb
Host smart-c6d915f5-a59f-4da2-be42-645a4c5797d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474310759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.474310759
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2643733914
Short name T233
Test name
Test status
Simulation time 206300777 ps
CPU time 1.09 seconds
Started Mar 31 12:38:59 PM PDT 24
Finished Mar 31 12:39:00 PM PDT 24
Peak memory 195760 kb
Host smart-0e247996-f776-4427-b3da-ed269eca93d8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643733914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2643733914
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.1537373340
Short name T631
Test name
Test status
Simulation time 19049116069 ps
CPU time 121.26 seconds
Started Mar 31 12:38:47 PM PDT 24
Finished Mar 31 12:40:49 PM PDT 24
Peak memory 198052 kb
Host smart-d2a153c2-cb99-4476-a282-407a56bfa583
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537373340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.1537373340
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.763762864
Short name T437
Test name
Test status
Simulation time 179187312 ps
CPU time 0.6 seconds
Started Mar 31 12:38:48 PM PDT 24
Finished Mar 31 12:38:48 PM PDT 24
Peak memory 193916 kb
Host smart-c273904a-184d-4b50-9e5f-c36c8a94ab81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763762864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.763762864
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.3518441808
Short name T414
Test name
Test status
Simulation time 41708143 ps
CPU time 0.97 seconds
Started Mar 31 12:39:00 PM PDT 24
Finished Mar 31 12:39:01 PM PDT 24
Peak memory 196660 kb
Host smart-ab2f49e3-7aa8-42a9-b918-f5b9310c6bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518441808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.3518441808
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.1344257569
Short name T127
Test name
Test status
Simulation time 377196797 ps
CPU time 20.29 seconds
Started Mar 31 12:39:00 PM PDT 24
Finished Mar 31 12:39:20 PM PDT 24
Peak memory 198004 kb
Host smart-dd885555-644b-4ed1-9f12-eab3094874d8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344257569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.1344257569
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3706136516
Short name T222
Test name
Test status
Simulation time 27896161 ps
CPU time 0.64 seconds
Started Mar 31 12:39:04 PM PDT 24
Finished Mar 31 12:39:05 PM PDT 24
Peak memory 194340 kb
Host smart-bd1867d2-95b0-4e15-8099-6f3d8d412926
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706136516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3706136516
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.1434572699
Short name T115
Test name
Test status
Simulation time 382599049 ps
CPU time 1.48 seconds
Started Mar 31 12:38:51 PM PDT 24
Finished Mar 31 12:38:52 PM PDT 24
Peak memory 197944 kb
Host smart-118b62cd-b8fc-4957-a746-e7bceb987d64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434572699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.1434572699
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.2228541905
Short name T329
Test name
Test status
Simulation time 256253200 ps
CPU time 2.71 seconds
Started Mar 31 12:38:49 PM PDT 24
Finished Mar 31 12:38:52 PM PDT 24
Peak memory 197984 kb
Host smart-06287396-9c65-486c-9b63-168d19780b69
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228541905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.2228541905
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.2723859702
Short name T135
Test name
Test status
Simulation time 273320689 ps
CPU time 1.66 seconds
Started Mar 31 12:39:00 PM PDT 24
Finished Mar 31 12:39:02 PM PDT 24
Peak memory 196160 kb
Host smart-235048a7-4a33-438f-9ba8-7d130bd971e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723859702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.2723859702
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.1008005616
Short name T496
Test name
Test status
Simulation time 904961620 ps
CPU time 1.16 seconds
Started Mar 31 12:39:03 PM PDT 24
Finished Mar 31 12:39:05 PM PDT 24
Peak memory 196960 kb
Host smart-6131f47d-145f-4bb9-ad5a-1b5d9bdfa426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008005616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.1008005616
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.2680427934
Short name T309
Test name
Test status
Simulation time 25454089 ps
CPU time 0.97 seconds
Started Mar 31 12:38:49 PM PDT 24
Finished Mar 31 12:38:50 PM PDT 24
Peak memory 195992 kb
Host smart-2d23382e-935a-426f-a448-11b3b9c51be7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680427934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.2680427934
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.2422831863
Short name T582
Test name
Test status
Simulation time 198571331 ps
CPU time 1.47 seconds
Started Mar 31 12:38:48 PM PDT 24
Finished Mar 31 12:38:49 PM PDT 24
Peak memory 198000 kb
Host smart-91828ad4-ea84-405e-a474-473826fc7e62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422831863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.2422831863
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.101873073
Short name T522
Test name
Test status
Simulation time 308981209 ps
CPU time 1.13 seconds
Started Mar 31 12:39:12 PM PDT 24
Finished Mar 31 12:39:14 PM PDT 24
Peak memory 195664 kb
Host smart-be8fa912-1633-46f9-a90b-3967af4b4680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101873073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.101873073
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.1414488777
Short name T232
Test name
Test status
Simulation time 418795040 ps
CPU time 1.11 seconds
Started Mar 31 12:38:47 PM PDT 24
Finished Mar 31 12:38:49 PM PDT 24
Peak memory 195452 kb
Host smart-861f6c4f-ae12-44f2-89b9-87d1b1a92f74
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414488777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.1414488777
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.3472752243
Short name T297
Test name
Test status
Simulation time 2348251573 ps
CPU time 52.19 seconds
Started Mar 31 12:39:12 PM PDT 24
Finished Mar 31 12:40:05 PM PDT 24
Peak memory 198204 kb
Host smart-5434da38-fd91-46f0-834c-093389885a90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472752243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.3472752243
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.89507497
Short name T561
Test name
Test status
Simulation time 377352559508 ps
CPU time 1305.52 seconds
Started Mar 31 12:39:04 PM PDT 24
Finished Mar 31 01:00:50 PM PDT 24
Peak memory 198060 kb
Host smart-c3995e92-c538-4d1f-9bdf-a381f1951cd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=89507497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.89507497
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.4151816264
Short name T294
Test name
Test status
Simulation time 32450430 ps
CPU time 0.56 seconds
Started Mar 31 12:39:17 PM PDT 24
Finished Mar 31 12:39:18 PM PDT 24
Peak memory 194104 kb
Host smart-c45fcc49-7bd2-400c-97bf-4b19bf600244
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151816264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.4151816264
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3084276587
Short name T132
Test name
Test status
Simulation time 42820097 ps
CPU time 0.71 seconds
Started Mar 31 12:38:49 PM PDT 24
Finished Mar 31 12:38:50 PM PDT 24
Peak memory 194804 kb
Host smart-415579c5-9cfa-44db-9cc1-7bd445d2be42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084276587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.3084276587
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.1522190460
Short name T589
Test name
Test status
Simulation time 382705486 ps
CPU time 12.62 seconds
Started Mar 31 12:39:05 PM PDT 24
Finished Mar 31 12:39:17 PM PDT 24
Peak memory 198008 kb
Host smart-c5cc5abe-f9be-42c7-af92-3c98899ad746
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522190460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.1522190460
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.2155908158
Short name T119
Test name
Test status
Simulation time 84409717 ps
CPU time 0.76 seconds
Started Mar 31 12:38:59 PM PDT 24
Finished Mar 31 12:39:00 PM PDT 24
Peak memory 195808 kb
Host smart-2bd8c314-48b7-46f6-882e-d5c8613137e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155908158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.2155908158
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.1904416769
Short name T433
Test name
Test status
Simulation time 114715953 ps
CPU time 0.84 seconds
Started Mar 31 12:38:56 PM PDT 24
Finished Mar 31 12:38:57 PM PDT 24
Peak memory 195420 kb
Host smart-2ab50050-0b58-46b7-9d37-abdaf8b37b8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904416769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1904416769
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.4270681900
Short name T288
Test name
Test status
Simulation time 27384703 ps
CPU time 1.18 seconds
Started Mar 31 12:38:49 PM PDT 24
Finished Mar 31 12:38:50 PM PDT 24
Peak memory 197632 kb
Host smart-8a5c9516-c710-46b3-bb35-5cf3d1b29f42
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270681900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.4270681900
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.3026207096
Short name T552
Test name
Test status
Simulation time 200251738 ps
CPU time 1.27 seconds
Started Mar 31 12:38:51 PM PDT 24
Finished Mar 31 12:38:52 PM PDT 24
Peak memory 196148 kb
Host smart-603a1f5a-a84d-4e3a-bc6c-d89980472234
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026207096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.3026207096
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.4225544807
Short name T271
Test name
Test status
Simulation time 37756615 ps
CPU time 1.28 seconds
Started Mar 31 12:38:55 PM PDT 24
Finished Mar 31 12:38:56 PM PDT 24
Peak memory 196968 kb
Host smart-47ce8ee6-9297-4d50-83eb-be23b80a33d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225544807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.4225544807
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.1724730421
Short name T25
Test name
Test status
Simulation time 127818115 ps
CPU time 0.77 seconds
Started Mar 31 12:39:02 PM PDT 24
Finished Mar 31 12:39:03 PM PDT 24
Peak memory 195560 kb
Host smart-3fbb4e94-f792-4ad9-a478-b4f7810e58d3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724730421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.1724730421
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.2175338768
Short name T492
Test name
Test status
Simulation time 386534675 ps
CPU time 5.98 seconds
Started Mar 31 12:38:49 PM PDT 24
Finished Mar 31 12:38:55 PM PDT 24
Peak memory 197920 kb
Host smart-4ddf5d2e-187d-420e-9170-db2f5dc93940
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175338768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.2175338768
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.2931309446
Short name T546
Test name
Test status
Simulation time 192908628 ps
CPU time 1.16 seconds
Started Mar 31 12:39:06 PM PDT 24
Finished Mar 31 12:39:08 PM PDT 24
Peak memory 195712 kb
Host smart-d1ea3dfe-d1a8-4a2b-beed-ea7181f4033d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931309446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.2931309446
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.2780756865
Short name T560
Test name
Test status
Simulation time 231373491 ps
CPU time 1.19 seconds
Started Mar 31 12:39:07 PM PDT 24
Finished Mar 31 12:39:08 PM PDT 24
Peak memory 195788 kb
Host smart-6f135444-d2ab-4b6c-b8ca-bc126c9da876
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780756865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.2780756865
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.1380413915
Short name T698
Test name
Test status
Simulation time 15366042735 ps
CPU time 113.06 seconds
Started Mar 31 12:39:04 PM PDT 24
Finished Mar 31 12:40:57 PM PDT 24
Peak memory 198164 kb
Host smart-e9d0b942-98f0-4118-80c2-4b2588c35581
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380413915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.1380413915
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.1600115107
Short name T425
Test name
Test status
Simulation time 39012142 ps
CPU time 0.53 seconds
Started Mar 31 12:39:16 PM PDT 24
Finished Mar 31 12:39:17 PM PDT 24
Peak memory 193812 kb
Host smart-5c8144ef-b631-424b-8aa1-9106e86b00cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600115107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.1600115107
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.2640716707
Short name T343
Test name
Test status
Simulation time 96735683 ps
CPU time 0.85 seconds
Started Mar 31 12:39:16 PM PDT 24
Finished Mar 31 12:39:17 PM PDT 24
Peak memory 196492 kb
Host smart-79a79026-1a76-4316-9911-aa3ac1f685ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640716707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.2640716707
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.82710924
Short name T313
Test name
Test status
Simulation time 1600215219 ps
CPU time 14.15 seconds
Started Mar 31 12:39:11 PM PDT 24
Finished Mar 31 12:39:25 PM PDT 24
Peak memory 197872 kb
Host smart-6f6737af-fe8c-4fc5-a156-b1ab1a4107d9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82710924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stress
.82710924
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.3864562589
Short name T97
Test name
Test status
Simulation time 47727435 ps
CPU time 0.63 seconds
Started Mar 31 12:39:21 PM PDT 24
Finished Mar 31 12:39:22 PM PDT 24
Peak memory 194904 kb
Host smart-f3fc4c51-3b9a-4356-84c5-12366e56d3f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864562589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.3864562589
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.1201703358
Short name T622
Test name
Test status
Simulation time 171504265 ps
CPU time 1.47 seconds
Started Mar 31 12:39:00 PM PDT 24
Finished Mar 31 12:39:02 PM PDT 24
Peak memory 197040 kb
Host smart-fb1a4dd9-17ab-48d4-9a46-5d403ef7ae3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201703358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.1201703358
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.1209028773
Short name T476
Test name
Test status
Simulation time 152617374 ps
CPU time 1.69 seconds
Started Mar 31 12:39:09 PM PDT 24
Finished Mar 31 12:39:11 PM PDT 24
Peak memory 198000 kb
Host smart-1365978a-ab16-4c40-b78f-d3078d511cbf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209028773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.1209028773
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.1716331099
Short name T616
Test name
Test status
Simulation time 155153450 ps
CPU time 3.29 seconds
Started Mar 31 12:39:07 PM PDT 24
Finished Mar 31 12:39:11 PM PDT 24
Peak memory 196920 kb
Host smart-88b2ffdc-fe63-4198-b8e4-76c06873de45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716331099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.1716331099
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.1475195017
Short name T601
Test name
Test status
Simulation time 88696921 ps
CPU time 0.71 seconds
Started Mar 31 12:39:02 PM PDT 24
Finished Mar 31 12:39:03 PM PDT 24
Peak memory 195364 kb
Host smart-19f20965-40bd-4e1a-83bd-69f62e2bb7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475195017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.1475195017
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.1141476266
Short name T213
Test name
Test status
Simulation time 30365041 ps
CPU time 0.78 seconds
Started Mar 31 12:39:05 PM PDT 24
Finished Mar 31 12:39:06 PM PDT 24
Peak memory 195512 kb
Host smart-89781781-ad0c-4b08-978b-7b2e2fe0f24f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141476266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.1141476266
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.231270923
Short name T658
Test name
Test status
Simulation time 670373722 ps
CPU time 2.32 seconds
Started Mar 31 12:39:22 PM PDT 24
Finished Mar 31 12:39:24 PM PDT 24
Peak memory 197800 kb
Host smart-ddaf3d4d-3fd1-4488-8838-87e96103b0b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231270923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ran
dom_long_reg_writes_reg_reads.231270923
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.4162674743
Short name T156
Test name
Test status
Simulation time 60504392 ps
CPU time 1.1 seconds
Started Mar 31 12:39:04 PM PDT 24
Finished Mar 31 12:39:05 PM PDT 24
Peak memory 195652 kb
Host smart-7701c6ad-ca9b-4158-b3a5-85abc995a8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162674743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.4162674743
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.3646042037
Short name T360
Test name
Test status
Simulation time 143324846 ps
CPU time 1.28 seconds
Started Mar 31 12:39:09 PM PDT 24
Finished Mar 31 12:39:11 PM PDT 24
Peak memory 197988 kb
Host smart-beea0e13-8388-469e-9f1f-f15bd57a32f8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646042037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.3646042037
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.570016257
Short name T140
Test name
Test status
Simulation time 133628591151 ps
CPU time 110.09 seconds
Started Mar 31 12:39:15 PM PDT 24
Finished Mar 31 12:41:05 PM PDT 24
Peak memory 198200 kb
Host smart-3a89c4c2-c92e-41be-a663-cdfb6dea703a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570016257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.g
pio_stress_all.570016257
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.3712861138
Short name T542
Test name
Test status
Simulation time 45965579971 ps
CPU time 929.07 seconds
Started Mar 31 12:39:16 PM PDT 24
Finished Mar 31 12:54:46 PM PDT 24
Peak memory 198252 kb
Host smart-52e8ee05-0f40-41a5-844b-7f67d3642f6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3712861138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.3712861138
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.1936472976
Short name T126
Test name
Test status
Simulation time 12064053 ps
CPU time 0.55 seconds
Started Mar 31 12:39:01 PM PDT 24
Finished Mar 31 12:39:02 PM PDT 24
Peak memory 193788 kb
Host smart-f8cb0a88-4ce4-4284-a4db-2cb3f5ff47fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936472976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.1936472976
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.3432717075
Short name T422
Test name
Test status
Simulation time 47256904 ps
CPU time 0.96 seconds
Started Mar 31 12:39:15 PM PDT 24
Finished Mar 31 12:39:17 PM PDT 24
Peak memory 196412 kb
Host smart-15ca2d4c-1929-40ed-a668-94b3036bc313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432717075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.3432717075
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.1570593850
Short name T27
Test name
Test status
Simulation time 115693137 ps
CPU time 3.08 seconds
Started Mar 31 12:39:24 PM PDT 24
Finished Mar 31 12:39:27 PM PDT 24
Peak memory 195764 kb
Host smart-5fa3df18-331f-4ef7-8ee1-65d4f57b018a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570593850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.1570593850
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.1482072288
Short name T334
Test name
Test status
Simulation time 248945015 ps
CPU time 0.92 seconds
Started Mar 31 12:39:08 PM PDT 24
Finished Mar 31 12:39:09 PM PDT 24
Peak memory 196164 kb
Host smart-c14633bd-0e21-4f84-8155-531c07813e0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482072288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.1482072288
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.2006041849
Short name T457
Test name
Test status
Simulation time 52849209 ps
CPU time 1.08 seconds
Started Mar 31 12:39:11 PM PDT 24
Finished Mar 31 12:39:13 PM PDT 24
Peak memory 195936 kb
Host smart-42648936-aa25-48be-865f-ecbd2db12a92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006041849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.2006041849
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.1477237967
Short name T234
Test name
Test status
Simulation time 285833159 ps
CPU time 2.89 seconds
Started Mar 31 12:39:03 PM PDT 24
Finished Mar 31 12:39:06 PM PDT 24
Peak memory 198112 kb
Host smart-ffc0a5ca-6e84-48f0-bbd4-1650a48e3981
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477237967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.1477237967
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.2651029481
Short name T184
Test name
Test status
Simulation time 265091214 ps
CPU time 1.88 seconds
Started Mar 31 12:39:12 PM PDT 24
Finished Mar 31 12:39:16 PM PDT 24
Peak memory 196656 kb
Host smart-54d2efa1-a692-425b-a209-6df5beb92291
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651029481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.2651029481
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.2739159200
Short name T349
Test name
Test status
Simulation time 56394545 ps
CPU time 1.04 seconds
Started Mar 31 12:39:16 PM PDT 24
Finished Mar 31 12:39:17 PM PDT 24
Peak memory 195948 kb
Host smart-edd038d0-6051-4126-a113-be0e8b170372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739159200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.2739159200
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.2952083912
Short name T442
Test name
Test status
Simulation time 31329311 ps
CPU time 1.06 seconds
Started Mar 31 12:38:59 PM PDT 24
Finished Mar 31 12:39:00 PM PDT 24
Peak memory 195916 kb
Host smart-ecda9df7-76b3-4412-a00f-8e0ffa62ecd0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952083912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.2952083912
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.2849853577
Short name T441
Test name
Test status
Simulation time 220196926 ps
CPU time 3.33 seconds
Started Mar 31 12:39:14 PM PDT 24
Finished Mar 31 12:39:18 PM PDT 24
Peak memory 197912 kb
Host smart-d56662e4-0a86-40ac-b407-bd1a1aaec3c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849853577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.2849853577
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.3065216855
Short name T527
Test name
Test status
Simulation time 57281286 ps
CPU time 1.52 seconds
Started Mar 31 12:39:06 PM PDT 24
Finished Mar 31 12:39:08 PM PDT 24
Peak memory 196724 kb
Host smart-1faaf443-5286-4935-90c3-fbf637a5165f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065216855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.3065216855
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.808864653
Short name T403
Test name
Test status
Simulation time 32862488 ps
CPU time 0.78 seconds
Started Mar 31 12:39:12 PM PDT 24
Finished Mar 31 12:39:14 PM PDT 24
Peak memory 195236 kb
Host smart-af2987f0-9ac9-4128-9268-3f7d0c9875a6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808864653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.808864653
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.1613883205
Short name T379
Test name
Test status
Simulation time 11250860874 ps
CPU time 59.82 seconds
Started Mar 31 12:39:02 PM PDT 24
Finished Mar 31 12:40:02 PM PDT 24
Peak memory 198120 kb
Host smart-34612bde-2226-43e3-ae58-47f840483251
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613883205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.1613883205
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.651701985
Short name T179
Test name
Test status
Simulation time 15837445 ps
CPU time 0.59 seconds
Started Mar 31 12:39:10 PM PDT 24
Finished Mar 31 12:39:11 PM PDT 24
Peak memory 193884 kb
Host smart-2d32ae15-897c-4b2c-874f-5c901f4bc1fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651701985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.651701985
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.2205107660
Short name T377
Test name
Test status
Simulation time 157419814 ps
CPU time 0.95 seconds
Started Mar 31 12:39:15 PM PDT 24
Finished Mar 31 12:39:16 PM PDT 24
Peak memory 196528 kb
Host smart-e6bc303b-6e03-4acd-ab8c-4468a72e4457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205107660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.2205107660
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.1493183256
Short name T597
Test name
Test status
Simulation time 980520397 ps
CPU time 28.4 seconds
Started Mar 31 12:39:22 PM PDT 24
Finished Mar 31 12:39:50 PM PDT 24
Peak memory 196980 kb
Host smart-a23df5f2-c697-4ec0-b605-45b0d0546cce
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493183256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.1493183256
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.2500358102
Short name T385
Test name
Test status
Simulation time 141240101 ps
CPU time 0.66 seconds
Started Mar 31 12:39:04 PM PDT 24
Finished Mar 31 12:39:05 PM PDT 24
Peak memory 195188 kb
Host smart-8d70e485-a713-49b0-9464-f4af50fd77cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500358102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.2500358102
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.1413451703
Short name T264
Test name
Test status
Simulation time 204774003 ps
CPU time 1.45 seconds
Started Mar 31 12:38:57 PM PDT 24
Finished Mar 31 12:38:59 PM PDT 24
Peak memory 197060 kb
Host smart-f4ebe85b-9f7a-4cee-866d-e138ff64928b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413451703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.1413451703
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.3563782244
Short name T563
Test name
Test status
Simulation time 166527642 ps
CPU time 1.79 seconds
Started Mar 31 12:39:02 PM PDT 24
Finished Mar 31 12:39:04 PM PDT 24
Peak memory 198100 kb
Host smart-f032392e-60a7-42fb-af56-5f15765b6134
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563782244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.3563782244
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.3942507187
Short name T320
Test name
Test status
Simulation time 155725630 ps
CPU time 3.16 seconds
Started Mar 31 12:39:00 PM PDT 24
Finished Mar 31 12:39:03 PM PDT 24
Peak memory 196740 kb
Host smart-e05962f6-b219-4e06-a1f4-19f6e09cae54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942507187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.3942507187
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.703776526
Short name T149
Test name
Test status
Simulation time 253045773 ps
CPU time 1.15 seconds
Started Mar 31 12:39:08 PM PDT 24
Finished Mar 31 12:39:10 PM PDT 24
Peak memory 195932 kb
Host smart-77fc28ef-4491-4791-952d-bdc922623bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703776526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.703776526
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.3528448063
Short name T544
Test name
Test status
Simulation time 180076030 ps
CPU time 0.97 seconds
Started Mar 31 12:39:15 PM PDT 24
Finished Mar 31 12:39:17 PM PDT 24
Peak memory 195976 kb
Host smart-8b3faa71-8807-44e5-bb54-fc3cdf4b301c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528448063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.3528448063
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.4089206165
Short name T674
Test name
Test status
Simulation time 642565922 ps
CPU time 1.79 seconds
Started Mar 31 12:39:01 PM PDT 24
Finished Mar 31 12:39:04 PM PDT 24
Peak memory 198052 kb
Host smart-54d02c91-8d76-45db-8ea7-24588c1ed4d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089206165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.4089206165
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.252795270
Short name T581
Test name
Test status
Simulation time 66533533 ps
CPU time 1.13 seconds
Started Mar 31 12:39:06 PM PDT 24
Finished Mar 31 12:39:07 PM PDT 24
Peak memory 195684 kb
Host smart-e9f13493-265d-4460-b4a5-c005fcdacd06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252795270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.252795270
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.280584956
Short name T325
Test name
Test status
Simulation time 139706194 ps
CPU time 0.85 seconds
Started Mar 31 12:39:18 PM PDT 24
Finished Mar 31 12:39:19 PM PDT 24
Peak memory 196460 kb
Host smart-d6aa4f12-92bb-4ddc-a692-712bbf064c8e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280584956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.280584956
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.4136606705
Short name T705
Test name
Test status
Simulation time 13394392769 ps
CPU time 82.27 seconds
Started Mar 31 12:38:59 PM PDT 24
Finished Mar 31 12:40:22 PM PDT 24
Peak memory 198100 kb
Host smart-810e12c1-41a3-443a-99bb-4a02d0d4d90a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136606705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.4136606705
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.687157709
Short name T557
Test name
Test status
Simulation time 33275428522 ps
CPU time 373.02 seconds
Started Mar 31 12:39:09 PM PDT 24
Finished Mar 31 12:45:22 PM PDT 24
Peak memory 198240 kb
Host smart-80bcdf8c-603b-4a5a-93c7-97f8997eb31b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=687157709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.687157709
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.2743432399
Short name T599
Test name
Test status
Simulation time 41471809 ps
CPU time 0.56 seconds
Started Mar 31 12:38:13 PM PDT 24
Finished Mar 31 12:38:14 PM PDT 24
Peak memory 193956 kb
Host smart-96bf876f-7131-4760-9d48-4888c6886662
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743432399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.2743432399
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.249008670
Short name T316
Test name
Test status
Simulation time 67063467 ps
CPU time 0.81 seconds
Started Mar 31 12:38:02 PM PDT 24
Finished Mar 31 12:38:03 PM PDT 24
Peak memory 195232 kb
Host smart-fa8dc94e-5a6c-4921-ab8c-51a90c629e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249008670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.249008670
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.3080153657
Short name T164
Test name
Test status
Simulation time 6193596625 ps
CPU time 13.06 seconds
Started Mar 31 12:37:47 PM PDT 24
Finished Mar 31 12:38:01 PM PDT 24
Peak memory 196936 kb
Host smart-86a0e746-492f-457d-88ea-2c89a03ed22b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080153657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.3080153657
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.4251842561
Short name T311
Test name
Test status
Simulation time 37950853 ps
CPU time 0.72 seconds
Started Mar 31 12:38:00 PM PDT 24
Finished Mar 31 12:38:01 PM PDT 24
Peak memory 195552 kb
Host smart-a988038b-20a7-4370-9219-cbf16797493c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251842561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.4251842561
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.3093739153
Short name T123
Test name
Test status
Simulation time 289469536 ps
CPU time 1.25 seconds
Started Mar 31 12:37:51 PM PDT 24
Finished Mar 31 12:37:54 PM PDT 24
Peak memory 197996 kb
Host smart-85dbe561-c6c1-493c-8d04-ae2890a4cfe6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093739153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.3093739153
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.3787621913
Short name T108
Test name
Test status
Simulation time 225958987 ps
CPU time 2.78 seconds
Started Mar 31 12:38:02 PM PDT 24
Finished Mar 31 12:38:05 PM PDT 24
Peak memory 198084 kb
Host smart-a1796dba-3dc8-4837-ad10-527954b28b2d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787621913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.3787621913
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.600831291
Short name T244
Test name
Test status
Simulation time 461996331 ps
CPU time 2.48 seconds
Started Mar 31 12:37:53 PM PDT 24
Finished Mar 31 12:37:56 PM PDT 24
Peak memory 196856 kb
Host smart-0c6307d4-fbad-4f4b-99f0-63e1089cbba6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600831291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.600831291
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.2875570659
Short name T593
Test name
Test status
Simulation time 34396443 ps
CPU time 1.22 seconds
Started Mar 31 12:37:58 PM PDT 24
Finished Mar 31 12:37:59 PM PDT 24
Peak memory 198040 kb
Host smart-fbe722b7-a647-47a8-bba5-5c1c076f8bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875570659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.2875570659
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2164253909
Short name T361
Test name
Test status
Simulation time 341838213 ps
CPU time 1.12 seconds
Started Mar 31 12:37:41 PM PDT 24
Finished Mar 31 12:37:43 PM PDT 24
Peak memory 196668 kb
Host smart-6af89306-bd29-43d1-b55e-f36676f27c73
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164253909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.2164253909
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.1712588188
Short name T672
Test name
Test status
Simulation time 356844413 ps
CPU time 3.24 seconds
Started Mar 31 12:37:49 PM PDT 24
Finished Mar 31 12:37:54 PM PDT 24
Peak memory 197916 kb
Host smart-3f4bf3b5-b5d4-4b95-b9df-fc6c61c2d68f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712588188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.1712588188
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_smoke.876212620
Short name T272
Test name
Test status
Simulation time 142236900 ps
CPU time 1.02 seconds
Started Mar 31 12:37:48 PM PDT 24
Finished Mar 31 12:37:50 PM PDT 24
Peak memory 196268 kb
Host smart-e8dd0dfd-a923-467c-b022-a941625333cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876212620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.876212620
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.1410356592
Short name T181
Test name
Test status
Simulation time 142546413 ps
CPU time 0.93 seconds
Started Mar 31 12:37:45 PM PDT 24
Finished Mar 31 12:37:46 PM PDT 24
Peak memory 195780 kb
Host smart-87d89d4e-8f22-4a8d-9c2e-38cf14c0acf2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410356592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.1410356592
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.1930204688
Short name T384
Test name
Test status
Simulation time 1306497730 ps
CPU time 32.94 seconds
Started Mar 31 12:37:52 PM PDT 24
Finished Mar 31 12:38:27 PM PDT 24
Peak memory 198084 kb
Host smart-d14b4a00-6c64-448a-9c35-4c166f2f888d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930204688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.1930204688
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.3749705583
Short name T65
Test name
Test status
Simulation time 282525718094 ps
CPU time 958.84 seconds
Started Mar 31 12:37:56 PM PDT 24
Finished Mar 31 12:53:55 PM PDT 24
Peak memory 198268 kb
Host smart-2e43a6a3-ca39-4cb3-b4de-c6b6e1aea9df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3749705583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.3749705583
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.3588018443
Short name T11
Test name
Test status
Simulation time 18476090 ps
CPU time 0.55 seconds
Started Mar 31 12:39:10 PM PDT 24
Finished Mar 31 12:39:11 PM PDT 24
Peak memory 193760 kb
Host smart-7d89a6d2-4095-4192-9a8c-442d00aa2a8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588018443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.3588018443
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.1603439587
Short name T129
Test name
Test status
Simulation time 28631093 ps
CPU time 0.63 seconds
Started Mar 31 12:39:10 PM PDT 24
Finished Mar 31 12:39:11 PM PDT 24
Peak memory 194748 kb
Host smart-36e47f58-b3b8-4b66-871c-a6fcb2dfc576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603439587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.1603439587
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.1559235920
Short name T707
Test name
Test status
Simulation time 6745294993 ps
CPU time 23.68 seconds
Started Mar 31 12:39:20 PM PDT 24
Finished Mar 31 12:39:44 PM PDT 24
Peak memory 197208 kb
Host smart-5301f235-8e65-46fe-b624-a9b6172afa7a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559235920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.1559235920
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.1283639343
Short name T201
Test name
Test status
Simulation time 70802044 ps
CPU time 1.12 seconds
Started Mar 31 12:39:07 PM PDT 24
Finished Mar 31 12:39:08 PM PDT 24
Peak memory 197836 kb
Host smart-02731c09-569b-49c1-8b62-c79915c11730
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283639343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.1283639343
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.2519892025
Short name T706
Test name
Test status
Simulation time 126822763 ps
CPU time 1.09 seconds
Started Mar 31 12:39:03 PM PDT 24
Finished Mar 31 12:39:04 PM PDT 24
Peak memory 195988 kb
Host smart-e6d70214-bd5d-4957-8d98-95456504e2d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519892025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.2519892025
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.1210295500
Short name T18
Test name
Test status
Simulation time 134579834 ps
CPU time 1.35 seconds
Started Mar 31 12:39:22 PM PDT 24
Finished Mar 31 12:39:29 PM PDT 24
Peak memory 197648 kb
Host smart-e4c27e2a-ef17-4101-aef7-a98223a6e052
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210295500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.1210295500
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.570118378
Short name T532
Test name
Test status
Simulation time 406961937 ps
CPU time 2.15 seconds
Started Mar 31 12:39:00 PM PDT 24
Finished Mar 31 12:39:03 PM PDT 24
Peak memory 197172 kb
Host smart-49acfea4-43b5-4df4-bdf5-ca16f7eef3b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570118378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger.
570118378
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.1701540217
Short name T169
Test name
Test status
Simulation time 98983072 ps
CPU time 0.73 seconds
Started Mar 31 12:39:16 PM PDT 24
Finished Mar 31 12:39:17 PM PDT 24
Peak memory 195484 kb
Host smart-8e0c6780-908b-4716-bacb-5292fd86d5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701540217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.1701540217
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.1516147675
Short name T614
Test name
Test status
Simulation time 148336385 ps
CPU time 1.31 seconds
Started Mar 31 12:39:13 PM PDT 24
Finished Mar 31 12:39:15 PM PDT 24
Peak memory 197036 kb
Host smart-a268e716-38a4-47ed-b6fd-fe7aa5323d93
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516147675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.1516147675
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2589932358
Short name T574
Test name
Test status
Simulation time 271836216 ps
CPU time 3.27 seconds
Started Mar 31 12:39:03 PM PDT 24
Finished Mar 31 12:39:06 PM PDT 24
Peak memory 197980 kb
Host smart-1763c954-80e3-42eb-bf6f-d5d40321d969
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589932358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.2589932358
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.2616372968
Short name T23
Test name
Test status
Simulation time 535925536 ps
CPU time 1.15 seconds
Started Mar 31 12:39:10 PM PDT 24
Finished Mar 31 12:39:11 PM PDT 24
Peak memory 196608 kb
Host smart-76472bbc-0495-45ec-8eba-efc52349251c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616372968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.2616372968
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.3634354406
Short name T500
Test name
Test status
Simulation time 70115320 ps
CPU time 0.83 seconds
Started Mar 31 12:39:24 PM PDT 24
Finished Mar 31 12:39:25 PM PDT 24
Peak memory 195956 kb
Host smart-0510921e-f072-4b38-8ca1-dcab0c841515
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634354406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.3634354406
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.3088483969
Short name T16
Test name
Test status
Simulation time 6070876527 ps
CPU time 148.19 seconds
Started Mar 31 12:39:04 PM PDT 24
Finished Mar 31 12:41:32 PM PDT 24
Peak memory 198164 kb
Host smart-c53c051b-1cd4-45e8-aa39-1b066ec2aa3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088483969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.3088483969
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.1045692654
Short name T248
Test name
Test status
Simulation time 14421682 ps
CPU time 0.57 seconds
Started Mar 31 12:39:11 PM PDT 24
Finished Mar 31 12:39:11 PM PDT 24
Peak memory 194636 kb
Host smart-e6b9c575-c899-4388-a6e1-0e6ce9047a72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045692654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.1045692654
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.4268178359
Short name T397
Test name
Test status
Simulation time 169830166 ps
CPU time 0.64 seconds
Started Mar 31 12:39:16 PM PDT 24
Finished Mar 31 12:39:17 PM PDT 24
Peak memory 194052 kb
Host smart-16756ebe-1f1c-40aa-a4dc-b2c4534a9f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268178359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.4268178359
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.3436555483
Short name T434
Test name
Test status
Simulation time 1058380760 ps
CPU time 10.01 seconds
Started Mar 31 12:39:07 PM PDT 24
Finished Mar 31 12:39:17 PM PDT 24
Peak memory 197924 kb
Host smart-210f05c6-929e-4b1f-8854-ec8b259be242
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436555483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.3436555483
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.1508358988
Short name T197
Test name
Test status
Simulation time 29118505 ps
CPU time 0.7 seconds
Started Mar 31 12:39:15 PM PDT 24
Finished Mar 31 12:39:16 PM PDT 24
Peak memory 195716 kb
Host smart-a5eb47ed-b6aa-40a3-9c61-59aef6c1c248
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508358988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.1508358988
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.2393066776
Short name T221
Test name
Test status
Simulation time 18314228 ps
CPU time 0.75 seconds
Started Mar 31 12:39:15 PM PDT 24
Finished Mar 31 12:39:16 PM PDT 24
Peak memory 195216 kb
Host smart-a16e966e-0c19-4bd9-99b3-dc1370cda525
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393066776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.2393066776
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.918753942
Short name T218
Test name
Test status
Simulation time 157079697 ps
CPU time 2.65 seconds
Started Mar 31 12:39:10 PM PDT 24
Finished Mar 31 12:39:13 PM PDT 24
Peak memory 197992 kb
Host smart-5ca9ef43-5dd7-4037-9f68-30fe9b353f7a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918753942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.gpio_intr_with_filter_rand_intr_event.918753942
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.220780579
Short name T237
Test name
Test status
Simulation time 144972762 ps
CPU time 1.82 seconds
Started Mar 31 12:39:08 PM PDT 24
Finished Mar 31 12:39:10 PM PDT 24
Peak memory 196152 kb
Host smart-beb32694-c560-4be9-8855-af1cbe7db7a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220780579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger.
220780579
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.4071941442
Short name T268
Test name
Test status
Simulation time 40580506 ps
CPU time 0.9 seconds
Started Mar 31 12:39:15 PM PDT 24
Finished Mar 31 12:39:17 PM PDT 24
Peak memory 196032 kb
Host smart-76707087-aff5-468d-8098-af1b81b732a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071941442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.4071941442
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.198910808
Short name T702
Test name
Test status
Simulation time 23326908 ps
CPU time 0.81 seconds
Started Mar 31 12:39:19 PM PDT 24
Finished Mar 31 12:39:20 PM PDT 24
Peak memory 197308 kb
Host smart-d371078d-6b79-4f7f-b967-82ce19b94ddf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198910808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullup
_pulldown.198910808
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.75041981
Short name T365
Test name
Test status
Simulation time 1228183763 ps
CPU time 4.06 seconds
Started Mar 31 12:39:14 PM PDT 24
Finished Mar 31 12:39:19 PM PDT 24
Peak memory 197992 kb
Host smart-a9fa71e7-70aa-4d4e-95c1-09d743f4023c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75041981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand
om_long_reg_writes_reg_reads.75041981
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.3357545773
Short name T350
Test name
Test status
Simulation time 144856348 ps
CPU time 1.07 seconds
Started Mar 31 12:39:22 PM PDT 24
Finished Mar 31 12:39:23 PM PDT 24
Peak memory 195472 kb
Host smart-a5469d73-1326-4eb0-8438-44982e642b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357545773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.3357545773
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.916832293
Short name T487
Test name
Test status
Simulation time 80506464 ps
CPU time 1.29 seconds
Started Mar 31 12:39:22 PM PDT 24
Finished Mar 31 12:39:23 PM PDT 24
Peak memory 196576 kb
Host smart-81f75f52-448b-41b9-b65f-d4cc62c82ba5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916832293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.916832293
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.1836002813
Short name T553
Test name
Test status
Simulation time 7131633953 ps
CPU time 195.95 seconds
Started Mar 31 12:39:08 PM PDT 24
Finished Mar 31 12:42:24 PM PDT 24
Peak memory 198164 kb
Host smart-d93ec29c-88cf-4269-8c16-59224faa56b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836002813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.1836002813
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.1811136953
Short name T412
Test name
Test status
Simulation time 11727191 ps
CPU time 0.59 seconds
Started Mar 31 12:39:03 PM PDT 24
Finished Mar 31 12:39:04 PM PDT 24
Peak memory 194548 kb
Host smart-a9689731-c8d8-44e2-b538-29998b31d32b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811136953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.1811136953
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.1110184567
Short name T263
Test name
Test status
Simulation time 49364916 ps
CPU time 0.66 seconds
Started Mar 31 12:39:11 PM PDT 24
Finished Mar 31 12:39:12 PM PDT 24
Peak memory 193996 kb
Host smart-6f296d41-e79a-476c-811e-3f091e4beeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110184567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.1110184567
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.434504992
Short name T511
Test name
Test status
Simulation time 795831888 ps
CPU time 25.05 seconds
Started Mar 31 12:39:10 PM PDT 24
Finished Mar 31 12:39:35 PM PDT 24
Peak memory 196280 kb
Host smart-5ff5b96d-a3d5-4586-95f5-6fd654f66d07
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434504992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stres
s.434504992
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.1481616721
Short name T676
Test name
Test status
Simulation time 80648918 ps
CPU time 0.64 seconds
Started Mar 31 12:39:20 PM PDT 24
Finished Mar 31 12:39:21 PM PDT 24
Peak memory 195080 kb
Host smart-9a189a4f-cc3d-441d-ae77-30e5ba75da3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481616721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.1481616721
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.405753546
Short name T675
Test name
Test status
Simulation time 166143258 ps
CPU time 1.28 seconds
Started Mar 31 12:39:16 PM PDT 24
Finished Mar 31 12:39:18 PM PDT 24
Peak memory 196464 kb
Host smart-44f7cb19-7208-475e-8f45-2191d87e2f7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405753546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.405753546
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.1411184823
Short name T420
Test name
Test status
Simulation time 169373240 ps
CPU time 3.34 seconds
Started Mar 31 12:39:16 PM PDT 24
Finished Mar 31 12:39:19 PM PDT 24
Peak memory 198072 kb
Host smart-e0fe2822-bcea-4ab1-8403-44782c877ec8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411184823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.1411184823
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.2680202728
Short name T554
Test name
Test status
Simulation time 238454439 ps
CPU time 1.1 seconds
Started Mar 31 12:39:11 PM PDT 24
Finished Mar 31 12:39:12 PM PDT 24
Peak memory 195664 kb
Host smart-697e30cb-af5f-459a-a657-065149547c30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680202728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.2680202728
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.3754872522
Short name T619
Test name
Test status
Simulation time 75202670 ps
CPU time 0.95 seconds
Started Mar 31 12:39:12 PM PDT 24
Finished Mar 31 12:39:14 PM PDT 24
Peak memory 195736 kb
Host smart-f518920c-0f25-416e-a9d6-393a78d3f669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754872522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.3754872522
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.3983616021
Short name T249
Test name
Test status
Simulation time 212151823 ps
CPU time 0.78 seconds
Started Mar 31 12:39:08 PM PDT 24
Finished Mar 31 12:39:09 PM PDT 24
Peak memory 195452 kb
Host smart-925be4c7-b179-4cba-94aa-5fc27babf882
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983616021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.3983616021
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.3723745882
Short name T338
Test name
Test status
Simulation time 117762961 ps
CPU time 1.59 seconds
Started Mar 31 12:39:19 PM PDT 24
Finished Mar 31 12:39:21 PM PDT 24
Peak memory 197864 kb
Host smart-eea9296d-a1a4-4d0a-b0d7-659da50ce8de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723745882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.3723745882
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.4149987616
Short name T568
Test name
Test status
Simulation time 72189312 ps
CPU time 1.27 seconds
Started Mar 31 12:39:11 PM PDT 24
Finished Mar 31 12:39:13 PM PDT 24
Peak memory 196352 kb
Host smart-a805d41e-9420-416a-b7a5-d0bf356d7915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149987616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.4149987616
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.1768554620
Short name T383
Test name
Test status
Simulation time 19990502 ps
CPU time 0.71 seconds
Started Mar 31 12:39:08 PM PDT 24
Finished Mar 31 12:39:09 PM PDT 24
Peak memory 194220 kb
Host smart-98ce2ddf-d35c-4a9c-9a6e-ff9a88a65ae5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768554620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.1768554620
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.2651362579
Short name T2
Test name
Test status
Simulation time 16890770519 ps
CPU time 194.57 seconds
Started Mar 31 12:39:12 PM PDT 24
Finished Mar 31 12:42:28 PM PDT 24
Peak memory 198204 kb
Host smart-732af112-cd96-42a4-bdc6-dadb4c88baa6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651362579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.2651362579
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.441200416
Short name T551
Test name
Test status
Simulation time 62949860197 ps
CPU time 1291.92 seconds
Started Mar 31 12:39:08 PM PDT 24
Finished Mar 31 01:00:40 PM PDT 24
Peak memory 198116 kb
Host smart-6a33e5a1-c34e-421b-9bb9-dd46dc542ad0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=441200416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.441200416
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.4275689548
Short name T340
Test name
Test status
Simulation time 17877511 ps
CPU time 0.59 seconds
Started Mar 31 12:39:20 PM PDT 24
Finished Mar 31 12:39:21 PM PDT 24
Peak memory 194036 kb
Host smart-f51a4d45-fdeb-42ee-81f0-ab18000d3a3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275689548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.4275689548
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.3309841386
Short name T472
Test name
Test status
Simulation time 68378515 ps
CPU time 0.64 seconds
Started Mar 31 12:39:14 PM PDT 24
Finished Mar 31 12:39:15 PM PDT 24
Peak memory 194076 kb
Host smart-80d43cd6-da4f-460d-9a37-eb81586a6cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309841386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.3309841386
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.3087968433
Short name T406
Test name
Test status
Simulation time 1468631555 ps
CPU time 24.62 seconds
Started Mar 31 12:39:15 PM PDT 24
Finished Mar 31 12:39:40 PM PDT 24
Peak memory 196700 kb
Host smart-eed6d90c-d955-4221-8021-87878664e095
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087968433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.3087968433
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.3471728302
Short name T685
Test name
Test status
Simulation time 430648839 ps
CPU time 0.95 seconds
Started Mar 31 12:39:14 PM PDT 24
Finished Mar 31 12:39:16 PM PDT 24
Peak memory 197272 kb
Host smart-69a77477-aaf5-45e1-8418-e78f3a288eb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471728302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.3471728302
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.275776859
Short name T251
Test name
Test status
Simulation time 160366153 ps
CPU time 1.24 seconds
Started Mar 31 12:39:12 PM PDT 24
Finished Mar 31 12:39:13 PM PDT 24
Peak memory 196220 kb
Host smart-8ddd5f8b-8e74-4c9e-893c-e88fb40e7889
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275776859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.275776859
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.447920116
Short name T321
Test name
Test status
Simulation time 67062843 ps
CPU time 2.65 seconds
Started Mar 31 12:39:12 PM PDT 24
Finished Mar 31 12:39:16 PM PDT 24
Peak memory 196352 kb
Host smart-7a6ce7fd-6265-46fa-bfae-db3b5bc781d8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447920116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.gpio_intr_with_filter_rand_intr_event.447920116
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.1352807772
Short name T111
Test name
Test status
Simulation time 119914697 ps
CPU time 3.54 seconds
Started Mar 31 12:39:07 PM PDT 24
Finished Mar 31 12:39:11 PM PDT 24
Peak memory 196560 kb
Host smart-f3ed9818-50be-413b-9ed6-de489d17db9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352807772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.1352807772
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.608868170
Short name T591
Test name
Test status
Simulation time 205568104 ps
CPU time 1.13 seconds
Started Mar 31 12:39:12 PM PDT 24
Finished Mar 31 12:39:14 PM PDT 24
Peak memory 196864 kb
Host smart-b005e670-a9bf-4313-87f4-8c0bad366be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608868170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.608868170
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.3001982017
Short name T204
Test name
Test status
Simulation time 395149407 ps
CPU time 1.27 seconds
Started Mar 31 12:39:07 PM PDT 24
Finished Mar 31 12:39:08 PM PDT 24
Peak memory 196832 kb
Host smart-d96ef19d-9951-480b-9c92-aa1b8f9ce6f5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001982017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.3001982017
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.2861704649
Short name T484
Test name
Test status
Simulation time 508810966 ps
CPU time 5.44 seconds
Started Mar 31 12:39:10 PM PDT 24
Finished Mar 31 12:39:16 PM PDT 24
Peak memory 197936 kb
Host smart-d3d4bd49-20ed-4c6e-a3f3-2cbbcb9a5c13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861704649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.2861704649
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.2562107985
Short name T629
Test name
Test status
Simulation time 96219104 ps
CPU time 1.01 seconds
Started Mar 31 12:39:12 PM PDT 24
Finished Mar 31 12:39:13 PM PDT 24
Peak memory 195532 kb
Host smart-923b3df5-f10d-43e9-8ebf-879dfbe5c0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562107985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.2562107985
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.583400115
Short name T280
Test name
Test status
Simulation time 748838286 ps
CPU time 0.95 seconds
Started Mar 31 12:39:14 PM PDT 24
Finished Mar 31 12:39:15 PM PDT 24
Peak memory 196376 kb
Host smart-3a7d2df1-8bf5-435c-b7b8-1986f9380033
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583400115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.583400115
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.2839170391
Short name T415
Test name
Test status
Simulation time 19782150175 ps
CPU time 121.43 seconds
Started Mar 31 12:39:17 PM PDT 24
Finished Mar 31 12:41:18 PM PDT 24
Peak memory 198136 kb
Host smart-55d76253-4b04-491a-b07a-c873e63e1cf1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839170391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.2839170391
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.2942322048
Short name T42
Test name
Test status
Simulation time 49267965 ps
CPU time 0.55 seconds
Started Mar 31 12:39:11 PM PDT 24
Finished Mar 31 12:39:12 PM PDT 24
Peak memory 194580 kb
Host smart-cffb1666-19c0-4282-9db3-f6f4bf05d203
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942322048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.2942322048
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.3540325080
Short name T57
Test name
Test status
Simulation time 336001474 ps
CPU time 0.93 seconds
Started Mar 31 12:39:17 PM PDT 24
Finished Mar 31 12:39:18 PM PDT 24
Peak memory 196176 kb
Host smart-affd2c04-fed7-4a23-b67a-d0668b6ee932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540325080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.3540325080
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.1512425213
Short name T255
Test name
Test status
Simulation time 1607358283 ps
CPU time 28.12 seconds
Started Mar 31 12:39:15 PM PDT 24
Finished Mar 31 12:39:44 PM PDT 24
Peak memory 195540 kb
Host smart-a340de47-8502-4205-b9a2-77f418e98811
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512425213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.1512425213
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.122542921
Short name T678
Test name
Test status
Simulation time 212764518 ps
CPU time 0.83 seconds
Started Mar 31 12:39:15 PM PDT 24
Finished Mar 31 12:39:17 PM PDT 24
Peak memory 196104 kb
Host smart-05302787-eb11-4406-a948-73c2832c125a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122542921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.122542921
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.318347269
Short name T113
Test name
Test status
Simulation time 77877406 ps
CPU time 0.88 seconds
Started Mar 31 12:39:10 PM PDT 24
Finished Mar 31 12:39:11 PM PDT 24
Peak memory 197420 kb
Host smart-35d476a7-9bf8-4b55-92a2-7f335210af7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318347269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.318347269
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.3663314148
Short name T282
Test name
Test status
Simulation time 224407573 ps
CPU time 2.58 seconds
Started Mar 31 12:39:14 PM PDT 24
Finished Mar 31 12:39:17 PM PDT 24
Peak memory 198124 kb
Host smart-418ba3cf-d1f5-44c8-9b51-481254a14dd9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663314148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.3663314148
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.3417022182
Short name T395
Test name
Test status
Simulation time 978190453 ps
CPU time 2.3 seconds
Started Mar 31 12:39:13 PM PDT 24
Finished Mar 31 12:39:16 PM PDT 24
Peak memory 195760 kb
Host smart-b61ff257-e2c0-4a95-9a49-938f27a83974
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417022182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.3417022182
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.338154475
Short name T405
Test name
Test status
Simulation time 41058503 ps
CPU time 1.02 seconds
Started Mar 31 12:39:09 PM PDT 24
Finished Mar 31 12:39:10 PM PDT 24
Peak memory 195700 kb
Host smart-92739a3c-1d12-47b3-99e6-067584234de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338154475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.338154475
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.1365453521
Short name T618
Test name
Test status
Simulation time 31148653 ps
CPU time 1.19 seconds
Started Mar 31 12:39:04 PM PDT 24
Finished Mar 31 12:39:06 PM PDT 24
Peak memory 197132 kb
Host smart-e9008a72-b109-47d9-806b-00da5cccf33f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365453521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.1365453521
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.3681059287
Short name T512
Test name
Test status
Simulation time 447628535 ps
CPU time 5.13 seconds
Started Mar 31 12:39:12 PM PDT 24
Finished Mar 31 12:39:18 PM PDT 24
Peak memory 197976 kb
Host smart-5f66704f-0506-4f31-a321-7ccc614ba695
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681059287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.3681059287
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.1973948954
Short name T466
Test name
Test status
Simulation time 544248562 ps
CPU time 1.04 seconds
Started Mar 31 12:39:09 PM PDT 24
Finished Mar 31 12:39:10 PM PDT 24
Peak memory 196360 kb
Host smart-e53061fc-387a-450b-b535-ce923e60c625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973948954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.1973948954
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.2301521094
Short name T635
Test name
Test status
Simulation time 427298277 ps
CPU time 0.97 seconds
Started Mar 31 12:39:14 PM PDT 24
Finished Mar 31 12:39:15 PM PDT 24
Peak memory 195772 kb
Host smart-c1f6038e-127e-42cf-97f4-64da5d1904eb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301521094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.2301521094
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.3032921642
Short name T130
Test name
Test status
Simulation time 8208513334 ps
CPU time 97.72 seconds
Started Mar 31 12:39:16 PM PDT 24
Finished Mar 31 12:40:55 PM PDT 24
Peak memory 198048 kb
Host smart-7a5a16fa-e955-4a22-9b43-e3d53908dd27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032921642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.3032921642
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.3730096793
Short name T152
Test name
Test status
Simulation time 13520722 ps
CPU time 0.57 seconds
Started Mar 31 12:39:08 PM PDT 24
Finished Mar 31 12:39:09 PM PDT 24
Peak memory 193880 kb
Host smart-13b37ab2-9678-4ef2-9fb3-49911fd8dbda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730096793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.3730096793
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.1389101488
Short name T376
Test name
Test status
Simulation time 19882080 ps
CPU time 0.75 seconds
Started Mar 31 12:39:09 PM PDT 24
Finished Mar 31 12:39:10 PM PDT 24
Peak memory 194820 kb
Host smart-96419bfc-4cdc-475e-8943-e5096348de95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389101488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.1389101488
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.3516822577
Short name T632
Test name
Test status
Simulation time 276212963 ps
CPU time 9.26 seconds
Started Mar 31 12:39:11 PM PDT 24
Finished Mar 31 12:39:20 PM PDT 24
Peak memory 197936 kb
Host smart-64e9870a-ca69-4473-8dcd-ede5a9509372
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516822577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.3516822577
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.2142241894
Short name T398
Test name
Test status
Simulation time 226737737 ps
CPU time 1.05 seconds
Started Mar 31 12:39:13 PM PDT 24
Finished Mar 31 12:39:15 PM PDT 24
Peak memory 197848 kb
Host smart-d9c3eda2-93ec-470e-a51f-fcfcc6cee2cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142241894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.2142241894
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.2588892206
Short name T407
Test name
Test status
Simulation time 777205052 ps
CPU time 1.35 seconds
Started Mar 31 12:39:13 PM PDT 24
Finished Mar 31 12:39:15 PM PDT 24
Peak memory 197020 kb
Host smart-0cbea9c4-aa61-44a4-af93-06d4583bb8cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588892206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.2588892206
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.1262521882
Short name T367
Test name
Test status
Simulation time 33026660 ps
CPU time 1.36 seconds
Started Mar 31 12:39:14 PM PDT 24
Finished Mar 31 12:39:16 PM PDT 24
Peak memory 198120 kb
Host smart-4ddf2632-28fd-4322-a836-744c340c81a9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262521882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.1262521882
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.2238131264
Short name T671
Test name
Test status
Simulation time 46342396 ps
CPU time 1.55 seconds
Started Mar 31 12:39:10 PM PDT 24
Finished Mar 31 12:39:12 PM PDT 24
Peak memory 196340 kb
Host smart-b8dfeade-48b6-4b68-90f3-5bf8f3eb7457
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238131264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.2238131264
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.672422126
Short name T612
Test name
Test status
Simulation time 64794901 ps
CPU time 1.36 seconds
Started Mar 31 12:39:11 PM PDT 24
Finished Mar 31 12:39:13 PM PDT 24
Peak memory 198032 kb
Host smart-f871a17c-9b99-461f-878d-3c0a80020c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672422126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.672422126
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.3617840870
Short name T128
Test name
Test status
Simulation time 110122788 ps
CPU time 1.08 seconds
Started Mar 31 12:39:13 PM PDT 24
Finished Mar 31 12:39:15 PM PDT 24
Peak memory 195644 kb
Host smart-94f4a2f9-39aa-454a-9e03-ddceb2ebd966
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617840870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.3617840870
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.307218473
Short name T358
Test name
Test status
Simulation time 1292979682 ps
CPU time 5.42 seconds
Started Mar 31 12:39:10 PM PDT 24
Finished Mar 31 12:39:16 PM PDT 24
Peak memory 197876 kb
Host smart-441cde38-f52f-4ff4-8156-6ff0538acae9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307218473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ran
dom_long_reg_writes_reg_reads.307218473
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.3883919918
Short name T604
Test name
Test status
Simulation time 171931694 ps
CPU time 1.3 seconds
Started Mar 31 12:39:13 PM PDT 24
Finished Mar 31 12:39:15 PM PDT 24
Peak memory 197920 kb
Host smart-caa7a5a6-e80c-4b01-901a-05bc9f0f61d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883919918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.3883919918
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.1186830378
Short name T283
Test name
Test status
Simulation time 80098258 ps
CPU time 1.43 seconds
Started Mar 31 12:39:09 PM PDT 24
Finished Mar 31 12:39:11 PM PDT 24
Peak memory 196700 kb
Host smart-f022ef46-28ee-418e-9a03-f580733c7970
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186830378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.1186830378
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.3025141223
Short name T112
Test name
Test status
Simulation time 24003615950 ps
CPU time 136.8 seconds
Started Mar 31 12:39:09 PM PDT 24
Finished Mar 31 12:41:26 PM PDT 24
Peak memory 198108 kb
Host smart-afcb0574-3baa-44cd-bf44-f86e17c462d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025141223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.3025141223
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.897527652
Short name T704
Test name
Test status
Simulation time 36776688 ps
CPU time 0.57 seconds
Started Mar 31 12:39:13 PM PDT 24
Finished Mar 31 12:39:14 PM PDT 24
Peak memory 193900 kb
Host smart-c8d6b761-6e61-40d1-bbbe-d6b89efa8f0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897527652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.897527652
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.2505214775
Short name T17
Test name
Test status
Simulation time 129068448 ps
CPU time 0.86 seconds
Started Mar 31 12:39:10 PM PDT 24
Finished Mar 31 12:39:11 PM PDT 24
Peak memory 196152 kb
Host smart-a6416ab3-ce3d-4d24-9c8a-3379722d559e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505214775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.2505214775
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.1299013257
Short name T261
Test name
Test status
Simulation time 790661861 ps
CPU time 23.46 seconds
Started Mar 31 12:39:14 PM PDT 24
Finished Mar 31 12:39:38 PM PDT 24
Peak memory 196840 kb
Host smart-52d13e96-2f5c-4eb2-9e94-09e04f382429
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299013257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.1299013257
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.3815231755
Short name T228
Test name
Test status
Simulation time 83941204 ps
CPU time 0.92 seconds
Started Mar 31 12:39:10 PM PDT 24
Finished Mar 31 12:39:11 PM PDT 24
Peak memory 195940 kb
Host smart-7bda8143-a439-4ec6-bacf-a417883f261b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815231755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.3815231755
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.3752394311
Short name T596
Test name
Test status
Simulation time 195277776 ps
CPU time 1.08 seconds
Started Mar 31 12:39:13 PM PDT 24
Finished Mar 31 12:39:14 PM PDT 24
Peak memory 195840 kb
Host smart-6f5eb131-7764-4e84-a4d6-6ec732bb1072
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752394311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.3752394311
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.204459472
Short name T710
Test name
Test status
Simulation time 194595506 ps
CPU time 2.01 seconds
Started Mar 31 12:39:23 PM PDT 24
Finished Mar 31 12:39:25 PM PDT 24
Peak memory 198020 kb
Host smart-b43c2fda-5a1f-4243-a1cd-154ebcbd6f17
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204459472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.gpio_intr_with_filter_rand_intr_event.204459472
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.2544326545
Short name T103
Test name
Test status
Simulation time 181338416 ps
CPU time 1.66 seconds
Started Mar 31 12:39:16 PM PDT 24
Finished Mar 31 12:39:18 PM PDT 24
Peak memory 196600 kb
Host smart-83ac1cd4-ac99-4efc-a43f-ae594487daa3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544326545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.2544326545
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.3505690529
Short name T461
Test name
Test status
Simulation time 23692935 ps
CPU time 0.93 seconds
Started Mar 31 12:39:07 PM PDT 24
Finished Mar 31 12:39:09 PM PDT 24
Peak memory 195996 kb
Host smart-bc41be7f-3688-4e32-9cce-32e1b733316f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505690529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.3505690529
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.200959422
Short name T679
Test name
Test status
Simulation time 18893300 ps
CPU time 0.78 seconds
Started Mar 31 12:39:18 PM PDT 24
Finished Mar 31 12:39:18 PM PDT 24
Peak memory 195512 kb
Host smart-eb3ed1b9-624e-4d01-abd0-4bd77d903d5f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200959422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullup
_pulldown.200959422
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.4208055401
Short name T520
Test name
Test status
Simulation time 740107438 ps
CPU time 3.43 seconds
Started Mar 31 12:39:17 PM PDT 24
Finished Mar 31 12:39:20 PM PDT 24
Peak memory 197888 kb
Host smart-86c48645-ca5e-4c86-a222-45c14dabaeb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208055401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.4208055401
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.3663805479
Short name T191
Test name
Test status
Simulation time 80515321 ps
CPU time 1.42 seconds
Started Mar 31 12:39:17 PM PDT 24
Finished Mar 31 12:39:19 PM PDT 24
Peak memory 197892 kb
Host smart-a7b6be76-04cf-4e55-b059-a18734cd4d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663805479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.3663805479
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.1506996978
Short name T585
Test name
Test status
Simulation time 77027596 ps
CPU time 1.19 seconds
Started Mar 31 12:39:16 PM PDT 24
Finished Mar 31 12:39:17 PM PDT 24
Peak memory 195504 kb
Host smart-e2572352-5b34-48a0-9a33-855f71c10f97
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506996978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.1506996978
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.2901240720
Short name T651
Test name
Test status
Simulation time 33569746738 ps
CPU time 55.98 seconds
Started Mar 31 12:39:15 PM PDT 24
Finished Mar 31 12:40:11 PM PDT 24
Peak memory 198196 kb
Host smart-ce678596-0c1c-475d-9eb0-f89c71618aa9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901240720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.2901240720
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.1415851408
Short name T64
Test name
Test status
Simulation time 566839994696 ps
CPU time 2119.67 seconds
Started Mar 31 12:39:09 PM PDT 24
Finished Mar 31 01:14:30 PM PDT 24
Peak memory 198172 kb
Host smart-6cc82832-6652-4cba-8f82-fa7e3c6114b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1415851408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.1415851408
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.2845512016
Short name T646
Test name
Test status
Simulation time 13101927 ps
CPU time 0.62 seconds
Started Mar 31 12:39:14 PM PDT 24
Finished Mar 31 12:39:15 PM PDT 24
Peak memory 194940 kb
Host smart-1a20cb04-ef77-4fc7-9d00-3d8d395f796f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845512016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.2845512016
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.1167786229
Short name T205
Test name
Test status
Simulation time 28475957 ps
CPU time 0.77 seconds
Started Mar 31 12:39:14 PM PDT 24
Finished Mar 31 12:39:15 PM PDT 24
Peak memory 196008 kb
Host smart-34ea5819-6902-4d2d-8941-57b3600f165b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167786229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.1167786229
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.2513688557
Short name T29
Test name
Test status
Simulation time 144471644 ps
CPU time 6.54 seconds
Started Mar 31 12:39:11 PM PDT 24
Finished Mar 31 12:39:19 PM PDT 24
Peak memory 197964 kb
Host smart-dd578ec0-308b-475c-8fa0-b0e334634f70
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513688557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.2513688557
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.2777166385
Short name T323
Test name
Test status
Simulation time 577699899 ps
CPU time 0.92 seconds
Started Mar 31 12:39:12 PM PDT 24
Finished Mar 31 12:39:13 PM PDT 24
Peak memory 197196 kb
Host smart-911b43df-778f-476c-8131-7c9f5678ddba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777166385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.2777166385
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.3573450410
Short name T337
Test name
Test status
Simulation time 322427474 ps
CPU time 1.26 seconds
Started Mar 31 12:39:14 PM PDT 24
Finished Mar 31 12:39:15 PM PDT 24
Peak memory 197104 kb
Host smart-d5e3e84f-c69a-431b-ae2e-67121bd4a04c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573450410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.3573450410
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.1700499210
Short name T639
Test name
Test status
Simulation time 121145819 ps
CPU time 3.22 seconds
Started Mar 31 12:39:07 PM PDT 24
Finished Mar 31 12:39:10 PM PDT 24
Peak memory 198128 kb
Host smart-fd608234-a514-4573-8e5f-77cad899bfff
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700499210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.1700499210
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.262714715
Short name T247
Test name
Test status
Simulation time 187525639 ps
CPU time 2.17 seconds
Started Mar 31 12:39:13 PM PDT 24
Finished Mar 31 12:39:16 PM PDT 24
Peak memory 198000 kb
Host smart-98962530-ccbf-4ac3-85d1-827e4150426e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262714715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger.
262714715
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.340611599
Short name T508
Test name
Test status
Simulation time 22669115 ps
CPU time 0.94 seconds
Started Mar 31 12:39:20 PM PDT 24
Finished Mar 31 12:39:21 PM PDT 24
Peak memory 195916 kb
Host smart-4a0c6b13-a9e7-4bd6-ba6f-b5877ecfe8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340611599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.340611599
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.3687743481
Short name T543
Test name
Test status
Simulation time 522579941 ps
CPU time 1.27 seconds
Started Mar 31 12:39:09 PM PDT 24
Finished Mar 31 12:39:11 PM PDT 24
Peak memory 196484 kb
Host smart-3635d6fe-1daa-4376-bb34-b0d049f7fd85
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687743481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.3687743481
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.2730093463
Short name T455
Test name
Test status
Simulation time 67072443 ps
CPU time 2.99 seconds
Started Mar 31 12:39:12 PM PDT 24
Finished Mar 31 12:39:15 PM PDT 24
Peak memory 197964 kb
Host smart-3924dc87-acfc-40a8-ae58-7ea4a32287fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730093463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.2730093463
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.1433615955
Short name T453
Test name
Test status
Simulation time 96718554 ps
CPU time 1.55 seconds
Started Mar 31 12:39:17 PM PDT 24
Finished Mar 31 12:39:19 PM PDT 24
Peak memory 197940 kb
Host smart-0ca35f10-937c-433d-9a4f-808d78a1cb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433615955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.1433615955
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.2064775176
Short name T333
Test name
Test status
Simulation time 22340321 ps
CPU time 0.79 seconds
Started Mar 31 12:39:09 PM PDT 24
Finished Mar 31 12:39:10 PM PDT 24
Peak memory 195840 kb
Host smart-b116e5bb-8715-4203-b2a7-c4a82dc83aa9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064775176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.2064775176
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.1900360940
Short name T440
Test name
Test status
Simulation time 22248899748 ps
CPU time 71.98 seconds
Started Mar 31 12:39:15 PM PDT 24
Finished Mar 31 12:40:27 PM PDT 24
Peak memory 198188 kb
Host smart-28b7f135-90c6-4abc-858c-3e81b577be11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900360940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.1900360940
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.1551790686
Short name T417
Test name
Test status
Simulation time 14805660 ps
CPU time 0.56 seconds
Started Mar 31 12:39:18 PM PDT 24
Finished Mar 31 12:39:18 PM PDT 24
Peak memory 193888 kb
Host smart-c3154800-7aa2-406c-b705-dfff2842d04b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551790686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.1551790686
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.1122878247
Short name T613
Test name
Test status
Simulation time 35657288 ps
CPU time 0.83 seconds
Started Mar 31 12:39:11 PM PDT 24
Finished Mar 31 12:39:13 PM PDT 24
Peak memory 195288 kb
Host smart-21a305eb-9951-461d-bdfb-27060a4d8240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122878247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.1122878247
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.1901945142
Short name T158
Test name
Test status
Simulation time 3223992476 ps
CPU time 26.06 seconds
Started Mar 31 12:39:19 PM PDT 24
Finished Mar 31 12:39:45 PM PDT 24
Peak memory 197432 kb
Host smart-b77e712d-7bb0-4312-bf2e-7ab0a02e1e35
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901945142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.1901945142
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.2025470654
Short name T584
Test name
Test status
Simulation time 63739126 ps
CPU time 0.84 seconds
Started Mar 31 12:39:19 PM PDT 24
Finished Mar 31 12:39:20 PM PDT 24
Peak memory 195976 kb
Host smart-3931b2c6-684f-4b9f-9fef-05890c373b43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025470654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.2025470654
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.798104129
Short name T687
Test name
Test status
Simulation time 204647471 ps
CPU time 1.37 seconds
Started Mar 31 12:39:15 PM PDT 24
Finished Mar 31 12:39:17 PM PDT 24
Peak memory 197016 kb
Host smart-7f9efee6-9540-4ab3-a2f1-d11596a9c895
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798104129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.798104129
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.3404019060
Short name T647
Test name
Test status
Simulation time 611174148 ps
CPU time 3.84 seconds
Started Mar 31 12:39:14 PM PDT 24
Finished Mar 31 12:39:19 PM PDT 24
Peak memory 198044 kb
Host smart-c04e0377-771d-43da-ae35-0f4ef2c85664
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404019060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.3404019060
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.4142162312
Short name T125
Test name
Test status
Simulation time 176835906 ps
CPU time 1.5 seconds
Started Mar 31 12:39:13 PM PDT 24
Finished Mar 31 12:39:15 PM PDT 24
Peak memory 195956 kb
Host smart-7b64d1cb-d112-4997-9da1-4cc537ef54fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142162312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.4142162312
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.285702765
Short name T464
Test name
Test status
Simulation time 52766017 ps
CPU time 1.09 seconds
Started Mar 31 12:39:11 PM PDT 24
Finished Mar 31 12:39:12 PM PDT 24
Peak memory 197996 kb
Host smart-26bbadfa-2863-4036-bda9-42cedf0bd55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285702765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.285702765
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.601944905
Short name T274
Test name
Test status
Simulation time 360226502 ps
CPU time 1.04 seconds
Started Mar 31 12:39:19 PM PDT 24
Finished Mar 31 12:39:20 PM PDT 24
Peak memory 195776 kb
Host smart-2671cb52-a2dd-480f-9a45-91b8ef96aa4e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601944905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullup
_pulldown.601944905
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.3016804174
Short name T636
Test name
Test status
Simulation time 139359293 ps
CPU time 3.52 seconds
Started Mar 31 12:39:12 PM PDT 24
Finished Mar 31 12:39:17 PM PDT 24
Peak memory 197904 kb
Host smart-85b3d78e-9781-40ed-a1bd-b2e6635d6e5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016804174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.3016804174
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.596106876
Short name T680
Test name
Test status
Simulation time 85225794 ps
CPU time 0.78 seconds
Started Mar 31 12:39:12 PM PDT 24
Finished Mar 31 12:39:13 PM PDT 24
Peak memory 195340 kb
Host smart-d6ad31bb-efa3-4f89-82cc-0f732f0d15b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596106876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.596106876
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.1395129169
Short name T394
Test name
Test status
Simulation time 34524865 ps
CPU time 0.75 seconds
Started Mar 31 12:39:18 PM PDT 24
Finished Mar 31 12:39:19 PM PDT 24
Peak memory 194904 kb
Host smart-83663265-35cb-4c02-9a79-485db86fd485
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395129169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.1395129169
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.4240888668
Short name T590
Test name
Test status
Simulation time 12190587101 ps
CPU time 176.36 seconds
Started Mar 31 12:39:23 PM PDT 24
Finished Mar 31 12:42:20 PM PDT 24
Peak memory 198124 kb
Host smart-7851d4f1-12e5-4676-bfbe-ab2c9da853f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240888668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.4240888668
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.3155285292
Short name T284
Test name
Test status
Simulation time 19588396 ps
CPU time 0.57 seconds
Started Mar 31 12:39:20 PM PDT 24
Finished Mar 31 12:39:21 PM PDT 24
Peak memory 193824 kb
Host smart-a24b6537-f552-4450-9073-cf4b55ffdcc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155285292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.3155285292
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.743588317
Short name T305
Test name
Test status
Simulation time 26448172 ps
CPU time 0.67 seconds
Started Mar 31 12:39:18 PM PDT 24
Finished Mar 31 12:39:18 PM PDT 24
Peak memory 194148 kb
Host smart-fe4bb6b0-ac2b-4f66-917f-31d949aa15c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743588317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.743588317
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.2680650830
Short name T216
Test name
Test status
Simulation time 556930965 ps
CPU time 16.55 seconds
Started Mar 31 12:39:19 PM PDT 24
Finished Mar 31 12:39:36 PM PDT 24
Peak memory 196212 kb
Host smart-a9a894d1-dca7-4bde-a15b-ac1a631ab340
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680650830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.2680650830
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.841583062
Short name T565
Test name
Test status
Simulation time 114959353 ps
CPU time 0.82 seconds
Started Mar 31 12:39:16 PM PDT 24
Finished Mar 31 12:39:18 PM PDT 24
Peak memory 196740 kb
Host smart-628431a6-839d-45ab-ab2a-24c2c5cf87f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841583062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.841583062
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.2538117271
Short name T54
Test name
Test status
Simulation time 43075181 ps
CPU time 0.8 seconds
Started Mar 31 12:39:22 PM PDT 24
Finished Mar 31 12:39:23 PM PDT 24
Peak memory 195372 kb
Host smart-caf0617e-d76b-4aa7-8fd2-1de094c08ca3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538117271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.2538117271
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.2178935949
Short name T290
Test name
Test status
Simulation time 59909223 ps
CPU time 2.66 seconds
Started Mar 31 12:39:21 PM PDT 24
Finished Mar 31 12:39:24 PM PDT 24
Peak memory 198080 kb
Host smart-3b67f966-3f69-4125-a620-4b21c20961c1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178935949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.2178935949
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.3815492203
Short name T147
Test name
Test status
Simulation time 279044185 ps
CPU time 3.05 seconds
Started Mar 31 12:39:15 PM PDT 24
Finished Mar 31 12:39:19 PM PDT 24
Peak memory 197232 kb
Host smart-a5a31cf0-94fd-4651-a6fd-bb9d92d21b4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815492203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.3815492203
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.3403727971
Short name T258
Test name
Test status
Simulation time 23857757 ps
CPU time 0.75 seconds
Started Mar 31 12:39:15 PM PDT 24
Finished Mar 31 12:39:16 PM PDT 24
Peak memory 196120 kb
Host smart-e2bbe71a-88c0-44c4-ab67-9fd42059c28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403727971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.3403727971
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.2954179792
Short name T326
Test name
Test status
Simulation time 235469791 ps
CPU time 1.1 seconds
Started Mar 31 12:39:15 PM PDT 24
Finished Mar 31 12:39:17 PM PDT 24
Peak memory 196536 kb
Host smart-066b63dd-9d42-44d3-86cf-9f6997658e42
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954179792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.2954179792
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.445593925
Short name T483
Test name
Test status
Simulation time 129051187 ps
CPU time 1.57 seconds
Started Mar 31 12:39:19 PM PDT 24
Finished Mar 31 12:39:21 PM PDT 24
Peak memory 197936 kb
Host smart-5f2df7a5-d648-4cc1-bd7a-31593fcbaaa7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445593925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ran
dom_long_reg_writes_reg_reads.445593925
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.3974246773
Short name T193
Test name
Test status
Simulation time 47553664 ps
CPU time 0.84 seconds
Started Mar 31 12:39:16 PM PDT 24
Finished Mar 31 12:39:18 PM PDT 24
Peak memory 196288 kb
Host smart-3f4f90d4-7c25-4145-a2a6-44784759ccfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974246773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.3974246773
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2133541368
Short name T662
Test name
Test status
Simulation time 149278243 ps
CPU time 1.21 seconds
Started Mar 31 12:39:10 PM PDT 24
Finished Mar 31 12:39:11 PM PDT 24
Peak memory 196436 kb
Host smart-da30cd49-929b-423f-bfbe-be98580816a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133541368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.2133541368
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.1218496988
Short name T192
Test name
Test status
Simulation time 19763767113 ps
CPU time 53.83 seconds
Started Mar 31 12:39:19 PM PDT 24
Finished Mar 31 12:40:13 PM PDT 24
Peak memory 198152 kb
Host smart-fe0d89b6-6a86-4b00-b02b-347b53a05fde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218496988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.1218496988
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.1341992671
Short name T260
Test name
Test status
Simulation time 92833700 ps
CPU time 0.58 seconds
Started Mar 31 12:37:49 PM PDT 24
Finished Mar 31 12:37:50 PM PDT 24
Peak memory 193952 kb
Host smart-175cde4c-12a8-4b91-9925-e28f500032de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341992671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.1341992671
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2330266487
Short name T15
Test name
Test status
Simulation time 38051099 ps
CPU time 0.73 seconds
Started Mar 31 12:37:59 PM PDT 24
Finished Mar 31 12:37:59 PM PDT 24
Peak memory 195980 kb
Host smart-1929fa90-d05a-4f2f-8176-b1943a7966d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330266487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2330266487
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.3973750512
Short name T502
Test name
Test status
Simulation time 124007432 ps
CPU time 6.65 seconds
Started Mar 31 12:37:52 PM PDT 24
Finished Mar 31 12:37:59 PM PDT 24
Peak memory 197896 kb
Host smart-81e1ae86-a43d-4257-be79-54a327b75338
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973750512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.3973750512
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.2132508391
Short name T363
Test name
Test status
Simulation time 239595574 ps
CPU time 0.88 seconds
Started Mar 31 12:38:00 PM PDT 24
Finished Mar 31 12:38:01 PM PDT 24
Peak memory 196892 kb
Host smart-20b601e7-99dd-4e5a-931d-d755a267c9b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132508391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.2132508391
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.3762539383
Short name T626
Test name
Test status
Simulation time 268771507 ps
CPU time 0.78 seconds
Started Mar 31 12:37:50 PM PDT 24
Finished Mar 31 12:37:53 PM PDT 24
Peak memory 195396 kb
Host smart-d3836d98-401f-4a3d-bfc6-95709819cd24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762539383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.3762539383
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.3094258812
Short name T275
Test name
Test status
Simulation time 314343600 ps
CPU time 2.48 seconds
Started Mar 31 12:38:12 PM PDT 24
Finished Mar 31 12:38:14 PM PDT 24
Peak memory 198056 kb
Host smart-d50de45e-5909-4802-b023-4dfd27316ce4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094258812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.3094258812
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.3467495417
Short name T144
Test name
Test status
Simulation time 1026998427 ps
CPU time 3.4 seconds
Started Mar 31 12:37:51 PM PDT 24
Finished Mar 31 12:37:56 PM PDT 24
Peak memory 195804 kb
Host smart-a8fcfb9b-9b32-48ad-bd31-68e8bba16143
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467495417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
3467495417
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.681109299
Short name T460
Test name
Test status
Simulation time 98547255 ps
CPU time 1.03 seconds
Started Mar 31 12:38:06 PM PDT 24
Finished Mar 31 12:38:07 PM PDT 24
Peak memory 196448 kb
Host smart-4779fdcf-804a-4e41-96e0-be0b7a8de898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681109299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.681109299
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.3990974933
Short name T606
Test name
Test status
Simulation time 24200973 ps
CPU time 0.87 seconds
Started Mar 31 12:38:05 PM PDT 24
Finished Mar 31 12:38:06 PM PDT 24
Peak memory 196068 kb
Host smart-cf0d57c7-1c97-43e3-801d-7ddec7f64856
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990974933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.3990974933
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.608949587
Short name T656
Test name
Test status
Simulation time 366544575 ps
CPU time 6.05 seconds
Started Mar 31 12:37:52 PM PDT 24
Finished Mar 31 12:37:58 PM PDT 24
Peak memory 197892 kb
Host smart-1e9b3d71-25fb-43ac-a062-44f8f3a604fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608949587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand
om_long_reg_writes_reg_reads.608949587
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.576938235
Short name T188
Test name
Test status
Simulation time 239101637 ps
CPU time 0.72 seconds
Started Mar 31 12:37:49 PM PDT 24
Finished Mar 31 12:37:50 PM PDT 24
Peak memory 195984 kb
Host smart-c6463adb-7d2b-4499-b250-feedbc4fd6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576938235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.576938235
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.1611377356
Short name T210
Test name
Test status
Simulation time 23777268 ps
CPU time 0.71 seconds
Started Mar 31 12:38:00 PM PDT 24
Finished Mar 31 12:38:00 PM PDT 24
Peak memory 194916 kb
Host smart-14b8d0f1-a7ea-41e0-9568-93451fe1b1dc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611377356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.1611377356
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.2795863714
Short name T267
Test name
Test status
Simulation time 88481126766 ps
CPU time 98.61 seconds
Started Mar 31 12:37:50 PM PDT 24
Finished Mar 31 12:39:29 PM PDT 24
Peak memory 198168 kb
Host smart-17229e73-fb29-4a6b-ba4b-570987c9ad12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795863714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.2795863714
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.2813773674
Short name T61
Test name
Test status
Simulation time 13274609433 ps
CPU time 344.32 seconds
Started Mar 31 12:38:10 PM PDT 24
Finished Mar 31 12:43:55 PM PDT 24
Peak memory 198272 kb
Host smart-864a535e-5728-4ff7-9717-d75d4d844e02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2813773674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.2813773674
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.2915673394
Short name T246
Test name
Test status
Simulation time 25599732 ps
CPU time 0.6 seconds
Started Mar 31 12:37:56 PM PDT 24
Finished Mar 31 12:37:57 PM PDT 24
Peak memory 194048 kb
Host smart-18f25f04-ab95-4376-b85e-39846c5e7080
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915673394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.2915673394
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.2405678496
Short name T518
Test name
Test status
Simulation time 155743326 ps
CPU time 0.72 seconds
Started Mar 31 12:37:57 PM PDT 24
Finished Mar 31 12:37:58 PM PDT 24
Peak memory 195248 kb
Host smart-70f59ea8-1d3f-4eb2-b1aa-cf7136f59b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405678496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.2405678496
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.1729204885
Short name T110
Test name
Test status
Simulation time 2982121852 ps
CPU time 21.13 seconds
Started Mar 31 12:38:00 PM PDT 24
Finished Mar 31 12:38:21 PM PDT 24
Peak memory 196620 kb
Host smart-8df83f66-0db7-4213-a8cb-a5c2a25940f0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729204885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.1729204885
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.671843149
Short name T588
Test name
Test status
Simulation time 88117096 ps
CPU time 1.02 seconds
Started Mar 31 12:37:53 PM PDT 24
Finished Mar 31 12:37:55 PM PDT 24
Peak memory 196292 kb
Host smart-201e6a87-01c5-4e96-86cf-a9d3b36240f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671843149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.671843149
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.2591292350
Short name T426
Test name
Test status
Simulation time 27762870 ps
CPU time 0.73 seconds
Started Mar 31 12:37:53 PM PDT 24
Finished Mar 31 12:37:55 PM PDT 24
Peak memory 194980 kb
Host smart-f6052d6f-b778-4386-92a5-5c5f6b00e5ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591292350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.2591292350
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.3609943787
Short name T190
Test name
Test status
Simulation time 279155993 ps
CPU time 2.98 seconds
Started Mar 31 12:37:56 PM PDT 24
Finished Mar 31 12:37:59 PM PDT 24
Peak memory 198000 kb
Host smart-4a2fd243-6b09-4ddd-ac78-1291098501d0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609943787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.3609943787
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.1548634535
Short name T625
Test name
Test status
Simulation time 327665443 ps
CPU time 2.62 seconds
Started Mar 31 12:37:54 PM PDT 24
Finished Mar 31 12:37:58 PM PDT 24
Peak memory 197884 kb
Host smart-7fad5df4-d501-4f1e-9010-861934dcc05e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548634535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
1548634535
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.2507494225
Short name T556
Test name
Test status
Simulation time 21758900 ps
CPU time 0.83 seconds
Started Mar 31 12:37:56 PM PDT 24
Finished Mar 31 12:37:57 PM PDT 24
Peak memory 196624 kb
Host smart-9e09f3b3-0d40-4554-8914-d5a78a858c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507494225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.2507494225
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.626892513
Short name T178
Test name
Test status
Simulation time 114389024 ps
CPU time 1.22 seconds
Started Mar 31 12:37:56 PM PDT 24
Finished Mar 31 12:37:58 PM PDT 24
Peak memory 196924 kb
Host smart-533690d1-9316-4529-bdc4-5b05e23682f2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626892513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_
pulldown.626892513
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.545546680
Short name T136
Test name
Test status
Simulation time 59180398 ps
CPU time 2.56 seconds
Started Mar 31 12:38:01 PM PDT 24
Finished Mar 31 12:38:03 PM PDT 24
Peak memory 197940 kb
Host smart-dc92e45e-c706-4c5b-be3a-824d27e8cc4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545546680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand
om_long_reg_writes_reg_reads.545546680
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.1039103873
Short name T692
Test name
Test status
Simulation time 117503950 ps
CPU time 1.01 seconds
Started Mar 31 12:37:57 PM PDT 24
Finished Mar 31 12:37:58 PM PDT 24
Peak memory 195668 kb
Host smart-1aa42818-4469-4f96-b6be-dabf1746fd7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039103873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.1039103873
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.357883160
Short name T423
Test name
Test status
Simulation time 230789626 ps
CPU time 1.36 seconds
Started Mar 31 12:38:07 PM PDT 24
Finished Mar 31 12:38:08 PM PDT 24
Peak memory 196848 kb
Host smart-621010b7-758c-4b33-a572-e0ef999671cc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357883160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.357883160
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.3766044532
Short name T354
Test name
Test status
Simulation time 7230930664 ps
CPU time 168.82 seconds
Started Mar 31 12:38:01 PM PDT 24
Finished Mar 31 12:40:50 PM PDT 24
Peak memory 198220 kb
Host smart-9aefea11-df61-4cda-943b-c720c2572265
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766044532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.3766044532
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.266655423
Short name T421
Test name
Test status
Simulation time 1361652942120 ps
CPU time 1869 seconds
Started Mar 31 12:37:53 PM PDT 24
Finished Mar 31 01:09:03 PM PDT 24
Peak memory 206408 kb
Host smart-11e67fd4-6621-4357-bd7c-34229ed158dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=266655423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.266655423
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.4256163973
Short name T217
Test name
Test status
Simulation time 14834406 ps
CPU time 0.64 seconds
Started Mar 31 12:37:54 PM PDT 24
Finished Mar 31 12:37:55 PM PDT 24
Peak memory 194136 kb
Host smart-d8cb5d19-5efa-44cd-8a81-ddfbc1a949ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256163973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.4256163973
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.3590932098
Short name T286
Test name
Test status
Simulation time 37991134 ps
CPU time 0.86 seconds
Started Mar 31 12:37:49 PM PDT 24
Finished Mar 31 12:37:50 PM PDT 24
Peak memory 195524 kb
Host smart-62e530fa-1a16-4c5a-83a5-a2addaa7cf14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590932098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.3590932098
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.2214335026
Short name T344
Test name
Test status
Simulation time 2269489824 ps
CPU time 28.73 seconds
Started Mar 31 12:38:16 PM PDT 24
Finished Mar 31 12:38:45 PM PDT 24
Peak memory 196848 kb
Host smart-2f848751-b341-4ef9-8f4d-76242a6f271e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214335026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.2214335026
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.551099084
Short name T488
Test name
Test status
Simulation time 63930780 ps
CPU time 0.89 seconds
Started Mar 31 12:38:18 PM PDT 24
Finished Mar 31 12:38:19 PM PDT 24
Peak memory 196036 kb
Host smart-24e92f03-a16c-4b3c-8f53-772f38433695
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551099084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.551099084
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.1703096299
Short name T328
Test name
Test status
Simulation time 67502900 ps
CPU time 0.66 seconds
Started Mar 31 12:38:15 PM PDT 24
Finished Mar 31 12:38:16 PM PDT 24
Peak memory 194364 kb
Host smart-98edc976-55dc-4b34-a047-504ec2c44905
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703096299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.1703096299
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.90232900
Short name T364
Test name
Test status
Simulation time 172588169 ps
CPU time 2.82 seconds
Started Mar 31 12:38:19 PM PDT 24
Finished Mar 31 12:38:22 PM PDT 24
Peak memory 196320 kb
Host smart-8de0f0c6-2f6b-492a-8be2-d6cb27b20004
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90232900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.gpio_intr_with_filter_rand_intr_event.90232900
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.4034527163
Short name T501
Test name
Test status
Simulation time 53614878 ps
CPU time 1.28 seconds
Started Mar 31 12:38:06 PM PDT 24
Finished Mar 31 12:38:07 PM PDT 24
Peak memory 197444 kb
Host smart-6acf7767-e44e-4001-88e4-5ef649ede3ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034527163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
4034527163
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.4168194546
Short name T163
Test name
Test status
Simulation time 54293470 ps
CPU time 1.24 seconds
Started Mar 31 12:37:52 PM PDT 24
Finished Mar 31 12:37:54 PM PDT 24
Peak memory 196900 kb
Host smart-fcc2a297-953a-49e4-a6b5-c003a22d7ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168194546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.4168194546
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3438040694
Short name T463
Test name
Test status
Simulation time 29715009 ps
CPU time 0.79 seconds
Started Mar 31 12:37:53 PM PDT 24
Finished Mar 31 12:37:54 PM PDT 24
Peak memory 195360 kb
Host smart-e9389dce-c19a-4e5f-80d8-5304f4bfd111
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438040694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.3438040694
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.4141027091
Short name T314
Test name
Test status
Simulation time 8267929067 ps
CPU time 4.8 seconds
Started Mar 31 12:37:57 PM PDT 24
Finished Mar 31 12:38:02 PM PDT 24
Peak memory 197976 kb
Host smart-66e1a564-6ad6-43bf-bc5d-530ede6f4aea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141027091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.4141027091
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.427346584
Short name T696
Test name
Test status
Simulation time 43129691 ps
CPU time 1.06 seconds
Started Mar 31 12:37:53 PM PDT 24
Finished Mar 31 12:37:55 PM PDT 24
Peak memory 195648 kb
Host smart-b9c741d4-18af-4cef-8683-0dc11ae1c388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427346584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.427346584
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.3729559940
Short name T369
Test name
Test status
Simulation time 27842406 ps
CPU time 0.96 seconds
Started Mar 31 12:37:53 PM PDT 24
Finished Mar 31 12:37:55 PM PDT 24
Peak memory 196236 kb
Host smart-d275c67a-48bc-4251-aa01-4e456327b2f6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729559940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.3729559940
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.3052324612
Short name T139
Test name
Test status
Simulation time 12603353838 ps
CPU time 79.42 seconds
Started Mar 31 12:38:17 PM PDT 24
Finished Mar 31 12:39:36 PM PDT 24
Peak memory 198196 kb
Host smart-99c23c3d-d92e-4599-94fa-84f2ce5bf5bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052324612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.3052324612
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.2740480570
Short name T238
Test name
Test status
Simulation time 25108677 ps
CPU time 0.58 seconds
Started Mar 31 12:37:57 PM PDT 24
Finished Mar 31 12:37:58 PM PDT 24
Peak memory 194032 kb
Host smart-76f57f9b-f022-4d12-8908-15f097bcbc8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740480570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.2740480570
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.936221290
Short name T378
Test name
Test status
Simulation time 49026316 ps
CPU time 0.6 seconds
Started Mar 31 12:38:18 PM PDT 24
Finished Mar 31 12:38:19 PM PDT 24
Peak memory 193944 kb
Host smart-fcc51fa6-d3ef-4d62-b1b9-8f25f58353d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936221290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.936221290
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.2025874247
Short name T196
Test name
Test status
Simulation time 3329304615 ps
CPU time 8.6 seconds
Started Mar 31 12:38:04 PM PDT 24
Finished Mar 31 12:38:13 PM PDT 24
Peak memory 197104 kb
Host smart-d33291c7-907e-4dda-8c26-c7066ca1700b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025874247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.2025874247
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.2803310608
Short name T411
Test name
Test status
Simulation time 30964610 ps
CPU time 0.72 seconds
Started Mar 31 12:37:58 PM PDT 24
Finished Mar 31 12:37:59 PM PDT 24
Peak memory 195644 kb
Host smart-bf44b790-efac-48ba-89aa-f003bbbad840
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803310608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.2803310608
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.2482158199
Short name T432
Test name
Test status
Simulation time 177274919 ps
CPU time 1.32 seconds
Started Mar 31 12:37:55 PM PDT 24
Finished Mar 31 12:37:57 PM PDT 24
Peak memory 197024 kb
Host smart-49f17ae8-6fe7-4737-a643-92d095e7ae2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482158199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.2482158199
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.2663461139
Short name T150
Test name
Test status
Simulation time 174167974 ps
CPU time 1.92 seconds
Started Mar 31 12:38:18 PM PDT 24
Finished Mar 31 12:38:20 PM PDT 24
Peak memory 198104 kb
Host smart-60f39e65-1fb8-4b6b-84a0-bf3625adbd5c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663461139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.2663461139
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.739704259
Short name T505
Test name
Test status
Simulation time 422419990 ps
CPU time 3.08 seconds
Started Mar 31 12:37:56 PM PDT 24
Finished Mar 31 12:38:00 PM PDT 24
Peak memory 196424 kb
Host smart-a1427f67-08d2-4556-8ce0-571ed3f9d3f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739704259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.739704259
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.2787972440
Short name T664
Test name
Test status
Simulation time 45834599 ps
CPU time 1.06 seconds
Started Mar 31 12:37:58 PM PDT 24
Finished Mar 31 12:37:59 PM PDT 24
Peak memory 196636 kb
Host smart-9938acf4-3f2a-435c-948d-a3a833f39546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787972440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.2787972440
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.2703261822
Short name T270
Test name
Test status
Simulation time 66548334 ps
CPU time 1.25 seconds
Started Mar 31 12:38:14 PM PDT 24
Finished Mar 31 12:38:15 PM PDT 24
Peak memory 197068 kb
Host smart-c6ccb4dc-7361-4d15-ba46-b2df062dbac1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703261822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.2703261822
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.1497770149
Short name T352
Test name
Test status
Simulation time 396800662 ps
CPU time 3 seconds
Started Mar 31 12:37:58 PM PDT 24
Finished Mar 31 12:38:01 PM PDT 24
Peak memory 198004 kb
Host smart-e0b9f7a4-27e4-42e1-bed7-54616f1a677c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497770149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.1497770149
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.559648113
Short name T153
Test name
Test status
Simulation time 44213018 ps
CPU time 1.01 seconds
Started Mar 31 12:37:57 PM PDT 24
Finished Mar 31 12:37:58 PM PDT 24
Peak memory 196252 kb
Host smart-00941f5f-78f1-436b-b10d-69f40362e5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559648113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.559648113
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.2479942444
Short name T99
Test name
Test status
Simulation time 168621045 ps
CPU time 1.34 seconds
Started Mar 31 12:38:13 PM PDT 24
Finished Mar 31 12:38:15 PM PDT 24
Peak memory 198156 kb
Host smart-50f798c4-87c8-4ae3-add2-b9d98ea61a4a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479942444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.2479942444
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.613979370
Short name T9
Test name
Test status
Simulation time 19982787644 ps
CPU time 120.35 seconds
Started Mar 31 12:38:15 PM PDT 24
Finished Mar 31 12:40:15 PM PDT 24
Peak memory 198192 kb
Host smart-6bf6173a-0649-4513-b0d5-672a6eafa914
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613979370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gp
io_stress_all.613979370
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.107163232
Short name T576
Test name
Test status
Simulation time 49440984 ps
CPU time 0.59 seconds
Started Mar 31 12:38:04 PM PDT 24
Finished Mar 31 12:38:05 PM PDT 24
Peak memory 193752 kb
Host smart-e0815d9d-249b-4693-b489-f06b87c3c2e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107163232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.107163232
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.2810432629
Short name T490
Test name
Test status
Simulation time 132516913 ps
CPU time 0.72 seconds
Started Mar 31 12:38:07 PM PDT 24
Finished Mar 31 12:38:08 PM PDT 24
Peak memory 195280 kb
Host smart-74256c74-d81e-4ea8-91d6-c60e25cbf646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810432629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.2810432629
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.3199370688
Short name T468
Test name
Test status
Simulation time 374665664 ps
CPU time 19.25 seconds
Started Mar 31 12:38:21 PM PDT 24
Finished Mar 31 12:38:40 PM PDT 24
Peak memory 197952 kb
Host smart-a61e989f-350a-488c-8023-7903c5b2c0e8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199370688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.3199370688
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.4229415316
Short name T292
Test name
Test status
Simulation time 72276088 ps
CPU time 1.07 seconds
Started Mar 31 12:38:20 PM PDT 24
Finished Mar 31 12:38:21 PM PDT 24
Peak memory 196536 kb
Host smart-c9534813-0869-4dcf-801d-7c8d9d3dd180
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229415316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.4229415316
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.2318026303
Short name T219
Test name
Test status
Simulation time 45283626 ps
CPU time 1.28 seconds
Started Mar 31 12:38:17 PM PDT 24
Finished Mar 31 12:38:18 PM PDT 24
Peak memory 196788 kb
Host smart-d90ad3bd-e962-4a76-9b00-e0e951c1a81c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318026303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.2318026303
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.772922940
Short name T327
Test name
Test status
Simulation time 200998972 ps
CPU time 1.67 seconds
Started Mar 31 12:37:57 PM PDT 24
Finished Mar 31 12:37:59 PM PDT 24
Peak memory 196324 kb
Host smart-bb763911-e15b-4125-ac52-f1aecbe0485c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772922940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.gpio_intr_with_filter_rand_intr_event.772922940
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.984966896
Short name T482
Test name
Test status
Simulation time 79424617 ps
CPU time 1.7 seconds
Started Mar 31 12:38:22 PM PDT 24
Finished Mar 31 12:38:23 PM PDT 24
Peak memory 196848 kb
Host smart-bfaa6c7b-1d83-4d71-8af2-ad2264cfcc25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984966896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.984966896
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.1629639190
Short name T296
Test name
Test status
Simulation time 112968231 ps
CPU time 1.14 seconds
Started Mar 31 12:37:57 PM PDT 24
Finished Mar 31 12:37:59 PM PDT 24
Peak memory 196752 kb
Host smart-023f846b-6867-4184-aafd-933243ae0c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629639190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.1629639190
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.2540909685
Short name T627
Test name
Test status
Simulation time 143111134 ps
CPU time 0.97 seconds
Started Mar 31 12:37:58 PM PDT 24
Finished Mar 31 12:37:59 PM PDT 24
Peak memory 196664 kb
Host smart-00ae0f8d-87e2-48b6-959b-45578d6181e2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540909685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.2540909685
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.2600560768
Short name T374
Test name
Test status
Simulation time 653090759 ps
CPU time 4.33 seconds
Started Mar 31 12:38:19 PM PDT 24
Finished Mar 31 12:38:23 PM PDT 24
Peak memory 197560 kb
Host smart-8c137133-bbc4-4ae8-8e3c-dc9553dddb26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600560768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.2600560768
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.670526557
Short name T446
Test name
Test status
Simulation time 47590724 ps
CPU time 0.88 seconds
Started Mar 31 12:37:58 PM PDT 24
Finished Mar 31 12:37:59 PM PDT 24
Peak memory 195368 kb
Host smart-ed2d68c7-e562-4bb2-9913-afdd5c5758a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670526557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.670526557
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.3442869756
Short name T491
Test name
Test status
Simulation time 93112622 ps
CPU time 1.03 seconds
Started Mar 31 12:38:06 PM PDT 24
Finished Mar 31 12:38:07 PM PDT 24
Peak memory 196588 kb
Host smart-7bfc14cf-e7bc-49c1-879a-dde021b010b1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442869756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.3442869756
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.1045645138
Short name T450
Test name
Test status
Simulation time 55468414956 ps
CPU time 167.45 seconds
Started Mar 31 12:38:27 PM PDT 24
Finished Mar 31 12:41:15 PM PDT 24
Peak memory 198168 kb
Host smart-414608a9-004d-4920-85c2-4886abd8c3db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045645138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.1045645138
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.767573938
Short name T891
Test name
Test status
Simulation time 517858075 ps
CPU time 1.23 seconds
Started Mar 31 12:28:20 PM PDT 24
Finished Mar 31 12:28:21 PM PDT 24
Peak memory 192216 kb
Host smart-e755120f-5dd7-4a03-ae67-48bd5d689a53
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=767573938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.767573938
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.744376401
Short name T911
Test name
Test status
Simulation time 72468397 ps
CPU time 0.98 seconds
Started Mar 31 12:28:19 PM PDT 24
Finished Mar 31 12:28:20 PM PDT 24
Peak memory 192192 kb
Host smart-b474d7cb-5dd7-426a-89fc-9b50d43f1bf1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744376401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.744376401
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.113427464
Short name T862
Test name
Test status
Simulation time 39773194 ps
CPU time 0.96 seconds
Started Mar 31 12:28:23 PM PDT 24
Finished Mar 31 12:28:24 PM PDT 24
Peak memory 192036 kb
Host smart-18d18df4-741a-4f5d-af6c-086dea9f7f65
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=113427464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.113427464
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3927352923
Short name T858
Test name
Test status
Simulation time 64624416 ps
CPU time 1.18 seconds
Started Mar 31 12:29:30 PM PDT 24
Finished Mar 31 12:29:31 PM PDT 24
Peak memory 192060 kb
Host smart-ca66193f-df80-48e9-a049-ecb58a4f5c9f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927352923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3927352923
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2224439233
Short name T885
Test name
Test status
Simulation time 290432212 ps
CPU time 1.25 seconds
Started Mar 31 12:28:13 PM PDT 24
Finished Mar 31 12:28:14 PM PDT 24
Peak memory 197788 kb
Host smart-443e11c3-b658-45a9-9691-3f5894d78cca
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2224439233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.2224439233
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.614951742
Short name T870
Test name
Test status
Simulation time 54813910 ps
CPU time 1.18 seconds
Started Mar 31 12:28:14 PM PDT 24
Finished Mar 31 12:28:15 PM PDT 24
Peak memory 192212 kb
Host smart-ef6d3249-3270-4bbc-a025-ed8996299861
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614951742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.614951742
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3094168553
Short name T863
Test name
Test status
Simulation time 28663263 ps
CPU time 0.94 seconds
Started Mar 31 12:28:19 PM PDT 24
Finished Mar 31 12:28:20 PM PDT 24
Peak memory 192128 kb
Host smart-fe0b2b1b-b682-40e4-93ef-40844099691f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3094168553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.3094168553
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.731256824
Short name T887
Test name
Test status
Simulation time 52930002 ps
CPU time 0.95 seconds
Started Mar 31 12:28:45 PM PDT 24
Finished Mar 31 12:28:46 PM PDT 24
Peak memory 192020 kb
Host smart-2e3406a2-1986-4f46-b3b6-08f28f0e7983
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731256824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.731256824
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2592738536
Short name T851
Test name
Test status
Simulation time 51842583 ps
CPU time 0.99 seconds
Started Mar 31 12:28:11 PM PDT 24
Finished Mar 31 12:28:12 PM PDT 24
Peak memory 198324 kb
Host smart-2c0a23fe-52d3-4d4b-9ff4-fc4530366ae2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2592738536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.2592738536
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3844183452
Short name T930
Test name
Test status
Simulation time 363090996 ps
CPU time 1.07 seconds
Started Mar 31 12:28:35 PM PDT 24
Finished Mar 31 12:28:37 PM PDT 24
Peak memory 198484 kb
Host smart-c611a474-845b-421d-ade3-88f3b7a276d1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844183452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3844183452
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2746003689
Short name T908
Test name
Test status
Simulation time 168880622 ps
CPU time 0.9 seconds
Started Mar 31 12:28:40 PM PDT 24
Finished Mar 31 12:28:41 PM PDT 24
Peak memory 196588 kb
Host smart-e3cce54f-d2a0-4cf3-b454-e4e300897ec6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2746003689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.2746003689
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2229595265
Short name T909
Test name
Test status
Simulation time 33721168 ps
CPU time 1.04 seconds
Started Mar 31 12:28:15 PM PDT 24
Finished Mar 31 12:28:17 PM PDT 24
Peak memory 192172 kb
Host smart-7201ecff-4139-4494-9fc2-9134b1799aa7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229595265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2229595265
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.279075938
Short name T921
Test name
Test status
Simulation time 125211126 ps
CPU time 0.92 seconds
Started Mar 31 12:28:25 PM PDT 24
Finished Mar 31 12:28:26 PM PDT 24
Peak memory 198332 kb
Host smart-174e33cd-bde0-4feb-ae29-185dc1114396
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=279075938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.279075938
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1325178863
Short name T879
Test name
Test status
Simulation time 262566922 ps
CPU time 1.29 seconds
Started Mar 31 12:28:00 PM PDT 24
Finished Mar 31 12:28:01 PM PDT 24
Peak memory 198496 kb
Host smart-efd90786-2974-45b6-afaa-d2d99c5cc18c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325178863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1325178863
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2477562095
Short name T847
Test name
Test status
Simulation time 42034388 ps
CPU time 1.27 seconds
Started Mar 31 12:28:24 PM PDT 24
Finished Mar 31 12:28:25 PM PDT 24
Peak memory 198480 kb
Host smart-1ce6459b-e286-4f07-9f58-bca33d3c9fd0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2477562095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.2477562095
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2006909914
Short name T859
Test name
Test status
Simulation time 558184285 ps
CPU time 1.16 seconds
Started Mar 31 12:28:31 PM PDT 24
Finished Mar 31 12:28:32 PM PDT 24
Peak memory 192288 kb
Host smart-7fc17af2-b08f-4823-aac7-44bb8371f933
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006909914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2006909914
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2764355071
Short name T932
Test name
Test status
Simulation time 71544847 ps
CPU time 1.24 seconds
Started Mar 31 12:28:14 PM PDT 24
Finished Mar 31 12:28:15 PM PDT 24
Peak memory 198780 kb
Host smart-58ce2d6b-1155-4724-b61c-c84903ff6461
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2764355071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.2764355071
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4072215626
Short name T893
Test name
Test status
Simulation time 55970057 ps
CPU time 1.42 seconds
Started Mar 31 12:28:20 PM PDT 24
Finished Mar 31 12:28:21 PM PDT 24
Peak memory 192216 kb
Host smart-fdf3f598-15f2-4f1c-9e74-e6254645bc2d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072215626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4072215626
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.832443269
Short name T907
Test name
Test status
Simulation time 87194938 ps
CPU time 1.39 seconds
Started Mar 31 12:28:22 PM PDT 24
Finished Mar 31 12:28:24 PM PDT 24
Peak memory 192272 kb
Host smart-ac85fae9-14f5-4920-81cd-c74d56f50d6b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=832443269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.832443269
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.743087821
Short name T888
Test name
Test status
Simulation time 263180423 ps
CPU time 1.33 seconds
Started Mar 31 12:28:28 PM PDT 24
Finished Mar 31 12:28:29 PM PDT 24
Peak memory 192160 kb
Host smart-2d722c75-245e-4c0b-be54-2d0c2bcc2baa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743087821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.743087821
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3965866935
Short name T846
Test name
Test status
Simulation time 85946235 ps
CPU time 1.19 seconds
Started Mar 31 12:28:26 PM PDT 24
Finished Mar 31 12:28:32 PM PDT 24
Peak memory 198520 kb
Host smart-d38f5fe9-b079-4293-a7ba-ed23dcf56920
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3965866935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.3965866935
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2518448446
Short name T865
Test name
Test status
Simulation time 176115478 ps
CPU time 0.9 seconds
Started Mar 31 12:28:22 PM PDT 24
Finished Mar 31 12:28:23 PM PDT 24
Peak memory 192020 kb
Host smart-a51c5a44-ff34-4e20-aa68-973958970a19
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518448446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2518448446
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.4133572757
Short name T927
Test name
Test status
Simulation time 285556823 ps
CPU time 1.31 seconds
Started Mar 31 12:28:05 PM PDT 24
Finished Mar 31 12:28:06 PM PDT 24
Peak memory 192200 kb
Host smart-8e0cc2fc-412a-4d30-8184-847c1f751943
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4133572757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.4133572757
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4203121507
Short name T843
Test name
Test status
Simulation time 376723773 ps
CPU time 1.27 seconds
Started Mar 31 12:27:59 PM PDT 24
Finished Mar 31 12:28:01 PM PDT 24
Peak memory 192220 kb
Host smart-bbcb63f8-b372-4e43-a565-ae60cea8b1c5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203121507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4203121507
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3284434900
Short name T897
Test name
Test status
Simulation time 159643894 ps
CPU time 0.91 seconds
Started Mar 31 12:29:26 PM PDT 24
Finished Mar 31 12:29:27 PM PDT 24
Peak memory 191600 kb
Host smart-b696fbc8-20a8-42ce-8f4a-94dd38d6c8a4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3284434900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.3284434900
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2552915760
Short name T869
Test name
Test status
Simulation time 154331160 ps
CPU time 1.13 seconds
Started Mar 31 12:29:31 PM PDT 24
Finished Mar 31 12:29:32 PM PDT 24
Peak memory 192056 kb
Host smart-badb3c2a-6b95-4096-abde-6419492bb711
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552915760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2552915760
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3483845905
Short name T918
Test name
Test status
Simulation time 231805873 ps
CPU time 1.06 seconds
Started Mar 31 12:27:58 PM PDT 24
Finished Mar 31 12:28:04 PM PDT 24
Peak memory 198500 kb
Host smart-08fac8e0-c737-4e06-9f82-8134250e3379
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3483845905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.3483845905
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3838694625
Short name T903
Test name
Test status
Simulation time 396629406 ps
CPU time 1.26 seconds
Started Mar 31 12:27:52 PM PDT 24
Finished Mar 31 12:27:54 PM PDT 24
Peak memory 192216 kb
Host smart-bb3fba11-4a3f-4e42-9c17-38c89f8e0e3b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838694625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3838694625
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1918990327
Short name T917
Test name
Test status
Simulation time 120399198 ps
CPU time 1.04 seconds
Started Mar 31 12:28:29 PM PDT 24
Finished Mar 31 12:28:31 PM PDT 24
Peak memory 192188 kb
Host smart-5d0900f7-fd54-406d-b6b0-8b89629c75de
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1918990327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.1918990327
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.758399390
Short name T875
Test name
Test status
Simulation time 227329004 ps
CPU time 1.07 seconds
Started Mar 31 12:28:21 PM PDT 24
Finished Mar 31 12:28:22 PM PDT 24
Peak memory 192184 kb
Host smart-7bc1b7df-9c4f-4455-86eb-8b2c0886b5c7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758399390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.758399390
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.90849804
Short name T889
Test name
Test status
Simulation time 36555078 ps
CPU time 1.12 seconds
Started Mar 31 12:28:36 PM PDT 24
Finished Mar 31 12:28:37 PM PDT 24
Peak memory 198064 kb
Host smart-d5507257-8a47-4689-b7ed-6405fdc2e598
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=90849804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.90849804
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2223096641
Short name T866
Test name
Test status
Simulation time 229313947 ps
CPU time 1.13 seconds
Started Mar 31 12:28:23 PM PDT 24
Finished Mar 31 12:28:30 PM PDT 24
Peak memory 192164 kb
Host smart-cd35420a-8c61-426c-81f1-3ed08c91d991
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223096641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2223096641
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.782636408
Short name T936
Test name
Test status
Simulation time 71035271 ps
CPU time 1.01 seconds
Started Mar 31 12:28:32 PM PDT 24
Finished Mar 31 12:28:33 PM PDT 24
Peak memory 191984 kb
Host smart-b36abd58-4ec1-418b-8439-ca83ae79eab5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=782636408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.782636408
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2574927661
Short name T884
Test name
Test status
Simulation time 55173503 ps
CPU time 1.06 seconds
Started Mar 31 12:28:28 PM PDT 24
Finished Mar 31 12:28:29 PM PDT 24
Peak memory 192228 kb
Host smart-bd2be7e3-6334-41c5-a8aa-2c57b71c3103
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574927661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2574927661
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2902983898
Short name T902
Test name
Test status
Simulation time 196526678 ps
CPU time 0.92 seconds
Started Mar 31 12:28:19 PM PDT 24
Finished Mar 31 12:28:20 PM PDT 24
Peak memory 192140 kb
Host smart-6d9d5ca6-95c2-443c-be11-f442061efc8a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2902983898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.2902983898
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2922645935
Short name T842
Test name
Test status
Simulation time 74497948 ps
CPU time 0.97 seconds
Started Mar 31 12:28:32 PM PDT 24
Finished Mar 31 12:28:33 PM PDT 24
Peak memory 192040 kb
Host smart-62b2a4ef-7b0b-475c-9933-e6b089ab2a19
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922645935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2922645935
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1939190133
Short name T895
Test name
Test status
Simulation time 31397850 ps
CPU time 0.8 seconds
Started Mar 31 12:28:39 PM PDT 24
Finished Mar 31 12:28:40 PM PDT 24
Peak memory 191984 kb
Host smart-feb48750-0114-4b1b-be48-cf262969144e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1939190133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.1939190133
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3871170188
Short name T937
Test name
Test status
Simulation time 43973474 ps
CPU time 1.22 seconds
Started Mar 31 12:28:25 PM PDT 24
Finished Mar 31 12:28:27 PM PDT 24
Peak memory 197768 kb
Host smart-d5bcebcd-ee7d-45e1-ad9d-f04e80ce60fd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871170188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3871170188
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.2157377687
Short name T878
Test name
Test status
Simulation time 747235319 ps
CPU time 1.37 seconds
Started Mar 31 12:28:07 PM PDT 24
Finished Mar 31 12:28:09 PM PDT 24
Peak memory 192148 kb
Host smart-4d003385-3565-40ab-9aa8-5bb7fea531c2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2157377687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.2157377687
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4008999419
Short name T872
Test name
Test status
Simulation time 44136941 ps
CPU time 0.9 seconds
Started Mar 31 12:28:01 PM PDT 24
Finished Mar 31 12:28:02 PM PDT 24
Peak memory 198284 kb
Host smart-b98d0bf8-c8f9-4cd3-a494-60ef115bc47e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008999419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4008999419
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2124295384
Short name T877
Test name
Test status
Simulation time 982286509 ps
CPU time 1.29 seconds
Started Mar 31 12:28:32 PM PDT 24
Finished Mar 31 12:28:33 PM PDT 24
Peak memory 192148 kb
Host smart-aeea011d-a798-4444-91b6-21c685fac79c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2124295384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.2124295384
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.412781457
Short name T920
Test name
Test status
Simulation time 110037197 ps
CPU time 0.9 seconds
Started Mar 31 12:28:21 PM PDT 24
Finished Mar 31 12:28:22 PM PDT 24
Peak memory 192020 kb
Host smart-7abf6406-6068-4379-b498-3fabad2001ae
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412781457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.412781457
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.148322561
Short name T938
Test name
Test status
Simulation time 228725513 ps
CPU time 1.12 seconds
Started Mar 31 12:28:00 PM PDT 24
Finished Mar 31 12:28:01 PM PDT 24
Peak memory 192160 kb
Host smart-6ec213db-e58b-4c07-9193-278ff8d3f104
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=148322561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.148322561
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2855324018
Short name T934
Test name
Test status
Simulation time 89396189 ps
CPU time 0.94 seconds
Started Mar 31 12:28:40 PM PDT 24
Finished Mar 31 12:28:41 PM PDT 24
Peak memory 192016 kb
Host smart-abcc69a8-9ee1-4ab8-8c03-1cd26b0d7cfe
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855324018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2855324018
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3931309959
Short name T928
Test name
Test status
Simulation time 40854183 ps
CPU time 0.83 seconds
Started Mar 31 12:28:02 PM PDT 24
Finished Mar 31 12:28:03 PM PDT 24
Peak memory 191992 kb
Host smart-b77e307a-f3ab-49d8-9bcb-59f52e161ca4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3931309959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.3931309959
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3233205823
Short name T941
Test name
Test status
Simulation time 108557439 ps
CPU time 1.26 seconds
Started Mar 31 12:28:22 PM PDT 24
Finished Mar 31 12:28:24 PM PDT 24
Peak memory 192180 kb
Host smart-7a22f6f8-25ff-4291-b2f2-2dcb80fee90e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233205823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3233205823
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.3668825729
Short name T914
Test name
Test status
Simulation time 60658673 ps
CPU time 0.81 seconds
Started Mar 31 12:29:27 PM PDT 24
Finished Mar 31 12:29:28 PM PDT 24
Peak memory 191788 kb
Host smart-7b93d65b-4c71-4f96-bd47-a95671338665
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3668825729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.3668825729
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2483814535
Short name T935
Test name
Test status
Simulation time 70018830 ps
CPU time 1.03 seconds
Started Mar 31 12:28:05 PM PDT 24
Finished Mar 31 12:28:06 PM PDT 24
Peak memory 192164 kb
Host smart-2bfda597-b8fa-447d-b092-d2b97eecf9b2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483814535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2483814535
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1358149602
Short name T901
Test name
Test status
Simulation time 331050727 ps
CPU time 1.22 seconds
Started Mar 31 12:29:01 PM PDT 24
Finished Mar 31 12:29:04 PM PDT 24
Peak memory 191088 kb
Host smart-30b7c5fe-3c83-4217-a84c-8b844f05fb50
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1358149602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.1358149602
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.494460196
Short name T904
Test name
Test status
Simulation time 466969759 ps
CPU time 1.19 seconds
Started Mar 31 12:28:04 PM PDT 24
Finished Mar 31 12:28:05 PM PDT 24
Peak memory 192208 kb
Host smart-78e070ab-31d9-4608-8f2e-61ee236d8756
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494460196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.494460196
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3574268307
Short name T939
Test name
Test status
Simulation time 61276692 ps
CPU time 1.03 seconds
Started Mar 31 12:28:18 PM PDT 24
Finished Mar 31 12:28:19 PM PDT 24
Peak memory 192148 kb
Host smart-d751c09d-8d92-42bc-a326-24d60d6dc33f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3574268307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.3574268307
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3484510617
Short name T854
Test name
Test status
Simulation time 94982445 ps
CPU time 1.43 seconds
Started Mar 31 12:28:23 PM PDT 24
Finished Mar 31 12:28:24 PM PDT 24
Peak memory 198512 kb
Host smart-c8eedf85-b475-426c-84c2-e02781d0fc8a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484510617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3484510617
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3779069475
Short name T882
Test name
Test status
Simulation time 50916884 ps
CPU time 0.87 seconds
Started Mar 31 12:28:23 PM PDT 24
Finished Mar 31 12:28:24 PM PDT 24
Peak memory 198396 kb
Host smart-c95efcae-f961-4a1e-83d4-57d08dcbb1e5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3779069475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.3779069475
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.169830804
Short name T881
Test name
Test status
Simulation time 39197182 ps
CPU time 0.78 seconds
Started Mar 31 12:28:07 PM PDT 24
Finished Mar 31 12:28:08 PM PDT 24
Peak memory 191976 kb
Host smart-407b9a45-3e3c-4f95-ba6e-53851f6f1b51
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169830804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.169830804
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.4048737717
Short name T849
Test name
Test status
Simulation time 164195060 ps
CPU time 1.21 seconds
Started Mar 31 12:27:57 PM PDT 24
Finished Mar 31 12:28:03 PM PDT 24
Peak memory 192216 kb
Host smart-72efc4ae-6131-4bb1-a58d-be3e8b5ef8e8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4048737717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.4048737717
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2269568390
Short name T844
Test name
Test status
Simulation time 146367637 ps
CPU time 1.4 seconds
Started Mar 31 12:28:38 PM PDT 24
Finished Mar 31 12:28:39 PM PDT 24
Peak memory 192436 kb
Host smart-6b69d447-66b2-48cb-8195-dcc92b804e1b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269568390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2269568390
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.374142315
Short name T853
Test name
Test status
Simulation time 82329832 ps
CPU time 1.25 seconds
Started Mar 31 12:28:16 PM PDT 24
Finished Mar 31 12:28:18 PM PDT 24
Peak memory 197712 kb
Host smart-f81f179c-a399-490b-8daa-6ac908ebd4ae
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=374142315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.374142315
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.154933150
Short name T868
Test name
Test status
Simulation time 398069948 ps
CPU time 1.26 seconds
Started Mar 31 12:28:26 PM PDT 24
Finished Mar 31 12:28:28 PM PDT 24
Peak memory 192136 kb
Host smart-e9c976ea-8e34-498f-85c0-8c926723d440
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154933150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.154933150
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1385450802
Short name T896
Test name
Test status
Simulation time 51042246 ps
CPU time 0.99 seconds
Started Mar 31 12:27:59 PM PDT 24
Finished Mar 31 12:28:00 PM PDT 24
Peak memory 192188 kb
Host smart-7673abd8-4858-45b1-9c4c-f72822c70252
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1385450802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.1385450802
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.245426146
Short name T850
Test name
Test status
Simulation time 159847929 ps
CPU time 1.34 seconds
Started Mar 31 12:27:58 PM PDT 24
Finished Mar 31 12:28:00 PM PDT 24
Peak memory 192160 kb
Host smart-f6f037b1-5be5-4dec-a332-5905cad3d08f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245426146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.245426146
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.741065856
Short name T940
Test name
Test status
Simulation time 32329456 ps
CPU time 0.89 seconds
Started Mar 31 12:28:00 PM PDT 24
Finished Mar 31 12:28:01 PM PDT 24
Peak memory 192020 kb
Host smart-0f64abf7-620b-4f55-9d39-4329d254b05b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=741065856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.741065856
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3995222760
Short name T856
Test name
Test status
Simulation time 97085889 ps
CPU time 1.34 seconds
Started Mar 31 12:29:23 PM PDT 24
Finished Mar 31 12:29:24 PM PDT 24
Peak memory 192140 kb
Host smart-e04927e7-5cf4-4098-9eaf-36cd2132f988
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995222760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3995222760
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2819035807
Short name T906
Test name
Test status
Simulation time 598955693 ps
CPU time 1.03 seconds
Started Mar 31 12:28:27 PM PDT 24
Finished Mar 31 12:28:28 PM PDT 24
Peak memory 198536 kb
Host smart-74565b38-c4bb-4444-9b5c-c63c1e794896
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2819035807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.2819035807
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1379274586
Short name T931
Test name
Test status
Simulation time 133763169 ps
CPU time 0.9 seconds
Started Mar 31 12:28:38 PM PDT 24
Finished Mar 31 12:28:39 PM PDT 24
Peak memory 192284 kb
Host smart-4bb80244-4b48-4d26-af4d-73ba92ed6b3b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379274586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1379274586
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3139099800
Short name T916
Test name
Test status
Simulation time 25071580 ps
CPU time 0.85 seconds
Started Mar 31 12:27:58 PM PDT 24
Finished Mar 31 12:27:59 PM PDT 24
Peak memory 192016 kb
Host smart-2b12ff9f-c5dd-4ea8-a154-9bf0cf094313
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3139099800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.3139099800
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3307181001
Short name T852
Test name
Test status
Simulation time 99445961 ps
CPU time 0.98 seconds
Started Mar 31 12:29:23 PM PDT 24
Finished Mar 31 12:29:24 PM PDT 24
Peak memory 198428 kb
Host smart-def16fc6-2976-437a-b408-97b601fb0e78
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307181001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3307181001
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2752263930
Short name T880
Test name
Test status
Simulation time 155247310 ps
CPU time 1.57 seconds
Started Mar 31 12:28:24 PM PDT 24
Finished Mar 31 12:28:26 PM PDT 24
Peak memory 198452 kb
Host smart-77fcae88-8e0c-4461-a4d1-906be162e00f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2752263930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.2752263930
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2247677246
Short name T883
Test name
Test status
Simulation time 238906525 ps
CPU time 1.18 seconds
Started Mar 31 12:29:01 PM PDT 24
Finished Mar 31 12:29:08 PM PDT 24
Peak memory 191612 kb
Host smart-e0f68c61-82ab-43ca-b44a-bd2feec518d3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247677246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2247677246
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3812764788
Short name T919
Test name
Test status
Simulation time 39591443 ps
CPU time 1.2 seconds
Started Mar 31 12:28:30 PM PDT 24
Finished Mar 31 12:28:32 PM PDT 24
Peak memory 192164 kb
Host smart-b362e0c5-fab3-45a2-bba7-1bd0f11e332e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3812764788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.3812764788
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3555836362
Short name T933
Test name
Test status
Simulation time 214282539 ps
CPU time 1.15 seconds
Started Mar 31 12:28:13 PM PDT 24
Finished Mar 31 12:28:14 PM PDT 24
Peak memory 192060 kb
Host smart-f2817dd8-3d73-4726-87b0-b303d07dbea1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555836362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3555836362
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1400915614
Short name T923
Test name
Test status
Simulation time 104395225 ps
CPU time 1.61 seconds
Started Mar 31 12:28:30 PM PDT 24
Finished Mar 31 12:28:32 PM PDT 24
Peak memory 192212 kb
Host smart-2124fcb6-ce9c-4a4c-8c92-f2a4bce5bcba
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1400915614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.1400915614
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.655395395
Short name T845
Test name
Test status
Simulation time 85883011 ps
CPU time 1.23 seconds
Started Mar 31 12:28:05 PM PDT 24
Finished Mar 31 12:28:06 PM PDT 24
Peak memory 192172 kb
Host smart-97822c97-4e06-4d44-bc87-53ac81f8ade0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655395395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.655395395
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3753491502
Short name T892
Test name
Test status
Simulation time 69233045 ps
CPU time 1.34 seconds
Started Mar 31 12:28:37 PM PDT 24
Finished Mar 31 12:28:39 PM PDT 24
Peak memory 192516 kb
Host smart-096be86c-3efc-400c-a53e-7e801f18f80f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3753491502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.3753491502
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2788235469
Short name T871
Test name
Test status
Simulation time 86323601 ps
CPU time 1.13 seconds
Started Mar 31 12:28:39 PM PDT 24
Finished Mar 31 12:28:40 PM PDT 24
Peak memory 192448 kb
Host smart-b91438ca-41ef-466f-91c4-3c1492af736a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788235469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2788235469
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3953638289
Short name T915
Test name
Test status
Simulation time 59605867 ps
CPU time 1.08 seconds
Started Mar 31 12:28:39 PM PDT 24
Finished Mar 31 12:28:40 PM PDT 24
Peak memory 192160 kb
Host smart-cc8556bf-9f60-4c02-a179-0e528df7e940
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3953638289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.3953638289
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.84834878
Short name T905
Test name
Test status
Simulation time 81954232 ps
CPU time 1.32 seconds
Started Mar 31 12:28:40 PM PDT 24
Finished Mar 31 12:28:41 PM PDT 24
Peak memory 192192 kb
Host smart-604b2475-697c-4ab0-b12f-5b58e19157f9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84834878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.84834878
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1499566078
Short name T898
Test name
Test status
Simulation time 52224713 ps
CPU time 0.95 seconds
Started Mar 31 12:28:38 PM PDT 24
Finished Mar 31 12:28:39 PM PDT 24
Peak memory 192460 kb
Host smart-303fb6e1-5336-43a4-801f-ca6fb61335b2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1499566078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.1499566078
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.217801259
Short name T855
Test name
Test status
Simulation time 55682119 ps
CPU time 0.98 seconds
Started Mar 31 12:28:29 PM PDT 24
Finished Mar 31 12:28:31 PM PDT 24
Peak memory 192152 kb
Host smart-2e00c0a9-0e36-4c07-8468-d355ec5fca27
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217801259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.217801259
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.4243443631
Short name T925
Test name
Test status
Simulation time 51024107 ps
CPU time 1.06 seconds
Started Mar 31 12:29:36 PM PDT 24
Finished Mar 31 12:29:37 PM PDT 24
Peak memory 192088 kb
Host smart-deee249a-3fd6-4063-98f4-1109c16f75d9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4243443631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.4243443631
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3510716488
Short name T874
Test name
Test status
Simulation time 141551567 ps
CPU time 1.07 seconds
Started Mar 31 12:28:27 PM PDT 24
Finished Mar 31 12:28:28 PM PDT 24
Peak memory 192172 kb
Host smart-586b1399-dca1-416c-82f4-b6ebaed45762
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510716488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3510716488
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.914488021
Short name T864
Test name
Test status
Simulation time 198695104 ps
CPU time 1.09 seconds
Started Mar 31 12:29:19 PM PDT 24
Finished Mar 31 12:29:20 PM PDT 24
Peak memory 198420 kb
Host smart-5bd35406-2363-4242-b710-15ed685e1d85
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=914488021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.914488021
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1771138161
Short name T922
Test name
Test status
Simulation time 279598721 ps
CPU time 1.23 seconds
Started Mar 31 12:28:22 PM PDT 24
Finished Mar 31 12:28:23 PM PDT 24
Peak memory 192452 kb
Host smart-947a92e2-a0f5-44c9-923b-ea1a5865146a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771138161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1771138161
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.3280146335
Short name T861
Test name
Test status
Simulation time 90287804 ps
CPU time 1.03 seconds
Started Mar 31 12:28:31 PM PDT 24
Finished Mar 31 12:28:32 PM PDT 24
Peak memory 192236 kb
Host smart-884d99f2-9f7c-4081-b4bb-7b1ab19a5c5c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3280146335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.3280146335
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1779460141
Short name T900
Test name
Test status
Simulation time 732635852 ps
CPU time 1.12 seconds
Started Mar 31 12:28:33 PM PDT 24
Finished Mar 31 12:28:35 PM PDT 24
Peak memory 197136 kb
Host smart-c96fef82-effa-441c-899a-4066c5c44efc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779460141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1779460141
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.858383595
Short name T867
Test name
Test status
Simulation time 221102468 ps
CPU time 1 seconds
Started Mar 31 12:29:15 PM PDT 24
Finished Mar 31 12:29:17 PM PDT 24
Peak memory 198460 kb
Host smart-04afd781-b81a-443a-a5a9-f35d058b3ba8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=858383595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.858383595
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.636664667
Short name T894
Test name
Test status
Simulation time 37863039 ps
CPU time 1.03 seconds
Started Mar 31 12:28:38 PM PDT 24
Finished Mar 31 12:28:39 PM PDT 24
Peak memory 198612 kb
Host smart-9bdeca22-2cb2-40a5-8c6d-405680a02fda
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636664667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.636664667
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.75135923
Short name T926
Test name
Test status
Simulation time 94869483 ps
CPU time 1.31 seconds
Started Mar 31 12:28:03 PM PDT 24
Finished Mar 31 12:28:04 PM PDT 24
Peak memory 192156 kb
Host smart-da564efc-0c4f-47ed-a45b-faf745b6c1f6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=75135923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.75135923
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1308657923
Short name T899
Test name
Test status
Simulation time 131107128 ps
CPU time 1.24 seconds
Started Mar 31 12:28:33 PM PDT 24
Finished Mar 31 12:28:35 PM PDT 24
Peak memory 198328 kb
Host smart-cf86fe1f-a426-415f-adb8-56d945ddfe78
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308657923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1308657923
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.4197197926
Short name T876
Test name
Test status
Simulation time 191580719 ps
CPU time 0.99 seconds
Started Mar 31 12:28:38 PM PDT 24
Finished Mar 31 12:28:39 PM PDT 24
Peak memory 192312 kb
Host smart-3f2bafac-f1e2-457b-a3ac-42557528ab63
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4197197926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.4197197926
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1096968494
Short name T912
Test name
Test status
Simulation time 35472484 ps
CPU time 1.03 seconds
Started Mar 31 12:28:33 PM PDT 24
Finished Mar 31 12:28:34 PM PDT 24
Peak memory 192396 kb
Host smart-8b233f0c-abc5-4e59-80bc-b37d2c6c77c2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096968494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1096968494
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2161975679
Short name T924
Test name
Test status
Simulation time 142919307 ps
CPU time 1.02 seconds
Started Mar 31 12:27:54 PM PDT 24
Finished Mar 31 12:28:05 PM PDT 24
Peak memory 198508 kb
Host smart-4ffd4c21-6295-422a-8f72-264e94149a61
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2161975679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.2161975679
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.854068191
Short name T848
Test name
Test status
Simulation time 36929993 ps
CPU time 0.9 seconds
Started Mar 31 12:28:00 PM PDT 24
Finished Mar 31 12:28:01 PM PDT 24
Peak memory 196768 kb
Host smart-afd0dd1e-75de-4872-9fde-c9f2a18036ec
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854068191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.854068191
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1641807349
Short name T890
Test name
Test status
Simulation time 83511903 ps
CPU time 0.78 seconds
Started Mar 31 12:28:59 PM PDT 24
Finished Mar 31 12:29:01 PM PDT 24
Peak memory 191268 kb
Host smart-4ada9196-cc26-4f02-8f1f-d4ea7b723c64
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1641807349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.1641807349
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3043997662
Short name T857
Test name
Test status
Simulation time 88530594 ps
CPU time 1.44 seconds
Started Mar 31 12:28:28 PM PDT 24
Finished Mar 31 12:28:29 PM PDT 24
Peak memory 192200 kb
Host smart-6529b48c-30b5-4c3e-83bb-44efbe21022f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043997662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3043997662
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1561886067
Short name T929
Test name
Test status
Simulation time 106736006 ps
CPU time 0.97 seconds
Started Mar 31 12:28:01 PM PDT 24
Finished Mar 31 12:28:02 PM PDT 24
Peak memory 192196 kb
Host smart-9c97f2f2-59ff-4445-9727-a869d85d9243
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1561886067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.1561886067
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.216884174
Short name T860
Test name
Test status
Simulation time 43634943 ps
CPU time 0.98 seconds
Started Mar 31 12:28:19 PM PDT 24
Finished Mar 31 12:28:20 PM PDT 24
Peak memory 192168 kb
Host smart-f874f248-b4df-4e74-934f-641d09602651
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216884174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.216884174
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1911470142
Short name T886
Test name
Test status
Simulation time 210599227 ps
CPU time 1.31 seconds
Started Mar 31 12:27:49 PM PDT 24
Finished Mar 31 12:27:51 PM PDT 24
Peak memory 192164 kb
Host smart-e4fec04f-68e0-47f9-b0b9-d394f1e2f6e4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1911470142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.1911470142
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2098125899
Short name T913
Test name
Test status
Simulation time 131619597 ps
CPU time 1.11 seconds
Started Mar 31 12:28:26 PM PDT 24
Finished Mar 31 12:28:28 PM PDT 24
Peak memory 196964 kb
Host smart-c74c47f6-507d-4910-abcf-5d78c47c27f0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098125899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2098125899
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1680396281
Short name T910
Test name
Test status
Simulation time 56174796 ps
CPU time 0.97 seconds
Started Mar 31 12:28:13 PM PDT 24
Finished Mar 31 12:28:19 PM PDT 24
Peak memory 197972 kb
Host smart-78d125f2-f0f0-4069-be81-982e43f212e2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1680396281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.1680396281
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.958421813
Short name T873
Test name
Test status
Simulation time 360747865 ps
CPU time 1.09 seconds
Started Mar 31 12:28:24 PM PDT 24
Finished Mar 31 12:28:25 PM PDT 24
Peak memory 192220 kb
Host smart-1e354a66-501b-46f8-9d0b-96c2d1156ecd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958421813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.958421813
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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