Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3143420	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

13520371

1

T23

119

T24

179

T25

2990

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	6784355	1			T23	78		T24	38		T25	1819
values[0x0]	4864373	1			T23	42		T24	76		T25	1034
values[0x1]	5015063	1			T23	39		T24	80		T25	1020

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2429283	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

14234508

1

T23

130

T24

184

T25

3174

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	57192	1			T26	1		T28	6		T30	3
valid_sources[0x01]	59911	1			T24	1		T28	4		T30	8
valid_sources[0x02]	56827	1			T24	1		T28	7		T29	20
valid_sources[0x03]	59025	1			T24	1		T26	3		T28	6
valid_sources[0x04]	57283	1			T24	1		T26	2		T28	12
valid_sources[0x05]	55373	1			T26	3		T28	11		T30	11
valid_sources[0x06]	62512	1			T24	1		T26	1		T28	6
valid_sources[0x07]	62657	1			T24	2		T28	12		T30	1
valid_sources[0x08]	59915	1			T26	2		T28	9		T30	2
valid_sources[0x09]	61018	1			T26	4		T28	8		T32	4
valid_sources[0x0a]	56157	1			T24	1		T26	2		T28	6
valid_sources[0x0b]	57324	1			T24	2		T26	2		T28	6
valid_sources[0x0c]	63189	1			T26	7		T28	5		T30	2
valid_sources[0x0d]	58714	1			T26	2		T28	10		T29	4
valid_sources[0x0e]	56109	1			T24	1		T26	3		T28	13
valid_sources[0x0f]	58798	1			T24	2		T28	12		T30	1
valid_sources[0x10]	56277	1			T24	1		T28	9		T34	6
valid_sources[0x11]	56993	1			T26	1		T28	11		T29	1
valid_sources[0x12]	64633	1			T24	1		T26	2		T28	9
valid_sources[0x13]	59051	1			T26	1		T28	8		T32	11
valid_sources[0x14]	67816	1			T26	3		T28	12		T30	2
valid_sources[0x15]	60292	1			T26	1		T28	6		T30	1
valid_sources[0x16]	56433	1			T28	12		T30	2		T34	6
valid_sources[0x17]	59855	1			T24	1		T28	10		T30	3
valid_sources[0x18]	57643	1			T24	2		T28	3		T30	8
valid_sources[0x19]	62380	1			T24	2		T28	12		T32	3
valid_sources[0x1a]	65128	1			T24	2		T28	7		T32	1
valid_sources[0x1b]	57272	1			T28	5		T32	3		T34	5
valid_sources[0x1c]	58027	1			T26	4		T28	7		T30	5
valid_sources[0x1d]	59410	1			T26	1		T28	7		T30	1
valid_sources[0x1e]	64739	1			T24	3		T26	2		T28	4
valid_sources[0x1f]	57722	1			T26	1		T28	9		T32	1
valid_sources[0x20]	60839	1			T26	1		T28	2		T30	4
valid_sources[0x21]	57263	1			T24	2		T26	1		T28	6
valid_sources[0x22]	57614	1			T26	1		T28	7		T34	2
valid_sources[0x23]	65038	1			T24	1		T28	9		T30	1
valid_sources[0x24]	56875	1			T28	6		T32	3		T34	7
valid_sources[0x25]	60260	1			T24	1		T26	1		T28	2
valid_sources[0x26]	60129	1			T24	2		T28	4		T30	2
valid_sources[0x27]	59263	1			T28	11		T30	3		T32	2
valid_sources[0x28]	59265	1			T24	1		T26	2		T28	6
valid_sources[0x29]	147099	1			T24	1		T28	10		T30	4
valid_sources[0x2a]	58471	1			T28	7		T29	27		T30	5
valid_sources[0x2b]	61700	1			T26	1		T28	13		T30	4
valid_sources[0x2c]	58011	1			T26	1		T28	9		T30	2
valid_sources[0x2d]	62033	1			T26	2		T28	5		T30	1
valid_sources[0x2e]	60703	1			T26	1		T28	5		T30	1
valid_sources[0x2f]	66544	1			T24	1		T28	8		T32	2
valid_sources[0x30]	57359	1			T24	1		T28	6		T32	2
valid_sources[0x31]	58010	1			T24	1		T28	11		T30	3
valid_sources[0x32]	57626	1			T24	1		T26	1		T28	11
valid_sources[0x33]	57151	1			T24	1		T26	1		T28	6
valid_sources[0x34]	60034	1			T26	1		T28	7		T32	3
valid_sources[0x35]	59721	1			T28	3		T31	11		T32	5
valid_sources[0x36]	58604	1			T24	1		T28	5		T34	6
valid_sources[0x37]	56227	1			T24	4		T28	7		T30	1
valid_sources[0x38]	59598	1			T24	1		T28	6		T30	1
valid_sources[0x39]	57443	1			T28	11		T32	4		T34	10
valid_sources[0x3a]	56806	1			T26	2		T28	11		T30	1
valid_sources[0x3b]	60492	1			T24	3		T28	13		T32	4
valid_sources[0x3c]	61679	1			T26	1		T28	6		T29	1
valid_sources[0x3d]	57976	1			T24	1		T28	7		T34	10
valid_sources[0x3e]	59041	1			T24	2		T28	8		T30	3
valid_sources[0x3f]	60105	1			T24	1		T28	6		T29	4
valid_sources[0x40]	57537	1			T26	1		T28	8		T30	10
valid_sources[0x41]	56231	1			T24	1		T26	1		T28	10
valid_sources[0x42]	59784	1			T28	12		T32	4		T34	11
valid_sources[0x43]	125604	1			T24	1		T28	8		T30	8
valid_sources[0x44]	59529	1			T24	1		T26	1		T28	6
valid_sources[0x45]	63803	1			T24	2		T28	7		T30	4
valid_sources[0x46]	65223	1			T28	4		T30	2		T32	9
valid_sources[0x47]	61124	1			T28	11		T30	1		T32	4
valid_sources[0x48]	61032	1			T26	3		T28	11		T29	1
valid_sources[0x49]	58143	1			T28	8		T29	1		T34	6
valid_sources[0x4a]	58796	1			T26	1		T28	7		T32	2
valid_sources[0x4b]	57089	1			T26	3		T28	10		T30	9
valid_sources[0x4c]	61226	1			T24	1		T26	1		T28	7
valid_sources[0x4d]	56334	1			T24	2		T28	7		T30	4
valid_sources[0x4e]	89096	1			T24	1		T26	2		T28	11
valid_sources[0x4f]	159783	1			T24	2		T28	8		T34	4
valid_sources[0x50]	57172	1			T24	1		T26	2		T28	4
valid_sources[0x51]	58752	1			T24	1		T26	3		T28	6
valid_sources[0x52]	58721	1			T26	4		T28	13		T30	2
valid_sources[0x53]	64231	1			T28	4		T30	1		T31	3
valid_sources[0x54]	60853	1			T28	8		T30	4		T31	1
valid_sources[0x55]	59806	1			T26	4		T28	3		T30	1
valid_sources[0x56]	60774	1			T28	6		T30	1		T32	6
valid_sources[0x57]	58509	1			T24	1		T26	3		T28	10
valid_sources[0x58]	56486	1			T28	9		T30	6		T32	2
valid_sources[0x59]	59226	1			T24	2		T26	2		T28	9
valid_sources[0x5a]	60762	1			T26	1		T28	10		T30	6
valid_sources[0x5b]	60899	1			T26	2		T28	6		T29	6
valid_sources[0x5c]	61836	1			T24	1		T28	5		T32	4
valid_sources[0x5d]	57464	1			T26	3		T28	14		T30	1
valid_sources[0x5e]	57678	1			T26	3		T28	7		T29	2
valid_sources[0x5f]	56579	1			T24	1		T26	3		T28	12
valid_sources[0x60]	60718	1			T24	1		T28	6		T30	1
valid_sources[0x61]	56388	1			T24	1		T28	10		T32	1
valid_sources[0x62]	56365	1			T26	4		T28	13		T32	4
valid_sources[0x63]	56157	1			T24	2		T28	7		T32	1
valid_sources[0x64]	57677	1			T24	2		T28	7		T30	2
valid_sources[0x65]	56184	1			T26	4		T28	4		T29	2
valid_sources[0x66]	55513	1			T26	1		T28	14		T32	2
valid_sources[0x67]	58982	1			T26	3		T28	2		T32	5
valid_sources[0x68]	57693	1			T28	11		T32	7		T34	3
valid_sources[0x69]	59180	1			T24	2		T26	3		T28	9
valid_sources[0x6a]	133578	1			T24	1		T28	9		T30	3
valid_sources[0x6b]	56734	1			T24	2		T26	1		T28	5
valid_sources[0x6c]	56955	1			T24	3		T28	7		T30	2
valid_sources[0x6d]	60515	1			T25	3873		T28	6		T30	3
valid_sources[0x6e]	64071	1			T26	3		T28	8		T30	4
valid_sources[0x6f]	55544	1			T24	3		T26	2		T28	5
valid_sources[0x70]	56387	1			T24	1		T26	4		T28	10
valid_sources[0x71]	59177	1			T28	6		T29	6		T32	2
valid_sources[0x72]	98419	1			T26	2		T28	8		T29	3
valid_sources[0x73]	80008	1			T24	2		T26	2		T28	5
valid_sources[0x74]	63853	1			T24	1		T28	11		T29	10
valid_sources[0x75]	60093	1			T24	1		T26	6		T28	10
valid_sources[0x76]	59952	1			T24	2		T26	1		T28	2
valid_sources[0x77]	56658	1			T28	9		T30	1		T31	3
valid_sources[0x78]	56984	1			T26	3		T28	11		T32	4
valid_sources[0x79]	59672	1			T28	12		T30	7		T32	1
valid_sources[0x7a]	59084	1			T24	1		T26	3		T28	12
valid_sources[0x7b]	57466	1			T28	7		T32	1		T34	7
valid_sources[0x7c]	61453	1			T24	1		T28	8		T30	2
valid_sources[0x7d]	61392	1			T24	1		T26	5		T28	4
valid_sources[0x7e]	56358	1			T23	159		T24	1		T28	4
valid_sources[0x7f]	56324	1			T28	7		T30	1		T32	5
valid_sources[0x80]	58246	1			T26	1		T28	6		T30	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3824697

1

T23

38

T24

23

T25

936

values[0x0]

all_enables

biggest_size

4848819

1

T23

42

T24

76

T25

1034

values[0x1]

all_enables

biggest_size

4846855

1

T23

39

T24

80

T25

1020