Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	132183783	0	0	0
ctrl_en_input_filter_rd_A	132183783	63096	0	0
intr_ctrl_en_falling_rd_A	132183783	65157	0	0
intr_ctrl_en_lvlhigh_rd_A	132183783	64438	0	0
intr_ctrl_en_lvllow_rd_A	132183783	63435	0	0
intr_ctrl_en_rising_rd_A	132183783	63618	0	0
intr_enable_rd_A	132183783	64586	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132183783	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132183783	63096	0	0
T1	44257	265	0	0
T2	0	2848	0	0
T3	0	1	0	0
T4	0	46	0	0
T5	0	3685	0	0
T6	0	202	0	0
T7	0	4416	0	0
T8	0	5	0	0
T9	0	4	0	0
T10	0	166	0	0
T11	155539	0	0	0
T12	4879	0	0	0
T13	5469	0	0	0
T14	5778	0	0	0
T15	4612	0	0	0
T16	5266	0	0	0
T17	328941	0	0	0
T18	30096	0	0	0
T19	51597	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132183783	65157	0	0
T1	44257	190	0	0
T2	0	3076	0	0
T3	0	3	0	0
T4	0	70	0	0
T5	0	3720	0	0
T6	0	224	0	0
T7	0	4698	0	0
T9	0	7	0	0
T10	0	202	0	0
T11	155539	0	0	0
T12	4879	0	0	0
T13	5469	0	0	0
T14	5778	0	0	0
T15	4612	0	0	0
T16	5266	0	0	0
T17	328941	0	0	0
T18	30096	0	0	0
T19	51597	0	0	0
T20	0	4	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132183783	64438	0	0
T1	44257	231	0	0
T2	0	2934	0	0
T3	0	2	0	0
T4	0	70	0	0
T5	0	3852	0	0
T6	0	200	0	0
T7	0	4651	0	0
T9	0	9	0	0
T10	0	183	0	0
T11	155539	0	0	0
T12	4879	0	0	0
T13	5469	0	0	0
T14	5778	0	0	0
T15	4612	0	0	0
T16	5266	0	0	0
T17	328941	0	0	0
T18	30096	0	0	0
T19	51597	0	0	0
T20	0	29	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132183783	63435	0	0
T1	44257	286	0	0
T2	0	3047	0	0
T4	0	87	0	0
T5	0	3632	0	0
T6	0	187	0	0
T7	0	4496	0	0
T9	0	7	0	0
T10	0	165	0	0
T11	155539	0	0	0
T12	4879	0	0	0
T13	5469	0	0	0
T14	5778	0	0	0
T15	4612	0	0	0
T16	5266	0	0	0
T17	328941	0	0	0
T18	30096	0	0	0
T19	51597	0	0	0
T20	0	10	0	0
T21	0	6270	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132183783	63618	0	0
T1	44257	296	0	0
T2	0	2883	0	0
T3	0	13	0	0
T4	0	20	0	0
T5	0	3658	0	0
T6	0	259	0	0
T7	0	4849	0	0
T9	0	1	0	0
T10	0	178	0	0
T11	155539	0	0	0
T12	4879	0	0	0
T13	5469	0	0	0
T14	5778	0	0	0
T15	4612	0	0	0
T16	5266	0	0	0
T17	328941	0	0	0
T18	30096	0	0	0
T19	51597	0	0	0
T22	0	13	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132183783	64586	0	0
T1	44257	324	0	0
T2	0	3181	0	0
T3	0	6	0	0
T4	0	74	0	0
T5	0	3743	0	0
T6	0	147	0	0
T7	0	4445	0	0
T9	0	2	0	0
T10	0	249	0	0
T11	155539	0	0	0
T12	4879	0	0	0
T13	5469	0	0	0
T14	5778	0	0	0
T15	4612	0	0	0
T16	5266	0	0	0
T17	328941	0	0	0
T18	30096	0	0	0
T19	51597	0	0	0
T22	0	5	0	0