Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4233846	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

19239455

1

T25

593

T26

2666

T1

84

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	9298335	1			T25	272		T26	4192		T1	9
values[0x0]	6960720	1			T25	238		T26	309		T1	38
values[0x1]	7214246	1			T25	237		T26	283		T1	38

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3243064	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

20230237

1

T25

624

T26

3090

T1

84

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	83567	1			T25	1		T26	13		T11	72
valid_sources[0x01]	92546	1			T26	23		T11	73		T2	5
valid_sources[0x02]	95030	1			T25	3		T26	8		T1	2
valid_sources[0x03]	82327	1			T25	3		T11	83		T2	7
valid_sources[0x04]	94297	1			T25	2		T26	2		T11	59
valid_sources[0x05]	125229	1			T25	1		T26	2		T11	77
valid_sources[0x06]	89606	1			T25	3		T26	15		T11	87
valid_sources[0x07]	168963	1			T25	2		T26	9		T11	70
valid_sources[0x08]	126018	1			T25	2		T26	19		T11	85
valid_sources[0x09]	84259	1			T25	2		T11	68		T12	3
valid_sources[0x0a]	82704	1			T25	1		T26	37		T11	86
valid_sources[0x0b]	84870	1			T25	1		T26	19		T11	81
valid_sources[0x0c]	84641	1			T25	2		T26	4		T1	1
valid_sources[0x0d]	77074	1			T25	7		T26	41		T11	84
valid_sources[0x0e]	84972	1			T25	6		T26	51		T11	79
valid_sources[0x0f]	113907	1			T25	2		T26	4		T11	87
valid_sources[0x10]	190081	1			T25	3		T26	6		T1	1
valid_sources[0x11]	87258	1			T25	1		T11	89		T2	3
valid_sources[0x12]	88374	1			T25	4		T26	28		T11	68
valid_sources[0x13]	90299	1			T25	3		T26	11		T11	81
valid_sources[0x14]	87761	1			T25	4		T26	3		T1	3
valid_sources[0x15]	83823	1			T25	2		T26	10		T11	67
valid_sources[0x16]	89744	1			T25	2		T26	22		T11	77
valid_sources[0x17]	83925	1			T25	2		T26	17		T11	74
valid_sources[0x18]	92653	1			T25	2		T26	10		T11	81
valid_sources[0x19]	97115	1			T25	4		T26	25		T11	73
valid_sources[0x1a]	90240	1			T25	2		T26	12		T11	83
valid_sources[0x1b]	95439	1			T25	2		T26	25		T11	78
valid_sources[0x1c]	91635	1			T25	4		T26	48		T11	66
valid_sources[0x1d]	97311	1			T25	4		T26	38		T1	2
valid_sources[0x1e]	91405	1			T25	1		T26	46		T1	1
valid_sources[0x1f]	75614	1			T25	2		T26	4		T1	1
valid_sources[0x20]	95130	1			T26	16		T1	3		T11	73
valid_sources[0x21]	83467	1			T25	3		T26	9		T11	69
valid_sources[0x22]	76905	1			T25	1		T26	38		T1	2
valid_sources[0x23]	85151	1			T25	2		T26	19		T1	2
valid_sources[0x24]	84934	1			T25	2		T26	19		T11	82
valid_sources[0x25]	91707	1			T25	4		T26	15		T11	64
valid_sources[0x26]	95330	1			T25	1		T26	13		T11	89
valid_sources[0x27]	93430	1			T25	3		T26	6		T11	59
valid_sources[0x28]	87795	1			T25	2		T26	15		T1	2
valid_sources[0x29]	83071	1			T25	3		T26	22		T11	78
valid_sources[0x2a]	91892	1			T25	4		T26	17		T11	71
valid_sources[0x2b]	87871	1			T25	3		T26	28		T11	70
valid_sources[0x2c]	97821	1			T25	6		T26	24		T11	81
valid_sources[0x2d]	91577	1			T25	5		T26	29		T11	72
valid_sources[0x2e]	90505	1			T25	1		T26	15		T11	69
valid_sources[0x2f]	83641	1			T25	3		T26	12		T1	1
valid_sources[0x30]	84123	1			T25	1		T11	75		T2	4
valid_sources[0x31]	93431	1			T25	3		T26	74		T11	78
valid_sources[0x32]	83905	1			T25	2		T26	18		T11	62
valid_sources[0x33]	79152	1			T25	3		T26	2		T11	79
valid_sources[0x34]	86950	1			T26	32		T11	68		T2	7
valid_sources[0x35]	87219	1			T25	3		T26	8		T11	58
valid_sources[0x36]	80055	1			T25	2		T26	27		T11	69
valid_sources[0x37]	87248	1			T25	2		T11	95		T2	5
valid_sources[0x38]	87459	1			T25	2		T26	20		T11	81
valid_sources[0x39]	88614	1			T25	7		T26	3		T1	2
valid_sources[0x3a]	171770	1			T25	7		T26	22		T11	72
valid_sources[0x3b]	90164	1			T25	2		T26	10		T11	76
valid_sources[0x3c]	87741	1			T25	7		T26	42		T11	80
valid_sources[0x3d]	95499	1			T25	4		T26	15		T11	76
valid_sources[0x3e]	87381	1			T25	2		T26	39		T11	81
valid_sources[0x3f]	81641	1			T25	2		T26	23		T11	87
valid_sources[0x40]	85899	1			T26	4		T11	76		T2	10
valid_sources[0x41]	84123	1			T25	6		T26	7		T11	75
valid_sources[0x42]	92613	1			T25	4		T26	22		T11	82
valid_sources[0x43]	84573	1			T25	5		T26	7		T11	75
valid_sources[0x44]	89126	1			T25	6		T26	30		T11	86
valid_sources[0x45]	84969	1			T25	1		T26	40		T1	1
valid_sources[0x46]	79454	1			T25	8		T11	86		T2	9
valid_sources[0x47]	80432	1			T25	4		T26	35		T11	69
valid_sources[0x48]	87369	1			T25	7		T26	34		T11	64
valid_sources[0x49]	88224	1			T25	3		T26	16		T11	81
valid_sources[0x4a]	85886	1			T25	6		T26	35		T11	95
valid_sources[0x4b]	86168	1			T25	3		T26	23		T11	73
valid_sources[0x4c]	89310	1			T25	3		T26	17		T1	1
valid_sources[0x4d]	90881	1			T25	7		T26	27		T11	78
valid_sources[0x4e]	85390	1			T25	6		T26	32		T11	64
valid_sources[0x4f]	81572	1			T25	1		T26	27		T1	1
valid_sources[0x50]	95077	1			T25	1		T26	4		T11	82
valid_sources[0x51]	85789	1			T25	4		T26	61		T11	72
valid_sources[0x52]	88043	1			T25	7		T26	7		T11	79
valid_sources[0x53]	81114	1			T26	31		T1	1		T11	82
valid_sources[0x54]	79301	1			T25	4		T26	12		T1	1
valid_sources[0x55]	80935	1			T25	2		T26	11		T11	74
valid_sources[0x56]	88930	1			T26	12		T11	69		T2	11
valid_sources[0x57]	95675	1			T25	9		T26	16		T11	91
valid_sources[0x58]	78961	1			T25	2		T26	21		T1	2
valid_sources[0x59]	81235	1			T25	2		T26	55		T11	63
valid_sources[0x5a]	86021	1			T25	1		T26	36		T1	5
valid_sources[0x5b]	85658	1			T25	2		T26	14		T1	2
valid_sources[0x5c]	98381	1			T25	3		T26	23		T11	87
valid_sources[0x5d]	87988	1			T25	2		T11	70		T2	8
valid_sources[0x5e]	87630	1			T25	1		T26	24		T11	83
valid_sources[0x5f]	174076	1			T25	6		T26	8		T11	73
valid_sources[0x60]	86897	1			T25	4		T26	23		T11	85
valid_sources[0x61]	140001	1			T25	3		T26	31		T11	77
valid_sources[0x62]	84566	1			T25	5		T26	10		T11	52
valid_sources[0x63]	89808	1			T26	5		T11	78		T2	6
valid_sources[0x64]	85263	1			T25	1		T11	69		T2	2
valid_sources[0x65]	87989	1			T25	5		T26	5		T11	73
valid_sources[0x66]	88420	1			T25	4		T26	25		T1	4
valid_sources[0x67]	92552	1			T25	4		T26	19		T1	3
valid_sources[0x68]	91043	1			T25	6		T26	18		T11	68
valid_sources[0x69]	79886	1			T25	4		T26	6		T11	81
valid_sources[0x6a]	83590	1			T25	3		T26	23		T11	70
valid_sources[0x6b]	97423	1			T25	2		T26	59		T11	75
valid_sources[0x6c]	85210	1			T25	1		T11	60		T2	7
valid_sources[0x6d]	92903	1			T25	2		T26	22		T1	4
valid_sources[0x6e]	91350	1			T25	3		T26	48		T11	65
valid_sources[0x6f]	77461	1			T25	2		T26	21		T11	66
valid_sources[0x70]	83537	1			T26	11		T11	72		T2	11
valid_sources[0x71]	88541	1			T25	2		T26	29		T11	70
valid_sources[0x72]	90725	1			T25	8		T26	21		T11	73
valid_sources[0x73]	96640	1			T25	3		T26	65		T11	82
valid_sources[0x74]	80430	1			T26	21		T11	81		T2	6
valid_sources[0x75]	89209	1			T25	3		T26	30		T11	76
valid_sources[0x76]	84122	1			T25	1		T26	16		T11	79
valid_sources[0x77]	79078	1			T25	4		T26	37		T11	79
valid_sources[0x78]	84930	1			T25	3		T26	12		T11	64
valid_sources[0x79]	99911	1			T25	3		T26	10		T11	64
valid_sources[0x7a]	89867	1			T25	1		T26	11		T11	70
valid_sources[0x7b]	88864	1			T25	4		T26	7		T11	74
valid_sources[0x7c]	81937	1			T25	3		T26	4		T11	77
valid_sources[0x7d]	84418	1			T26	6		T11	77		T2	7
valid_sources[0x7e]	92653	1			T25	1		T26	32		T11	77
valid_sources[0x7f]	80652	1			T25	7		T26	8		T11	66
valid_sources[0x80]	84467	1			T25	4		T26	2		T11	84

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5373105

1

T25

118

T26

2074

T1

8

values[0x0]

all_enables

biggest_size

6934736

1

T25

238

T26

309

T1

38

values[0x1]

all_enables

biggest_size

6931614

1

T25

237

T26

283

T1

38