Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	192471282	0	0	0
ctrl_en_input_filter_rd_A	192471282	72269	0	0
intr_ctrl_en_falling_rd_A	192471282	73848	0	0
intr_ctrl_en_lvlhigh_rd_A	192471282	70516	0	0
intr_ctrl_en_lvllow_rd_A	192471282	75020	0	0
intr_ctrl_en_rising_rd_A	192471282	72618	0	0
intr_enable_rd_A	192471282	72666	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192471282	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192471282	72269	0	0
T1	3437	14	0	0
T2	23842	187	0	0
T3	0	3497	0	0
T4	0	147	0	0
T5	0	72	0	0
T6	0	4200	0	0
T7	0	333	0	0
T8	0	1807	0	0
T9	0	125	0	0
T10	0	398	0	0
T11	185788	0	0	0
T12	1734	0	0	0
T13	7547	0	0	0
T14	4034	0	0	0
T15	4137	0	0	0
T16	1509	0	0	0
T17	4912	0	0	0
T18	649564	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192471282	73848	0	0
T2	23842	160	0	0
T3	0	3305	0	0
T4	0	155	0	0
T5	0	58	0	0
T6	0	4041	0	0
T7	0	280	0	0
T8	0	1636	0	0
T9	0	98	0	0
T13	7547	0	0	0
T14	4034	0	0	0
T15	4137	0	0	0
T16	1509	0	0	0
T17	4912	0	0	0
T18	649564	0	0	0
T19	0	3	0	0
T20	0	3	0	0
T21	5405	0	0	0
T22	7936	0	0	0
T23	9691	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192471282	70516	0	0
T1	3437	5	0	0
T2	23842	186	0	0
T3	0	3393	0	0
T4	0	132	0	0
T5	0	23	0	0
T6	0	3794	0	0
T7	0	287	0	0
T8	0	1719	0	0
T11	185788	0	0	0
T12	1734	0	0	0
T13	7547	0	0	0
T14	4034	0	0	0
T15	4137	0	0	0
T16	1509	0	0	0
T17	4912	0	0	0
T18	649564	0	0	0
T20	0	6	0	0
T24	0	1	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192471282	75020	0	0
T2	23842	188	0	0
T3	0	3625	0	0
T4	0	135	0	0
T5	0	46	0	0
T6	0	3905	0	0
T7	0	264	0	0
T8	0	1799	0	0
T9	0	115	0	0
T10	0	395	0	0
T13	7547	0	0	0
T14	4034	0	0	0
T15	4137	0	0	0
T16	1509	0	0	0
T17	4912	0	0	0
T18	649564	0	0	0
T20	0	3	0	0
T21	5405	0	0	0
T22	7936	0	0	0
T23	9691	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192471282	72618	0	0
T2	23842	184	0	0
T3	0	3493	0	0
T4	0	119	0	0
T5	0	41	0	0
T6	0	3836	0	0
T7	0	320	0	0
T8	0	1765	0	0
T9	0	83	0	0
T13	7547	0	0	0
T14	4034	0	0	0
T15	4137	0	0	0
T16	1509	0	0	0
T17	4912	0	0	0
T18	649564	0	0	0
T20	0	4	0	0
T21	5405	0	0	0
T22	7936	0	0	0
T23	9691	0	0	0
T24	0	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192471282	72666	0	0
T2	23842	156	0	0
T3	0	3443	0	0
T4	0	109	0	0
T5	0	25	0	0
T6	0	4078	0	0
T7	0	321	0	0
T8	0	1630	0	0
T9	0	85	0	0
T10	0	446	0	0
T13	7547	0	0	0
T14	4034	0	0	0
T15	4137	0	0	0
T16	1509	0	0	0
T17	4912	0	0	0
T18	649564	0	0	0
T20	0	7	0	0
T21	5405	0	0	0
T22	7936	0	0	0
T23	9691	0	0	0