Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2996934	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

13165731

1

T25

368

T26

916

T27

399

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	6507518	1			T25	85		T26	1116		T27	119
values[0x0]	4749480	1			T25	165		T26	179		T27	167
values[0x1]	4905667	1			T25	159		T26	192		T27	179

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2309670	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

13852995

1

T25

377

T26

1028

T27

407

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	57782	1			T25	2		T26	1		T27	39
valid_sources[0x01]	55367	1			T25	1		T26	9		T29	2
valid_sources[0x02]	67094	1			T25	1		T26	5		T30	6
valid_sources[0x03]	55275	1			T26	3		T29	11		T30	12
valid_sources[0x04]	54484	1			T26	3		T30	8		T32	17
valid_sources[0x05]	63199	1			T25	1		T26	3		T29	4
valid_sources[0x06]	52333	1			T26	6		T27	6		T30	7
valid_sources[0x07]	56866	1			T25	2		T26	2		T27	9
valid_sources[0x08]	57248	1			T25	1		T26	6		T30	3
valid_sources[0x09]	58016	1			T25	3		T26	8		T30	7
valid_sources[0x0a]	57914	1			T25	1		T26	4		T30	5
valid_sources[0x0b]	62776	1			T26	6		T29	3		T30	7
valid_sources[0x0c]	60790	1			T25	1		T26	8		T29	1
valid_sources[0x0d]	65967	1			T25	4		T26	9		T30	7
valid_sources[0x0e]	67642	1			T25	1		T26	4		T29	4
valid_sources[0x0f]	59816	1			T25	1		T26	8		T30	5
valid_sources[0x10]	53369	1			T25	2		T26	7		T29	6
valid_sources[0x11]	57948	1			T25	4		T26	6		T30	14
valid_sources[0x12]	61887	1			T25	3		T26	7		T30	6
valid_sources[0x13]	59323	1			T26	5		T30	11		T32	22
valid_sources[0x14]	63579	1			T25	1		T26	2		T30	9
valid_sources[0x15]	58769	1			T25	1		T26	7		T27	1
valid_sources[0x16]	54788	1			T25	1		T26	8		T30	9
valid_sources[0x17]	62062	1			T25	1		T26	4		T27	15
valid_sources[0x18]	58620	1			T25	1		T26	5		T29	6
valid_sources[0x19]	58566	1			T25	2		T26	2		T30	6
valid_sources[0x1a]	60701	1			T25	1		T26	6		T30	9
valid_sources[0x1b]	57421	1			T25	1		T26	6		T30	10
valid_sources[0x1c]	63281	1			T26	7		T30	8		T31	6
valid_sources[0x1d]	59178	1			T25	3		T26	2		T30	10
valid_sources[0x1e]	59861	1			T25	4		T26	3		T30	11
valid_sources[0x1f]	55237	1			T25	1		T26	4		T30	3
valid_sources[0x20]	61891	1			T25	1		T26	5		T27	8
valid_sources[0x21]	65672	1			T25	3		T26	3		T27	20
valid_sources[0x22]	53791	1			T25	1		T26	5		T29	8
valid_sources[0x23]	68036	1			T25	1		T26	7		T30	5
valid_sources[0x24]	149700	1			T25	1		T26	3		T27	1
valid_sources[0x25]	60070	1			T25	3		T26	7		T27	10
valid_sources[0x26]	55350	1			T26	6		T29	10		T30	4
valid_sources[0x27]	111301	1			T25	1		T26	14		T30	5
valid_sources[0x28]	57047	1			T25	4		T26	6		T30	11
valid_sources[0x29]	58367	1			T25	1		T26	3		T30	8
valid_sources[0x2a]	57997	1			T26	3		T29	2		T30	19
valid_sources[0x2b]	57964	1			T25	3		T26	7		T29	2
valid_sources[0x2c]	57577	1			T25	2		T26	6		T29	3
valid_sources[0x2d]	101088	1			T25	1		T26	3		T30	8
valid_sources[0x2e]	62134	1			T25	2		T26	2		T30	5
valid_sources[0x2f]	60307	1			T25	2		T26	4		T30	5
valid_sources[0x30]	54672	1			T26	5		T29	3		T30	13
valid_sources[0x31]	51888	1			T25	3		T26	8		T29	2
valid_sources[0x32]	61490	1			T25	2		T26	3		T30	10
valid_sources[0x33]	58706	1			T25	3		T26	5		T29	2
valid_sources[0x34]	58888	1			T25	1		T26	3		T30	20
valid_sources[0x35]	53248	1			T25	2		T26	5		T30	9
valid_sources[0x36]	59267	1			T26	5		T27	9		T30	6
valid_sources[0x37]	59029	1			T25	3		T26	5		T30	10
valid_sources[0x38]	58320	1			T25	1		T26	3		T30	11
valid_sources[0x39]	63869	1			T25	2		T26	5		T29	23
valid_sources[0x3a]	57556	1			T26	2		T30	3		T32	25
valid_sources[0x3b]	55694	1			T25	2		T26	5		T29	10
valid_sources[0x3c]	58710	1			T25	1		T26	3		T30	13
valid_sources[0x3d]	70415	1			T25	2		T26	1		T30	3
valid_sources[0x3e]	65777	1			T26	7		T30	2		T32	17
valid_sources[0x3f]	52449	1			T25	1		T26	7		T29	2
valid_sources[0x40]	57705	1			T26	7		T30	6		T32	21
valid_sources[0x41]	52812	1			T25	1		T26	5		T30	7
valid_sources[0x42]	60858	1			T25	3		T26	8		T29	4
valid_sources[0x43]	63485	1			T25	3		T26	7		T30	9
valid_sources[0x44]	57901	1			T25	2		T26	1		T30	6
valid_sources[0x45]	58450	1			T25	2		T26	5		T30	11
valid_sources[0x46]	55508	1			T25	4		T26	12		T30	6
valid_sources[0x47]	56166	1			T25	3		T26	5		T30	6
valid_sources[0x48]	62693	1			T26	8		T27	3		T30	5
valid_sources[0x49]	52471	1			T26	7		T30	2		T31	3
valid_sources[0x4a]	57300	1			T25	2		T26	9		T29	4
valid_sources[0x4b]	57259	1			T25	6		T26	6		T30	6
valid_sources[0x4c]	58874	1			T26	8		T30	7		T32	16
valid_sources[0x4d]	62368	1			T26	6		T27	15		T30	13
valid_sources[0x4e]	58154	1			T25	1		T26	5		T29	12
valid_sources[0x4f]	60481	1			T25	2		T26	3		T30	3
valid_sources[0x50]	53841	1			T25	2		T26	2		T27	2
valid_sources[0x51]	57376	1			T25	1		T26	7		T30	4
valid_sources[0x52]	62606	1			T25	1		T26	7		T27	3
valid_sources[0x53]	58866	1			T25	2		T26	4		T27	14
valid_sources[0x54]	58665	1			T25	3		T26	4		T29	1
valid_sources[0x55]	54651	1			T25	1		T26	3		T29	13
valid_sources[0x56]	65966	1			T26	10		T30	11		T32	13
valid_sources[0x57]	57508	1			T25	4		T26	2		T30	14
valid_sources[0x58]	68996	1			T25	2		T26	6		T27	1
valid_sources[0x59]	62156	1			T26	9		T30	11		T32	15
valid_sources[0x5a]	204277	1			T25	2		T26	4		T29	2
valid_sources[0x5b]	136055	1			T25	3		T26	5		T30	8
valid_sources[0x5c]	58343	1			T26	2		T30	3		T32	24
valid_sources[0x5d]	53528	1			T26	8		T27	6		T30	4
valid_sources[0x5e]	56560	1			T25	1		T26	5		T27	7
valid_sources[0x5f]	58206	1			T25	1		T26	7		T29	5
valid_sources[0x60]	159159	1			T26	6		T29	3		T30	12
valid_sources[0x61]	61331	1			T25	3		T26	3		T32	17
valid_sources[0x62]	59267	1			T26	12		T27	2		T29	3
valid_sources[0x63]	54535	1			T25	3		T26	1		T30	8
valid_sources[0x64]	61636	1			T25	3		T27	1		T30	10
valid_sources[0x65]	57425	1			T25	1		T26	6		T30	8
valid_sources[0x66]	59445	1			T25	2		T26	7		T29	1
valid_sources[0x67]	65059	1			T25	2		T26	4		T29	6
valid_sources[0x68]	56482	1			T25	2		T26	6		T29	2
valid_sources[0x69]	59830	1			T25	1		T26	10		T30	8
valid_sources[0x6a]	57962	1			T25	2		T26	5		T28	17
valid_sources[0x6b]	57853	1			T25	1		T26	4		T29	3
valid_sources[0x6c]	61053	1			T25	2		T26	4		T30	8
valid_sources[0x6d]	53519	1			T25	1		T26	5		T29	4
valid_sources[0x6e]	63005	1			T25	2		T26	6		T30	8
valid_sources[0x6f]	62838	1			T25	2		T26	3		T30	7
valid_sources[0x70]	60376	1			T25	5		T26	10		T29	8
valid_sources[0x71]	55618	1			T25	2		T26	5		T30	5
valid_sources[0x72]	57564	1			T26	12		T27	5		T29	5
valid_sources[0x73]	69018	1			T25	2		T26	5		T30	10
valid_sources[0x74]	61959	1			T25	2		T26	3		T30	7
valid_sources[0x75]	82701	1			T25	3		T26	4		T27	20
valid_sources[0x76]	55935	1			T26	9		T30	10		T31	9
valid_sources[0x77]	56278	1			T25	2		T26	10		T30	10
valid_sources[0x78]	61282	1			T25	2		T26	7		T30	10
valid_sources[0x79]	56595	1			T25	2		T26	10		T30	10
valid_sources[0x7a]	67247	1			T25	1		T26	5		T30	7
valid_sources[0x7b]	53440	1			T26	4		T30	8		T32	28
valid_sources[0x7c]	63778	1			T25	3		T26	6		T29	3
valid_sources[0x7d]	63581	1			T25	1		T26	11		T30	9
valid_sources[0x7e]	52977	1			T25	1		T26	3		T29	2
valid_sources[0x7f]	66429	1			T25	2		T26	1		T29	2
valid_sources[0x80]	58788	1			T25	3		T26	4		T30	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3698679

1

T25

44

T26

545

T27

53

values[0x0]

all_enables

biggest_size

4733487

1

T25

165

T26

179

T27

167

values[0x1]

all_enables

biggest_size

4733565

1

T25

159

T26

192

T27

179