Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	141744000	0	0	0
ctrl_en_input_filter_rd_A	141744000	91636	0	0
intr_ctrl_en_falling_rd_A	141744000	95305	0	0
intr_ctrl_en_lvlhigh_rd_A	141744000	92188	0	0
intr_ctrl_en_lvllow_rd_A	141744000	94299	0	0
intr_ctrl_en_rising_rd_A	141744000	92214	0	0
intr_enable_rd_A	141744000	93208	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141744000	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141744000	91636	0	0
T1	178253	5836	0	0
T2	0	116	0	0
T3	0	1649	0	0
T4	0	2898	0	0
T5	0	8081	0	0
T6	0	114	0	0
T7	0	9	0	0
T8	0	6097	0	0
T9	0	1248	0	0
T10	0	18	0	0
T11	2668	0	0	0
T12	2088	0	0	0
T13	19266	0	0	0
T14	46094	0	0	0
T15	5052	0	0	0
T16	7136	0	0	0
T17	762	0	0	0
T18	4375	0	0	0
T19	26517	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141744000	95305	0	0
T1	178253	5737	0	0
T2	0	178	0	0
T3	0	1595	0	0
T4	0	2963	0	0
T5	0	8292	0	0
T6	0	116	0	0
T8	0	5716	0	0
T9	0	1219	0	0
T11	2668	0	0	0
T12	2088	0	0	0
T13	19266	0	0	0
T14	46094	0	0	0
T15	5052	0	0	0
T16	7136	0	0	0
T17	762	0	0	0
T18	4375	0	0	0
T19	26517	0	0	0
T20	0	1	0	0
T21	0	5	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141744000	92188	0	0
T1	178253	5833	0	0
T2	0	143	0	0
T3	0	1674	0	0
T4	0	2893	0	0
T5	0	8507	0	0
T6	0	119	0	0
T8	0	5740	0	0
T9	0	1234	0	0
T11	2668	0	0	0
T12	2088	0	0	0
T13	19266	0	0	0
T14	46094	0	0	0
T15	5052	0	0	0
T16	7136	0	0	0
T17	762	0	0	0
T18	4375	0	0	0
T19	26517	0	0	0
T20	0	5	0	0
T22	0	1	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141744000	94299	0	0
T1	178253	5855	0	0
T2	0	109	0	0
T3	0	1891	0	0
T4	0	2930	0	0
T5	0	8364	0	0
T6	0	122	0	0
T7	0	2	0	0
T8	0	5921	0	0
T9	0	1109	0	0
T11	2668	0	0	0
T12	2088	0	0	0
T13	19266	0	0	0
T14	46094	0	0	0
T15	5052	0	0	0
T16	7136	0	0	0
T17	762	0	0	0
T18	4375	0	0	0
T19	26517	0	0	0
T21	0	8	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141744000	92214	0	0
T1	178253	5707	0	0
T2	0	138	0	0
T3	0	1735	0	0
T4	0	2843	0	0
T5	0	8720	0	0
T6	0	130	0	0
T8	0	5864	0	0
T9	0	1143	0	0
T11	2668	0	0	0
T12	2088	0	0	0
T13	19266	0	0	0
T14	46094	0	0	0
T15	5052	0	0	0
T16	7136	0	0	0
T17	762	0	0	0
T18	4375	0	0	0
T19	26517	0	0	0
T23	0	183	0	0
T24	0	149	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141744000	93208	0	0
T1	178253	5669	0	0
T2	0	122	0	0
T3	0	1679	0	0
T4	0	2750	0	0
T5	0	8425	0	0
T6	0	114	0	0
T8	0	5587	0	0
T9	0	1408	0	0
T11	2668	0	0	0
T12	2088	0	0	0
T13	19266	0	0	0
T14	46094	0	0	0
T15	5052	0	0	0
T16	7136	0	0	0
T17	762	0	0	0
T18	4375	0	0	0
T19	26517	0	0	0
T20	0	3	0	0
T21	0	8	0	0