Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3015766	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

13932978

1

T23

209

T24

1

T25

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	6672118	1			T23	234		T24	1		T25	1
values[0x0]	5038156	1			T23	48		T24	1		T25	9
values[0x1]	5238470	1			T23	32		T24	5		T25	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2301441	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

14647303

1

T23

232

T24

1

T25

5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	66114	1			T26	7		T29	3		T30	10
valid_sources[0x01]	63715	1			T30	8		T103	1		T34	2199
valid_sources[0x02]	64543	1			T26	5		T29	2		T30	2
valid_sources[0x03]	59788	1			T30	8		T44	2		T34	2293
valid_sources[0x04]	61719	1			T26	4		T30	5		T103	2
valid_sources[0x05]	57697	1			T30	4		T103	1		T44	4
valid_sources[0x06]	62791	1			T26	1		T30	4		T103	3
valid_sources[0x07]	64556	1			T30	14		T31	2		T44	3
valid_sources[0x08]	60971	1			T26	3		T30	5		T31	5
valid_sources[0x09]	55478	1			T23	20		T24	1		T30	5
valid_sources[0x0a]	124446	1			T23	50		T26	1		T30	11
valid_sources[0x0b]	62439	1			T30	4		T103	2		T44	5
valid_sources[0x0c]	63470	1			T29	1		T30	22		T31	3
valid_sources[0x0d]	61749	1			T30	3		T31	1		T103	1
valid_sources[0x0e]	63130	1			T26	3		T29	7		T30	7
valid_sources[0x0f]	58112	1			T30	8		T103	4		T34	2277
valid_sources[0x10]	64257	1			T23	19		T30	2		T103	2
valid_sources[0x11]	61694	1			T30	7		T31	6		T34	2247
valid_sources[0x12]	63224	1			T24	1		T26	8		T29	2
valid_sources[0x13]	61491	1			T29	3		T30	5		T31	1
valid_sources[0x14]	56186	1			T30	9		T103	3		T34	2328
valid_sources[0x15]	177330	1			T26	3		T30	4		T31	1
valid_sources[0x16]	79300	1			T26	1		T30	7		T31	3
valid_sources[0x17]	66744	1			T26	2		T29	1		T30	2
valid_sources[0x18]	65672	1			T26	5		T29	3		T30	10
valid_sources[0x19]	71756	1			T30	16		T31	1		T103	1
valid_sources[0x1a]	70206	1			T30	4		T31	2		T103	2
valid_sources[0x1b]	58946	1			T30	8		T31	9		T53	1
valid_sources[0x1c]	56711	1			T29	2		T30	11		T103	3
valid_sources[0x1d]	61870	1			T26	2		T30	3		T34	2223
valid_sources[0x1e]	62111	1			T30	9		T31	1		T34	2217
valid_sources[0x1f]	59722	1			T30	5		T103	4		T34	2235
valid_sources[0x20]	64201	1			T26	3		T30	2		T33	1
valid_sources[0x21]	59116	1			T23	16		T29	3		T30	5
valid_sources[0x22]	63964	1			T29	2		T30	5		T31	1
valid_sources[0x23]	59831	1			T29	1		T30	6		T31	1
valid_sources[0x24]	65288	1			T26	3		T29	1		T30	4
valid_sources[0x25]	57630	1			T29	5		T30	6		T31	1
valid_sources[0x26]	60279	1			T30	7		T103	8		T33	2
valid_sources[0x27]	73273	1			T29	2		T30	9		T45	3
valid_sources[0x28]	61953	1			T26	2		T29	3		T30	3
valid_sources[0x29]	65909	1			T26	4		T29	2		T30	1
valid_sources[0x2a]	61685	1			T26	1		T30	6		T34	2224
valid_sources[0x2b]	65836	1			T30	5		T44	2		T104	5
valid_sources[0x2c]	58592	1			T29	1		T30	1		T31	2
valid_sources[0x2d]	62970	1			T30	6		T101	3		T34	2171
valid_sources[0x2e]	84912	1			T30	5		T103	1		T105	17
valid_sources[0x2f]	67675	1			T30	9		T31	3		T103	1
valid_sources[0x30]	56585	1			T26	1		T30	3		T44	1
valid_sources[0x31]	58121	1			T29	2		T30	11		T103	3
valid_sources[0x32]	61645	1			T30	6		T31	2		T103	4
valid_sources[0x33]	59795	1			T28	2		T30	11		T103	4
valid_sources[0x34]	58437	1			T26	3		T30	2		T103	1
valid_sources[0x35]	59473	1			T26	2		T29	1		T30	9
valid_sources[0x36]	66139	1			T26	2		T30	6		T31	1
valid_sources[0x37]	60794	1			T30	9		T103	5		T34	2231
valid_sources[0x38]	59014	1			T23	18		T26	1		T30	5
valid_sources[0x39]	83413	1			T30	4		T31	2		T103	2
valid_sources[0x3a]	62274	1			T29	2		T30	5		T103	4
valid_sources[0x3b]	58819	1			T30	14		T103	2		T33	2
valid_sources[0x3c]	61471	1			T30	8		T103	3		T44	1
valid_sources[0x3d]	65415	1			T26	1		T30	4		T103	1
valid_sources[0x3e]	65612	1			T26	1		T29	1		T30	13
valid_sources[0x3f]	61023	1			T24	1		T26	1		T29	2
valid_sources[0x40]	59553	1			T26	5		T29	3		T30	2
valid_sources[0x41]	60128	1			T30	5		T31	1		T103	2
valid_sources[0x42]	60368	1			T26	1		T29	2		T30	9
valid_sources[0x43]	59415	1			T30	9		T31	3		T103	1
valid_sources[0x44]	67290	1			T30	4		T31	3		T44	2
valid_sources[0x45]	58718	1			T23	32		T30	17		T103	1
valid_sources[0x46]	55554	1			T26	1		T29	1		T30	3
valid_sources[0x47]	63614	1			T26	2		T29	2		T30	7
valid_sources[0x48]	62210	1			T26	6		T30	2		T103	4
valid_sources[0x49]	58525	1			T30	7		T103	3		T34	2383
valid_sources[0x4a]	63227	1			T30	5		T103	3		T34	2288
valid_sources[0x4b]	62107	1			T26	2		T30	3		T31	4
valid_sources[0x4c]	64839	1			T26	1		T30	4		T103	3
valid_sources[0x4d]	64253	1			T30	3		T31	1		T53	1
valid_sources[0x4e]	65268	1			T26	7		T30	4		T31	3
valid_sources[0x4f]	64632	1			T26	2		T29	3		T30	7
valid_sources[0x50]	59344	1			T26	7		T30	7		T34	2320
valid_sources[0x51]	56336	1			T26	1		T28	1		T29	3
valid_sources[0x52]	68169	1			T26	3		T30	8		T103	2
valid_sources[0x53]	61321	1			T30	7		T34	2324		T58	1
valid_sources[0x54]	59564	1			T30	8		T34	2247		T58	2
valid_sources[0x55]	65068	1			T26	1		T29	3		T30	6
valid_sources[0x56]	62075	1			T26	4		T29	2		T30	4
valid_sources[0x57]	59611	1			T26	2		T30	1		T31	1
valid_sources[0x58]	61095	1			T26	3		T28	1		T30	6
valid_sources[0x59]	64990	1			T26	3		T30	6		T31	2
valid_sources[0x5a]	62794	1			T26	2		T30	1		T103	2
valid_sources[0x5b]	60955	1			T26	4		T30	10		T103	5
valid_sources[0x5c]	63549	1			T29	2		T30	10		T31	2
valid_sources[0x5d]	57850	1			T26	2		T30	3		T31	2
valid_sources[0x5e]	61322	1			T30	3		T34	2188		T35	1480
valid_sources[0x5f]	60433	1			T28	1		T30	4		T31	3
valid_sources[0x60]	67852	1			T26	1		T30	7		T103	2
valid_sources[0x61]	59143	1			T30	7		T32	129		T103	3
valid_sources[0x62]	61490	1			T26	3		T27	195		T30	5
valid_sources[0x63]	60020	1			T29	9		T30	1		T31	1
valid_sources[0x64]	71055	1			T30	10		T103	1		T33	1
valid_sources[0x65]	121364	1			T26	1		T29	4		T30	7
valid_sources[0x66]	65635	1			T26	1		T29	3		T30	4
valid_sources[0x67]	62412	1			T26	3		T30	10		T103	2
valid_sources[0x68]	57185	1			T26	2		T29	4		T30	11
valid_sources[0x69]	64449	1			T23	2		T29	1		T30	7
valid_sources[0x6a]	64793	1			T26	4		T30	2		T31	1
valid_sources[0x6b]	60704	1			T29	2		T30	2		T31	1
valid_sources[0x6c]	61144	1			T26	5		T29	1		T30	8
valid_sources[0x6d]	63989	1			T26	1		T29	4		T30	13
valid_sources[0x6e]	59710	1			T23	29		T26	1		T29	1
valid_sources[0x6f]	62190	1			T26	1		T30	7		T31	3
valid_sources[0x70]	61505	1			T26	1		T30	6		T103	1
valid_sources[0x71]	57568	1			T26	2		T30	3		T31	2
valid_sources[0x72]	181136	1			T23	5		T26	2		T30	6
valid_sources[0x73]	58861	1			T30	7		T103	2		T34	2182
valid_sources[0x74]	57551	1			T26	2		T30	5		T31	3
valid_sources[0x75]	121086	1			T25	20		T29	5		T30	5
valid_sources[0x76]	66131	1			T30	13		T103	1		T34	2234
valid_sources[0x77]	58793	1			T30	8		T31	1		T103	1
valid_sources[0x78]	61048	1			T26	5		T30	9		T31	1
valid_sources[0x79]	59390	1			T29	2		T30	5		T103	1
valid_sources[0x7a]	63591	1			T30	4		T53	1		T34	2219
valid_sources[0x7b]	70112	1			T30	1		T31	1		T103	2
valid_sources[0x7c]	60733	1			T26	4		T29	1		T30	11
valid_sources[0x7d]	63481	1			T30	13		T31	1		T103	2
valid_sources[0x7e]	57577	1			T26	1		T30	1		T31	3
valid_sources[0x7f]	62098	1			T26	2		T30	11		T31	1
valid_sources[0x80]	61261	1			T30	4		T44	1		T53	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3896692

1

T23

129

T24

1

T26

38

values[0x0]

all_enables

biggest_size

5018172

1

T23

48

T25

4

T26

143

values[0x1]

all_enables

biggest_size

5018114

1

T23

32

T25

1

T26

157