Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	160535077	0	0	0
ctrl_en_input_filter_rd_A	160535077	53208	0	0
intr_ctrl_en_falling_rd_A	160535077	52893	0	0
intr_ctrl_en_lvlhigh_rd_A	160535077	51813	0	0
intr_ctrl_en_lvllow_rd_A	160535077	54024	0	0
intr_ctrl_en_rising_rd_A	160535077	52223	0	0
intr_enable_rd_A	160535077	51369	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160535077	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160535077	53208	0	0
T1	40516	261	0	0
T2	0	2539	0	0
T3	0	4331	0	0
T4	0	328	0	0
T5	0	147	0	0
T6	0	6	0	0
T7	0	2062	0	0
T8	0	141	0	0
T9	0	318	0	0
T10	0	102	0	0
T11	8430	0	0	0
T12	4444	0	0	0
T13	8320	0	0	0
T14	2110	0	0	0
T15	936	0	0	0
T16	18117	0	0	0
T17	3004	0	0	0
T18	6444	0	0	0
T19	7766	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160535077	52893	0	0
T1	40516	233	0	0
T2	0	2611	0	0
T3	0	4265	0	0
T4	0	269	0	0
T5	0	141	0	0
T6	0	3	0	0
T7	0	1899	0	0
T8	0	62	0	0
T9	0	307	0	0
T11	8430	0	0	0
T12	4444	0	0	0
T13	8320	0	0	0
T14	2110	0	0	0
T15	936	0	0	0
T16	18117	0	0	0
T17	3004	0	0	0
T18	6444	0	0	0
T19	7766	0	0	0
T20	0	6	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160535077	51813	0	0
T1	40516	241	0	0
T2	0	2365	0	0
T3	0	4299	0	0
T4	0	349	0	0
T5	0	179	0	0
T7	0	1942	0	0
T8	0	98	0	0
T9	0	308	0	0
T10	0	70	0	0
T11	8430	0	0	0
T12	4444	0	0	0
T13	8320	0	0	0
T14	2110	0	0	0
T15	936	0	0	0
T16	18117	0	0	0
T17	3004	0	0	0
T18	6444	0	0	0
T19	7766	0	0	0
T21	0	5416	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160535077	54024	0	0
T1	40516	222	0	0
T2	0	2413	0	0
T3	0	4101	0	0
T4	0	369	0	0
T5	0	154	0	0
T6	0	14	0	0
T7	0	2113	0	0
T8	0	124	0	0
T9	0	340	0	0
T11	8430	0	0	0
T12	4444	0	0	0
T13	8320	0	0	0
T14	2110	0	0	0
T15	936	0	0	0
T16	18117	0	0	0
T17	3004	0	0	0
T18	6444	0	0	0
T19	7766	0	0	0
T22	0	12	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160535077	52223	0	0
T1	40516	205	0	0
T2	0	2447	0	0
T3	0	4351	0	0
T4	0	313	0	0
T5	0	190	0	0
T7	0	1998	0	0
T8	0	181	0	0
T9	0	310	0	0
T10	0	106	0	0
T11	8430	0	0	0
T12	4444	0	0	0
T13	8320	0	0	0
T14	2110	0	0	0
T15	936	0	0	0
T16	18117	0	0	0
T17	3004	0	0	0
T18	6444	0	0	0
T19	7766	0	0	0
T22	0	17	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160535077	51369	0	0
T1	40516	174	0	0
T2	0	2417	0	0
T3	0	4112	0	0
T4	0	364	0	0
T5	0	95	0	0
T6	0	8	0	0
T7	0	1991	0	0
T8	0	162	0	0
T9	0	263	0	0
T11	8430	0	0	0
T12	4444	0	0	0
T13	8320	0	0	0
T14	2110	0	0	0
T15	936	0	0	0
T16	18117	0	0	0
T17	3004	0	0	0
T18	6444	0	0	0
T19	7766	0	0	0
T20	0	13	0	0