Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3582448	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

15641655

1

T21

295

T22

179

T23

169

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7751112	1			T21	173		T22	42		T23	108
values[0x0]	5646429	1			T21	105		T22	79		T23	54
values[0x1]	5826562	1			T21	101		T22	83		T23	62

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2765361	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

16458742

1

T21

307

T22

185

T23

179

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	62819	1			T26	1		T28	5		T32	496
valid_sources[0x01]	108497	1			T22	1		T25	1		T28	10
valid_sources[0x02]	71240	1			T22	2		T23	1		T26	20
valid_sources[0x03]	69031	1			T26	11		T28	9		T32	519
valid_sources[0x04]	63262	1			T22	1		T25	3		T28	10
valid_sources[0x05]	65202	1			T22	3		T25	1		T26	18
valid_sources[0x06]	65623	1			T25	2		T26	8		T28	11
valid_sources[0x07]	66612	1			T26	3		T28	6		T32	520
valid_sources[0x08]	66813	1			T23	3		T26	5		T28	7
valid_sources[0x09]	68657	1			T22	3		T25	1		T26	3
valid_sources[0x0a]	60976	1			T26	3		T28	9		T53	3
valid_sources[0x0b]	72989	1			T22	1		T25	1		T26	4
valid_sources[0x0c]	66812	1			T25	1		T28	10		T32	579
valid_sources[0x0d]	72374	1			T28	10		T32	483		T33	100
valid_sources[0x0e]	69716	1			T22	1		T26	3		T28	15
valid_sources[0x0f]	68303	1			T26	8		T28	6		T32	514
valid_sources[0x10]	76833	1			T25	1		T26	3		T28	8
valid_sources[0x11]	69843	1			T22	1		T25	3		T26	8
valid_sources[0x12]	73233	1			T25	3		T28	12		T32	542
valid_sources[0x13]	74179	1			T23	9		T26	3		T28	11
valid_sources[0x14]	63009	1			T22	1		T26	25		T28	13
valid_sources[0x15]	71162	1			T26	15		T28	12		T32	548
valid_sources[0x16]	80638	1			T28	6		T32	553		T33	77
valid_sources[0x17]	65113	1			T26	8		T28	9		T32	502
valid_sources[0x18]	68018	1			T22	5		T25	1		T26	6
valid_sources[0x19]	67539	1			T22	2		T25	1		T28	11
valid_sources[0x1a]	81133	1			T26	9		T28	11		T32	524
valid_sources[0x1b]	67604	1			T22	1		T26	10		T28	11
valid_sources[0x1c]	67656	1			T23	3		T26	11		T28	12
valid_sources[0x1d]	67249	1			T22	2		T25	1		T28	8
valid_sources[0x1e]	69589	1			T28	11		T32	533		T33	75
valid_sources[0x1f]	68462	1			T25	1		T26	6		T28	3
valid_sources[0x20]	65771	1			T25	4		T28	12		T53	4
valid_sources[0x21]	72097	1			T22	3		T25	1		T26	1
valid_sources[0x22]	67699	1			T22	2		T25	3		T26	6
valid_sources[0x23]	65940	1			T21	379		T22	1		T25	3
valid_sources[0x24]	61971	1			T22	1		T26	5		T28	14
valid_sources[0x25]	66349	1			T26	13		T28	13		T32	544
valid_sources[0x26]	61744	1			T25	1		T26	3		T28	8
valid_sources[0x27]	67539	1			T22	2		T23	2		T25	1
valid_sources[0x28]	73397	1			T25	1		T26	4		T28	8
valid_sources[0x29]	68287	1			T22	1		T25	2		T26	5
valid_sources[0x2a]	69854	1			T23	3		T28	11		T32	538
valid_sources[0x2b]	74789	1			T22	1		T23	6		T25	1
valid_sources[0x2c]	67668	1			T22	2		T25	1		T26	5
valid_sources[0x2d]	119005	1			T26	3		T28	10		T53	4
valid_sources[0x2e]	58596	1			T22	1		T26	1		T28	1
valid_sources[0x2f]	59484	1			T22	1		T23	7		T26	2
valid_sources[0x30]	100775	1			T22	2		T23	2		T26	2
valid_sources[0x31]	72806	1			T25	2		T26	5		T28	15
valid_sources[0x32]	65376	1			T25	4		T26	6		T28	5
valid_sources[0x33]	73987	1			T25	1		T28	9		T53	2
valid_sources[0x34]	68696	1			T22	3		T25	2		T26	1
valid_sources[0x35]	62897	1			T22	2		T23	9		T25	2
valid_sources[0x36]	64675	1			T25	1		T26	14		T28	10
valid_sources[0x37]	65885	1			T22	1		T26	7		T28	13
valid_sources[0x38]	63519	1			T23	11		T26	4		T28	9
valid_sources[0x39]	69835	1			T25	1		T26	1		T28	10
valid_sources[0x3a]	71127	1			T22	2		T26	5		T28	12
valid_sources[0x3b]	58304	1			T23	6		T28	3		T32	519
valid_sources[0x3c]	62144	1			T23	4		T25	1		T26	10
valid_sources[0x3d]	72106	1			T25	2		T26	2		T28	6
valid_sources[0x3e]	63747	1			T25	1		T26	1		T28	6
valid_sources[0x3f]	62094	1			T26	5		T28	12		T32	532
valid_sources[0x40]	77426	1			T25	2		T26	2		T28	10
valid_sources[0x41]	61274	1			T22	1		T25	1		T26	5
valid_sources[0x42]	66865	1			T22	2		T28	8		T53	1
valid_sources[0x43]	62408	1			T23	1		T25	4		T26	10
valid_sources[0x44]	174344	1			T23	3		T25	1		T28	9
valid_sources[0x45]	62657	1			T25	1		T26	11		T28	9
valid_sources[0x46]	74171	1			T22	1		T26	4		T28	7
valid_sources[0x47]	69652	1			T22	2		T26	10		T28	6
valid_sources[0x48]	66023	1			T22	2		T25	1		T28	6
valid_sources[0x49]	77414	1			T22	1		T25	4		T26	6
valid_sources[0x4a]	67643	1			T26	3		T28	15		T32	513
valid_sources[0x4b]	74142	1			T22	2		T23	8		T25	3
valid_sources[0x4c]	59709	1			T22	2		T23	1		T25	1
valid_sources[0x4d]	75672	1			T22	3		T25	1		T26	12
valid_sources[0x4e]	70069	1			T22	4		T25	1		T26	6
valid_sources[0x4f]	71126	1			T25	3		T26	7		T28	8
valid_sources[0x50]	62281	1			T22	2		T26	15		T28	15
valid_sources[0x51]	65163	1			T22	1		T25	1		T26	16
valid_sources[0x52]	67680	1			T22	1		T26	6		T28	7
valid_sources[0x53]	58157	1			T23	1		T25	1		T26	5
valid_sources[0x54]	62785	1			T25	4		T26	7		T28	9
valid_sources[0x55]	71549	1			T25	1		T26	2		T28	5
valid_sources[0x56]	70714	1			T25	3		T26	4		T28	11
valid_sources[0x57]	66872	1			T25	1		T26	7		T28	5
valid_sources[0x58]	63715	1			T22	1		T26	12		T28	6
valid_sources[0x59]	68117	1			T22	1		T25	2		T26	13
valid_sources[0x5a]	71374	1			T23	3		T25	2		T26	5
valid_sources[0x5b]	194323	1			T22	3		T23	1		T25	1
valid_sources[0x5c]	67835	1			T22	1		T25	2		T28	9
valid_sources[0x5d]	193395	1			T26	2		T28	9		T32	543
valid_sources[0x5e]	60752	1			T26	22		T28	11		T32	548
valid_sources[0x5f]	65505	1			T25	1		T26	8		T28	7
valid_sources[0x60]	64186	1			T23	9		T25	3		T26	15
valid_sources[0x61]	63903	1			T22	1		T25	1		T26	9
valid_sources[0x62]	72067	1			T26	2		T28	11		T53	8
valid_sources[0x63]	68205	1			T25	1		T26	13		T28	9
valid_sources[0x64]	65956	1			T22	2		T26	3		T28	5
valid_sources[0x65]	72243	1			T26	7		T28	7		T32	529
valid_sources[0x66]	63285	1			T22	1		T25	2		T26	10
valid_sources[0x67]	68954	1			T25	2		T26	2		T28	6
valid_sources[0x68]	73445	1			T26	5		T28	8		T53	3
valid_sources[0x69]	71166	1			T22	1		T25	3		T26	3
valid_sources[0x6a]	126401	1			T22	1		T25	1		T28	6
valid_sources[0x6b]	63212	1			T23	2		T25	2		T26	3
valid_sources[0x6c]	59900	1			T26	7		T28	12		T32	555
valid_sources[0x6d]	68131	1			T22	1		T26	5		T28	6
valid_sources[0x6e]	63777	1			T25	4		T26	8		T28	11
valid_sources[0x6f]	69687	1			T22	3		T25	4		T26	1
valid_sources[0x70]	68101	1			T25	2		T28	10		T32	558
valid_sources[0x71]	67689	1			T22	1		T26	11		T28	9
valid_sources[0x72]	63886	1			T22	2		T26	1		T28	10
valid_sources[0x73]	66149	1			T23	7		T26	7		T28	9
valid_sources[0x74]	70970	1			T26	8		T28	7		T32	545
valid_sources[0x75]	62585	1			T22	1		T23	6		T26	8
valid_sources[0x76]	69977	1			T25	1		T26	5		T28	10
valid_sources[0x77]	78098	1			T25	3		T26	3		T28	7
valid_sources[0x78]	60151	1			T23	3		T25	2		T26	19
valid_sources[0x79]	63947	1			T25	2		T26	5		T28	8
valid_sources[0x7a]	64495	1			T22	3		T23	1		T25	3
valid_sources[0x7b]	64136	1			T22	3		T23	1		T25	2
valid_sources[0x7c]	64462	1			T25	4		T26	5		T28	8
valid_sources[0x7d]	65286	1			T22	1		T25	3		T26	5
valid_sources[0x7e]	61500	1			T22	1		T25	1		T26	3
valid_sources[0x7f]	60472	1			T25	1		T26	8		T28	4
valid_sources[0x80]	75288	1			T25	1		T26	4		T28	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4383998

1

T21

89

T22

17

T23

53

values[0x0]

all_enables

biggest_size

5628440

1

T21

105

T22

79

T23

54

values[0x1]

all_enables

biggest_size

5629217

1

T21

101

T22

83

T23

62