Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	153865148	0	0	0
ctrl_en_input_filter_rd_A	153865148	87240	0	0
intr_ctrl_en_falling_rd_A	153865148	88981	0	0
intr_ctrl_en_lvlhigh_rd_A	153865148	86493	0	0
intr_ctrl_en_lvllow_rd_A	153865148	88275	0	0
intr_ctrl_en_rising_rd_A	153865148	87932	0	0
intr_enable_rd_A	153865148	87272	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153865148	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153865148	87240	0	0
T1	551904	2151	0	0
T2	153189	6367	0	0
T3	0	33	0	0
T4	0	364	0	0
T5	0	290	0	0
T6	0	2904	0	0
T7	0	3509	0	0
T8	0	5	0	0
T9	0	238	0	0
T10	0	6467	0	0
T11	1497	0	0	0
T12	1481	0	0	0
T13	8838	0	0	0
T14	10871	0	0	0
T15	1540	0	0	0
T16	4008	0	0	0
T17	11040	0	0	0
T18	4130	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153865148	88981	0	0
T1	551904	1760	0	0
T2	153189	5978	0	0
T3	0	34	0	0
T4	0	239	0	0
T5	0	213	0	0
T6	0	2878	0	0
T7	0	3656	0	0
T8	0	11	0	0
T9	0	162	0	0
T11	1497	0	0	0
T12	1481	0	0	0
T13	8838	0	0	0
T14	10871	0	0	0
T15	1540	0	0	0
T16	4008	0	0	0
T17	11040	0	0	0
T18	4130	0	0	0
T19	0	5	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153865148	86493	0	0
T1	551904	1814	0	0
T2	153189	5870	0	0
T3	0	25	0	0
T4	0	380	0	0
T5	0	283	0	0
T6	0	3282	0	0
T7	0	3574	0	0
T8	0	6	0	0
T11	1497	0	0	0
T12	1481	0	0	0
T13	8838	0	0	0
T14	10871	0	0	0
T15	1540	0	0	0
T16	4008	0	0	0
T17	11040	0	0	0
T18	4130	0	0	0
T19	0	1	0	0
T20	0	4	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153865148	88275	0	0
T1	551904	1975	0	0
T2	153189	6114	0	0
T3	0	45	0	0
T4	0	319	0	0
T5	0	292	0	0
T6	0	2910	0	0
T7	0	3657	0	0
T8	0	7	0	0
T9	0	155	0	0
T10	0	6357	0	0
T11	1497	0	0	0
T12	1481	0	0	0
T13	8838	0	0	0
T14	10871	0	0	0
T15	1540	0	0	0
T16	4008	0	0	0
T17	11040	0	0	0
T18	4130	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153865148	87932	0	0
T1	551904	2178	0	0
T2	153189	6140	0	0
T3	0	62	0	0
T4	0	328	0	0
T5	0	298	0	0
T6	0	3103	0	0
T7	0	3764	0	0
T8	0	8	0	0
T9	0	179	0	0
T11	1497	0	0	0
T12	1481	0	0	0
T13	8838	0	0	0
T14	10871	0	0	0
T15	1540	0	0	0
T16	4008	0	0	0
T17	11040	0	0	0
T18	4130	0	0	0
T19	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153865148	87272	0	0
T1	551904	1841	0	0
T2	153189	6206	0	0
T3	0	35	0	0
T4	0	339	0	0
T5	0	343	0	0
T6	0	2917	0	0
T7	0	3802	0	0
T8	0	3	0	0
T9	0	252	0	0
T11	1497	0	0	0
T12	1481	0	0	0
T13	8838	0	0	0
T14	10871	0	0	0
T15	1540	0	0	0
T16	4008	0	0	0
T17	11040	0	0	0
T18	4130	0	0	0
T20	0	4	0	0