Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3516452	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

15153118

1

T41

186

T42

339

T43

353

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7591963	1			T41	19		T42	28		T43	132
values[0x0]	5457137	1			T41	90		T42	159		T43	134
values[0x1]	5620470	1			T41	88		T42	167		T43	148

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2719902	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

15949668

1

T41

188

T42

341

T43

366

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	63504	1			T41	4		T42	2		T44	594
valid_sources[0x01]	63393	1			T43	1		T44	589		T46	6
valid_sources[0x02]	68093	1			T42	1		T44	557		T46	8
valid_sources[0x03]	68981	1			T42	3		T44	565		T46	14
valid_sources[0x04]	72281	1			T44	524		T46	12		T49	5
valid_sources[0x05]	62948	1			T42	3		T43	3		T44	604
valid_sources[0x06]	63388	1			T42	1		T43	2		T44	572
valid_sources[0x07]	66746	1			T41	2		T43	6		T44	577
valid_sources[0x08]	63901	1			T42	3		T44	580		T46	8
valid_sources[0x09]	60425	1			T41	1		T42	2		T43	2
valid_sources[0x0a]	73101	1			T42	3		T44	582		T46	7
valid_sources[0x0b]	67399	1			T42	3		T44	547		T46	7
valid_sources[0x0c]	70522	1			T41	8		T42	2		T43	1
valid_sources[0x0d]	67684	1			T41	2		T43	4		T44	569
valid_sources[0x0e]	68698	1			T41	2		T42	1		T43	5
valid_sources[0x0f]	67455	1			T42	2		T43	2		T44	572
valid_sources[0x10]	68470	1			T42	1		T43	2		T44	581
valid_sources[0x11]	62388	1			T43	3		T44	539		T46	7
valid_sources[0x12]	65847	1			T42	1		T44	585		T46	11
valid_sources[0x13]	69901	1			T43	1		T44	517		T46	14
valid_sources[0x14]	65761	1			T43	4		T44	575		T46	13
valid_sources[0x15]	60240	1			T41	2		T42	3		T44	534
valid_sources[0x16]	73553	1			T42	1		T43	1		T44	522
valid_sources[0x17]	65616	1			T44	615		T46	8		T50	80
valid_sources[0x18]	75333	1			T41	1		T43	3		T44	565
valid_sources[0x19]	69685	1			T42	2		T43	1		T44	593
valid_sources[0x1a]	66961	1			T41	1		T42	3		T43	3
valid_sources[0x1b]	68597	1			T41	1		T42	1		T44	530
valid_sources[0x1c]	63077	1			T41	1		T42	3		T44	602
valid_sources[0x1d]	201560	1			T41	1		T43	3		T44	574
valid_sources[0x1e]	64604	1			T41	7		T42	1		T43	3
valid_sources[0x1f]	65954	1			T42	2		T43	3		T44	577
valid_sources[0x20]	63184	1			T42	2		T43	2		T44	532
valid_sources[0x21]	66470	1			T44	594		T46	10		T50	107
valid_sources[0x22]	61681	1			T44	591		T46	6		T49	5
valid_sources[0x23]	65776	1			T44	604		T46	11		T50	132
valid_sources[0x24]	71342	1			T41	5		T42	1		T43	2
valid_sources[0x25]	66601	1			T42	2		T43	1		T44	563
valid_sources[0x26]	69498	1			T41	1		T42	3		T44	576
valid_sources[0x27]	120092	1			T42	3		T43	1		T44	572
valid_sources[0x28]	62579	1			T42	1		T43	3		T44	581
valid_sources[0x29]	67776	1			T41	1		T43	2		T44	579
valid_sources[0x2a]	71086	1			T41	1		T42	5		T43	1
valid_sources[0x2b]	68310	1			T42	1		T44	600		T46	9
valid_sources[0x2c]	64394	1			T42	2		T44	598		T46	11
valid_sources[0x2d]	70005	1			T42	3		T43	4		T44	600
valid_sources[0x2e]	65887	1			T41	3		T42	2		T44	563
valid_sources[0x2f]	73973	1			T42	2		T44	613		T46	7
valid_sources[0x30]	67141	1			T42	1		T44	529		T46	13
valid_sources[0x31]	61817	1			T42	5		T43	2		T44	541
valid_sources[0x32]	67706	1			T43	2		T44	581		T46	8
valid_sources[0x33]	63879	1			T42	2		T43	3		T44	601
valid_sources[0x34]	64843	1			T44	595		T46	10		T50	121
valid_sources[0x35]	62858	1			T42	4		T43	4		T44	605
valid_sources[0x36]	66435	1			T42	5		T43	1		T44	611
valid_sources[0x37]	63555	1			T41	2		T42	4		T43	2
valid_sources[0x38]	67097	1			T42	1		T44	585		T46	7
valid_sources[0x39]	67682	1			T42	2		T43	1		T44	567
valid_sources[0x3a]	71284	1			T42	3		T44	562		T46	8
valid_sources[0x3b]	191493	1			T42	1		T44	580		T46	4
valid_sources[0x3c]	66262	1			T42	2		T43	1		T44	515
valid_sources[0x3d]	75077	1			T43	3		T44	604		T46	8
valid_sources[0x3e]	67635	1			T42	3		T43	4		T44	584
valid_sources[0x3f]	64694	1			T44	603		T46	10		T50	106
valid_sources[0x40]	67137	1			T44	503		T46	10		T50	127
valid_sources[0x41]	63917	1			T42	2		T44	580		T46	9
valid_sources[0x42]	64519	1			T41	5		T42	2		T44	560
valid_sources[0x43]	71744	1			T44	542		T46	14		T50	113
valid_sources[0x44]	65609	1			T43	1		T44	543		T46	8
valid_sources[0x45]	65198	1			T42	1		T43	4		T44	538
valid_sources[0x46]	68171	1			T41	1		T43	3		T44	588
valid_sources[0x47]	65408	1			T43	2		T44	572		T46	14
valid_sources[0x48]	67870	1			T42	1		T43	2		T44	542
valid_sources[0x49]	67653	1			T42	1		T43	2		T44	565
valid_sources[0x4a]	67837	1			T42	3		T43	1		T44	600
valid_sources[0x4b]	64512	1			T41	2		T42	1		T43	2
valid_sources[0x4c]	62104	1			T42	3		T43	4		T44	619
valid_sources[0x4d]	62876	1			T42	3		T43	2		T44	606
valid_sources[0x4e]	64232	1			T42	3		T44	535		T46	5
valid_sources[0x4f]	69313	1			T42	1		T44	586		T46	6
valid_sources[0x50]	70828	1			T42	1		T43	2		T44	572
valid_sources[0x51]	60956	1			T41	3		T42	2		T43	1
valid_sources[0x52]	67027	1			T42	1		T43	3		T44	558
valid_sources[0x53]	65566	1			T43	1		T44	584		T46	5
valid_sources[0x54]	65136	1			T41	2		T42	1		T44	536
valid_sources[0x55]	68413	1			T42	1		T44	606		T46	2
valid_sources[0x56]	63146	1			T42	5		T43	2		T44	571
valid_sources[0x57]	68203	1			T42	2		T44	574		T46	10
valid_sources[0x58]	66930	1			T44	561		T46	9		T50	119
valid_sources[0x59]	63421	1			T42	1		T44	571		T46	8
valid_sources[0x5a]	63898	1			T42	1		T43	3		T44	528
valid_sources[0x5b]	81648	1			T43	1		T44	546		T46	13
valid_sources[0x5c]	63259	1			T41	1		T42	2		T43	1
valid_sources[0x5d]	61753	1			T43	1		T44	512		T46	10
valid_sources[0x5e]	68615	1			T41	1		T42	4		T43	1
valid_sources[0x5f]	87156	1			T42	1		T44	573		T46	14
valid_sources[0x60]	159288	1			T43	1		T44	584		T46	7
valid_sources[0x61]	64171	1			T41	1		T42	3		T43	1
valid_sources[0x62]	69515	1			T43	3		T44	550		T46	7
valid_sources[0x63]	66245	1			T42	1		T43	1		T44	557
valid_sources[0x64]	67048	1			T42	3		T43	2		T44	570
valid_sources[0x65]	183317	1			T42	2		T44	556		T46	11
valid_sources[0x66]	70288	1			T42	4		T43	1		T44	612
valid_sources[0x67]	66521	1			T42	2		T43	3		T44	564
valid_sources[0x68]	64332	1			T41	1		T42	5		T44	622
valid_sources[0x69]	62347	1			T42	2		T44	548		T46	10
valid_sources[0x6a]	66040	1			T42	3		T44	564		T46	8
valid_sources[0x6b]	69650	1			T44	553		T46	8		T50	120
valid_sources[0x6c]	66263	1			T41	2		T42	2		T43	3
valid_sources[0x6d]	69324	1			T41	12		T43	1		T44	560
valid_sources[0x6e]	73547	1			T42	3		T43	1		T44	585
valid_sources[0x6f]	66222	1			T43	4		T44	557		T46	14
valid_sources[0x70]	65630	1			T42	2		T43	1		T44	570
valid_sources[0x71]	65153	1			T44	554		T46	12		T50	128
valid_sources[0x72]	68901	1			T41	1		T44	538		T46	6
valid_sources[0x73]	70897	1			T41	3		T43	2		T44	539
valid_sources[0x74]	62112	1			T41	4		T43	1		T44	534
valid_sources[0x75]	74813	1			T41	1		T42	3		T43	4
valid_sources[0x76]	68739	1			T42	2		T44	559		T46	6
valid_sources[0x77]	68415	1			T41	1		T42	2		T43	2
valid_sources[0x78]	63899	1			T42	3		T44	591		T46	6
valid_sources[0x79]	71161	1			T41	1		T42	1		T43	4
valid_sources[0x7a]	62654	1			T41	3		T42	1		T43	1
valid_sources[0x7b]	65227	1			T41	3		T42	1		T44	514
valid_sources[0x7c]	76859	1			T42	1		T43	3		T44	555
valid_sources[0x7d]	72256	1			T41	2		T43	1		T44	558
valid_sources[0x7e]	64791	1			T42	1		T43	4		T44	550
valid_sources[0x7f]	71111	1			T42	1		T44	532		T46	6
valid_sources[0x80]	61407	1			T41	4		T42	2		T44	576

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4276146

1

T41

8

T42

13

T43

71

values[0x0]

all_enables

biggest_size

5440265

1

T41

90

T42

159

T43

134

values[0x1]

all_enables

biggest_size

5436707

1

T41

88

T42

167

T43

148