Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	139025643	0	0	0
ctrl_en_input_filter_rd_A	139025643	44437	0	0
intr_ctrl_en_falling_rd_A	139025643	44930	0	0
intr_ctrl_en_lvlhigh_rd_A	139025643	44661	0	0
intr_ctrl_en_lvllow_rd_A	139025643	44361	0	0
intr_ctrl_en_rising_rd_A	139025643	44256	0	0
intr_enable_rd_A	139025643	44634	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139025643	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139025643	44437	0	0
T1	7092	1	0	0
T2	0	6226	0	0
T3	0	43	0	0
T4	0	2	0	0
T5	0	266	0	0
T6	0	389	0	0
T7	0	9	0	0
T8	0	4647	0	0
T9	0	5881	0	0
T10	0	140	0	0
T11	67044	0	0	0
T12	25206	0	0	0
T13	373766	0	0	0
T14	690965	0	0	0
T15	3632	0	0	0
T16	7730	0	0	0
T17	3953	0	0	0
T18	8732	0	0	0
T19	21295	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139025643	44930	0	0
T2	0	6610	0	0
T3	0	34	0	0
T5	0	197	0	0
T6	0	356	0	0
T7	0	5	0	0
T8	0	4873	0	0
T9	0	5862	0	0
T10	0	123	0	0
T20	8885	8	0	0
T21	0	68	0	0
T22	7733	0	0	0
T23	112760	0	0	0
T24	192880	0	0	0
T25	3151	0	0	0
T26	4469	0	0	0
T27	3414	0	0	0
T28	1037	0	0	0
T29	22073	0	0	0
T30	3543	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139025643	44661	0	0
T2	0	6476	0	0
T3	0	31	0	0
T5	0	171	0	0
T6	0	375	0	0
T8	0	4971	0	0
T9	0	6234	0	0
T10	0	122	0	0
T20	8885	3	0	0
T21	0	93	0	0
T22	7733	0	0	0
T23	112760	0	0	0
T24	192880	0	0	0
T25	3151	0	0	0
T26	4469	0	0	0
T27	3414	0	0	0
T28	1037	0	0	0
T29	22073	0	0	0
T30	3543	0	0	0
T31	0	315	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139025643	44361	0	0
T1	0	12	0	0
T2	0	6222	0	0
T3	0	67	0	0
T4	0	3	0	0
T5	0	134	0	0
T6	0	370	0	0
T8	0	5159	0	0
T9	0	5811	0	0
T10	0	69	0	0
T20	8885	7	0	0
T22	7733	0	0	0
T23	112760	0	0	0
T24	192880	0	0	0
T25	3151	0	0	0
T26	4469	0	0	0
T27	3414	0	0	0
T28	1037	0	0	0
T29	22073	0	0	0
T30	3543	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139025643	44256	0	0
T2	144490	6173	0	0
T3	0	36	0	0
T4	0	6	0	0
T5	0	155	0	0
T6	0	375	0	0
T7	0	10	0	0
T8	0	4893	0	0
T9	0	5827	0	0
T10	0	81	0	0
T21	0	71	0	0
T32	1807	0	0	0
T33	5211	0	0	0
T34	4014	0	0	0
T35	301647	0	0	0
T36	19296	0	0	0
T37	11757	0	0	0
T38	7008	0	0	0
T39	10328	0	0	0
T40	1873	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139025643	44634	0	0
T1	0	3	0	0
T2	0	6155	0	0
T3	0	33	0	0
T5	0	196	0	0
T6	0	360	0	0
T8	0	4998	0	0
T9	0	5538	0	0
T10	0	146	0	0
T20	8885	2	0	0
T21	0	53	0	0
T22	7733	0	0	0
T23	112760	0	0	0
T24	192880	0	0	0
T25	3151	0	0	0
T26	4469	0	0	0
T27	3414	0	0	0
T28	1037	0	0	0
T29	22073	0	0	0
T30	3543	0	0	0