Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	144590465	0	0	0
ctrl_en_input_filter_rd_A	144590465	59576	0	0
intr_ctrl_en_falling_rd_A	144590465	59599	0	0
intr_ctrl_en_lvlhigh_rd_A	144590465	59277	0	0
intr_ctrl_en_lvllow_rd_A	144590465	60018	0	0
intr_ctrl_en_rising_rd_A	144590465	59826	0	0
intr_enable_rd_A	144590465	60117	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144590465	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144590465	59576	0	0
T1	138875	6365	0	0
T2	0	3204	0	0
T3	0	252	0	0
T4	0	3	0	0
T5	0	3	0	0
T6	0	3769	0	0
T7	0	1	0	0
T8	0	5628	0	0
T9	0	128	0	0
T10	0	290	0	0
T11	4253	0	0	0
T12	2413	0	0	0
T13	2105	0	0	0
T14	1590	0	0	0
T15	5763	0	0	0
T16	6224	0	0	0
T17	3085	0	0	0
T18	1470	0	0	0
T19	4592	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144590465	59599	0	0
T1	138875	6217	0	0
T2	0	3303	0	0
T3	0	192	0	0
T4	0	3	0	0
T5	0	15	0	0
T6	0	3789	0	0
T7	0	4	0	0
T8	0	5324	0	0
T11	4253	0	0	0
T12	2413	0	0	0
T13	2105	0	0	0
T14	1590	0	0	0
T15	5763	0	0	0
T16	6224	0	0	0
T17	3085	5	0	0
T18	1470	0	0	0
T19	4592	0	0	0
T20	0	1	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144590465	59277	0	0
T1	138875	6098	0	0
T2	0	3337	0	0
T3	0	223	0	0
T6	0	3950	0	0
T7	0	4	0	0
T8	0	5420	0	0
T9	0	168	0	0
T11	4253	0	0	0
T12	2413	8	0	0
T13	2105	0	0	0
T14	1590	0	0	0
T15	5763	0	0	0
T16	6224	0	0	0
T17	3085	1	0	0
T18	1470	0	0	0
T19	4592	0	0	0
T20	0	10	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144590465	60018	0	0
T1	138875	5866	0	0
T2	0	3361	0	0
T3	0	185	0	0
T5	0	6	0	0
T6	0	3795	0	0
T7	0	3	0	0
T8	0	5517	0	0
T11	4253	0	0	0
T12	2413	2	0	0
T13	2105	0	0	0
T14	1590	0	0	0
T15	5763	0	0	0
T16	6224	0	0	0
T17	3085	0	0	0
T18	1470	0	0	0
T19	4592	0	0	0
T20	0	3	0	0
T21	0	4	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144590465	59826	0	0
T1	138875	6426	0	0
T2	0	3148	0	0
T3	0	198	0	0
T6	0	3895	0	0
T7	0	20	0	0
T8	0	5585	0	0
T9	0	196	0	0
T10	0	228	0	0
T11	4253	0	0	0
T12	2413	0	0	0
T13	2105	0	0	0
T14	1590	0	0	0
T15	5763	0	0	0
T16	6224	0	0	0
T17	3085	2	0	0
T18	1470	0	0	0
T19	4592	0	0	0
T22	0	259	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144590465	60117	0	0
T1	138875	6391	0	0
T2	0	3309	0	0
T3	0	173	0	0
T4	0	4	0	0
T6	0	3785	0	0
T7	0	5	0	0
T8	0	5443	0	0
T9	0	126	0	0
T11	4253	0	0	0
T12	2413	0	0	0
T13	2105	0	0	0
T14	1590	0	0	0
T15	5763	0	0	0
T16	6224	0	0	0
T17	3085	8	0	0
T18	1470	0	0	0
T19	4592	0	0	0
T20	0	5	0	0