Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4087464	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

18519813

1

T23

2139

T24

782

T25

1092

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8973198	1			T23	3248		T24	352		T25	1287
values[0x0]	6697868	1			T23	231		T24	306		T25	210
values[0x1]	6936211	1			T23	265		T24	311		T25	231

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3135368	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

19471909

1

T23

2479

T24

827

T25

1209

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	86972	1			T23	6		T25	9		T26	4
valid_sources[0x01]	141119	1			T23	27		T24	6		T25	10
valid_sources[0x02]	87227	1			T23	19		T24	1		T25	4
valid_sources[0x03]	81701	1			T23	26		T24	3		T25	8
valid_sources[0x04]	77946	1			T23	4		T24	10		T25	7
valid_sources[0x05]	79396	1			T23	10		T25	6		T26	10
valid_sources[0x06]	82358	1			T23	5		T24	5		T25	8
valid_sources[0x07]	86237	1			T23	8		T24	3		T25	3
valid_sources[0x08]	82443	1			T23	13		T24	3		T25	10
valid_sources[0x09]	84208	1			T23	24		T24	5		T25	7
valid_sources[0x0a]	89039	1			T23	36		T24	7		T25	5
valid_sources[0x0b]	81487	1			T23	14		T24	5		T25	3
valid_sources[0x0c]	85520	1			T23	12		T24	3		T25	8
valid_sources[0x0d]	80667	1			T23	5		T24	3		T25	8
valid_sources[0x0e]	79030	1			T23	8		T24	1		T25	9
valid_sources[0x0f]	92872	1			T23	17		T24	6		T25	4
valid_sources[0x10]	85608	1			T23	3		T24	5		T25	10
valid_sources[0x11]	86116	1			T23	21		T24	1		T25	8
valid_sources[0x12]	79928	1			T23	7		T24	5		T25	4
valid_sources[0x13]	90498	1			T23	17		T24	2		T25	3
valid_sources[0x14]	84264	1			T23	10		T24	2		T25	5
valid_sources[0x15]	86915	1			T23	8		T25	2		T26	10
valid_sources[0x16]	94518	1			T23	13		T24	8		T25	16
valid_sources[0x17]	84011	1			T23	11		T24	5		T25	9
valid_sources[0x18]	82419	1			T23	8		T24	6		T25	10
valid_sources[0x19]	86901	1			T23	14		T25	4		T26	6
valid_sources[0x1a]	90949	1			T23	22		T24	3		T25	6
valid_sources[0x1b]	77084	1			T23	12		T24	1		T25	11
valid_sources[0x1c]	75969	1			T23	18		T24	3		T25	6
valid_sources[0x1d]	79170	1			T23	10		T24	3		T25	6
valid_sources[0x1e]	85928	1			T23	12		T24	6		T25	2
valid_sources[0x1f]	81725	1			T23	7		T24	3		T25	9
valid_sources[0x20]	77022	1			T23	7		T24	7		T25	6
valid_sources[0x21]	88824	1			T23	18		T24	2		T25	6
valid_sources[0x22]	83353	1			T23	17		T24	7		T25	6
valid_sources[0x23]	77574	1			T23	5		T24	11		T25	9
valid_sources[0x24]	83773	1			T23	10		T24	3		T25	7
valid_sources[0x25]	76694	1			T23	14		T24	8		T25	1
valid_sources[0x26]	95322	1			T23	7		T24	1		T25	4
valid_sources[0x27]	86916	1			T23	20		T24	2		T26	7
valid_sources[0x28]	84377	1			T23	9		T24	2		T25	7
valid_sources[0x29]	75913	1			T23	27		T24	2		T25	4
valid_sources[0x2a]	89843	1			T23	24		T24	1		T25	2
valid_sources[0x2b]	85610	1			T23	22		T24	4		T25	4
valid_sources[0x2c]	92635	1			T23	21		T24	5		T25	7
valid_sources[0x2d]	89550	1			T23	10		T24	5		T25	6
valid_sources[0x2e]	81515	1			T23	12		T24	3		T25	3
valid_sources[0x2f]	83992	1			T23	12		T24	1		T25	7
valid_sources[0x30]	81861	1			T23	21		T24	2		T25	5
valid_sources[0x31]	80832	1			T23	9		T24	3		T25	10
valid_sources[0x32]	81943	1			T23	6		T24	1		T25	9
valid_sources[0x33]	88117	1			T23	24		T25	5		T26	5
valid_sources[0x34]	95100	1			T23	7		T24	3		T25	5
valid_sources[0x35]	104422	1			T23	13		T24	2		T25	5
valid_sources[0x36]	89670	1			T23	21		T24	7		T25	7
valid_sources[0x37]	88442	1			T23	8		T24	5		T25	5
valid_sources[0x38]	105504	1			T23	25		T24	3		T25	16
valid_sources[0x39]	78873	1			T23	12		T24	2		T25	7
valid_sources[0x3a]	92051	1			T23	40		T24	6		T25	11
valid_sources[0x3b]	82425	1			T23	9		T24	4		T25	5
valid_sources[0x3c]	82794	1			T23	33		T24	3		T25	6
valid_sources[0x3d]	91350	1			T23	20		T24	2		T25	4
valid_sources[0x3e]	80843	1			T23	16		T24	4		T25	2
valid_sources[0x3f]	83782	1			T23	19		T24	5		T25	8
valid_sources[0x40]	80181	1			T23	9		T24	3		T25	10
valid_sources[0x41]	100450	1			T23	15		T24	4		T25	7
valid_sources[0x42]	82459	1			T23	11		T24	4		T25	7
valid_sources[0x43]	77700	1			T23	6		T24	5		T25	10
valid_sources[0x44]	90765	1			T23	11		T24	9		T25	3
valid_sources[0x45]	83080	1			T23	13		T24	6		T25	5
valid_sources[0x46]	84383	1			T23	20		T24	5		T25	2
valid_sources[0x47]	89955	1			T23	21		T24	5		T25	10
valid_sources[0x48]	84633	1			T23	25		T24	6		T25	9
valid_sources[0x49]	120002	1			T23	11		T24	2		T25	6
valid_sources[0x4a]	183375	1			T23	10		T24	7		T25	3
valid_sources[0x4b]	84610	1			T23	16		T24	4		T25	6
valid_sources[0x4c]	83220	1			T23	12		T24	7		T25	10
valid_sources[0x4d]	86030	1			T23	20		T24	2		T25	6
valid_sources[0x4e]	84862	1			T23	10		T24	2		T25	6
valid_sources[0x4f]	82923	1			T23	19		T24	4		T25	13
valid_sources[0x50]	82357	1			T23	3		T24	4		T25	10
valid_sources[0x51]	84521	1			T23	22		T24	2		T25	8
valid_sources[0x52]	77566	1			T23	14		T24	6		T25	11
valid_sources[0x53]	78020	1			T23	9		T24	2		T25	8
valid_sources[0x54]	92337	1			T23	23		T24	3		T25	6
valid_sources[0x55]	84774	1			T23	14		T24	5		T25	6
valid_sources[0x56]	83217	1			T23	16		T24	4		T25	4
valid_sources[0x57]	80564	1			T23	27		T24	2		T25	5
valid_sources[0x58]	78606	1			T23	12		T24	5		T25	6
valid_sources[0x59]	89463	1			T23	9		T24	5		T25	4
valid_sources[0x5a]	84107	1			T23	16		T24	3		T25	6
valid_sources[0x5b]	79887	1			T23	20		T24	3		T25	5
valid_sources[0x5c]	74615	1			T23	22		T24	7		T25	7
valid_sources[0x5d]	83474	1			T23	20		T24	4		T25	4
valid_sources[0x5e]	84072	1			T23	11		T24	4		T25	6
valid_sources[0x5f]	80356	1			T23	10		T24	4		T25	9
valid_sources[0x60]	84418	1			T23	32		T24	4		T25	2
valid_sources[0x61]	85435	1			T23	23		T24	6		T25	7
valid_sources[0x62]	85902	1			T23	20		T24	10		T25	4
valid_sources[0x63]	84064	1			T23	8		T24	5		T25	11
valid_sources[0x64]	181141	1			T23	11		T24	4		T25	8
valid_sources[0x65]	81485	1			T23	10		T24	1		T25	7
valid_sources[0x66]	161050	1			T23	9		T24	5		T25	4
valid_sources[0x67]	87016	1			T23	13		T24	2		T25	6
valid_sources[0x68]	80101	1			T23	20		T24	4		T25	5
valid_sources[0x69]	86664	1			T23	16		T24	3		T25	11
valid_sources[0x6a]	80167	1			T23	3		T24	2		T25	10
valid_sources[0x6b]	88640	1			T23	35		T24	5		T25	1
valid_sources[0x6c]	78135	1			T23	20		T24	4		T25	10
valid_sources[0x6d]	88099	1			T23	11		T24	5		T25	5
valid_sources[0x6e]	92086	1			T23	15		T24	4		T25	6
valid_sources[0x6f]	80872	1			T23	16		T24	3		T25	5
valid_sources[0x70]	87286	1			T23	9		T24	4		T25	9
valid_sources[0x71]	82729	1			T23	19		T24	7		T25	7
valid_sources[0x72]	80459	1			T23	9		T24	4		T25	7
valid_sources[0x73]	80663	1			T23	7		T24	2		T25	7
valid_sources[0x74]	83595	1			T23	24		T24	4		T25	3
valid_sources[0x75]	76516	1			T23	22		T24	7		T25	6
valid_sources[0x76]	88597	1			T23	22		T24	6		T25	6
valid_sources[0x77]	80912	1			T23	23		T24	4		T25	2
valid_sources[0x78]	83959	1			T23	7		T24	1		T25	10
valid_sources[0x79]	76731	1			T23	14		T24	4		T25	10
valid_sources[0x7a]	85234	1			T23	13		T24	6		T25	5
valid_sources[0x7b]	96165	1			T23	15		T24	5		T25	9
valid_sources[0x7c]	139528	1			T23	22		T24	4		T25	6
valid_sources[0x7d]	79233	1			T23	18		T25	10		T26	9
valid_sources[0x7e]	83169	1			T23	12		T24	1		T25	2
valid_sources[0x7f]	88112	1			T23	17		T24	1		T25	12
valid_sources[0x80]	90606	1			T23	31		T24	7		T25	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5177796

1

T23

1643

T24

165

T25

651

values[0x0]

all_enables

biggest_size

6673355

1

T23

231

T24

306

T25

210

values[0x1]

all_enables

biggest_size

6668662

1

T23

265

T24

311

T25

231