Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	189160337	0	0	0
ctrl_en_input_filter_rd_A	189160337	107326	0	0
intr_ctrl_en_falling_rd_A	189160337	109493	0	0
intr_ctrl_en_lvlhigh_rd_A	189160337	107751	0	0
intr_ctrl_en_lvllow_rd_A	189160337	110836	0	0
intr_ctrl_en_rising_rd_A	189160337	108030	0	0
intr_enable_rd_A	189160337	107451	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189160337	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189160337	107326	0	0
T1	145464	4488	0	0
T2	0	157	0	0
T3	0	406	0	0
T4	0	3	0	0
T5	0	2362	0	0
T6	0	102	0	0
T7	0	4	0	0
T8	0	5434	0	0
T9	0	8472	0	0
T10	0	2825	0	0
T11	9648	0	0	0
T12	554362	0	0	0
T13	5404	0	0	0
T14	7538	0	0	0
T15	11761	0	0	0
T16	7249	0	0	0
T17	8919	0	0	0
T18	823	0	0	0
T19	6016	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189160337	109493	0	0
T1	145464	4335	0	0
T2	0	131	0	0
T3	0	409	0	0
T5	0	2307	0	0
T6	0	71	0	0
T8	0	5548	0	0
T9	0	8087	0	0
T10	0	2904	0	0
T11	9648	0	0	0
T12	554362	0	0	0
T13	5404	0	0	0
T14	7538	0	0	0
T15	11761	0	0	0
T16	7249	0	0	0
T17	8919	0	0	0
T18	823	0	0	0
T19	6016	0	0	0
T20	0	120	0	0
T21	0	175	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189160337	107751	0	0
T1	145464	4345	0	0
T2	0	130	0	0
T3	0	384	0	0
T4	0	7	0	0
T5	0	2328	0	0
T6	0	146	0	0
T8	0	5526	0	0
T9	0	8148	0	0
T10	0	2986	0	0
T11	9648	0	0	0
T12	554362	0	0	0
T13	5404	0	0	0
T14	7538	0	0	0
T15	11761	0	0	0
T16	7249	0	0	0
T17	8919	0	0	0
T18	823	0	0	0
T19	6016	0	0	0
T22	0	7	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189160337	110836	0	0
T1	145464	4249	0	0
T2	0	137	0	0
T3	0	369	0	0
T5	0	2330	0	0
T6	0	101	0	0
T7	0	6	0	0
T8	0	5726	0	0
T9	0	8545	0	0
T10	0	2826	0	0
T11	9648	0	0	0
T12	554362	0	0	0
T13	5404	0	0	0
T14	7538	0	0	0
T15	11761	0	0	0
T16	7249	0	0	0
T17	8919	0	0	0
T18	823	0	0	0
T19	6016	0	0	0
T20	0	146	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189160337	108030	0	0
T1	145464	4212	0	0
T2	0	170	0	0
T3	0	334	0	0
T4	0	6	0	0
T5	0	2190	0	0
T6	0	96	0	0
T8	0	5521	0	0
T9	0	8993	0	0
T10	0	2933	0	0
T11	9648	0	0	0
T12	554362	0	0	0
T13	5404	0	0	0
T14	7538	0	0	0
T15	11761	0	0	0
T16	7249	0	0	0
T17	8919	0	0	0
T18	823	0	0	0
T19	6016	0	0	0
T20	0	120	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189160337	107451	0	0
T1	145464	4398	0	0
T2	0	156	0	0
T3	0	352	0	0
T5	0	2326	0	0
T6	0	88	0	0
T7	0	4	0	0
T8	0	5427	0	0
T9	0	8254	0	0
T10	0	2610	0	0
T11	9648	0	0	0
T12	554362	0	0	0
T13	5404	0	0	0
T14	7538	0	0	0
T15	11761	0	0	0
T16	7249	0	0	0
T17	8919	0	0	0
T18	823	0	0	0
T19	6016	0	0	0
T20	0	171	0	0