Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3744067	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

17178415

1

T22

349

T23

7

T24

754

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8258624	1			T22	156		T23	1		T24	882
values[0x0]	6215099	1			T22	137		T23	16		T24	160
values[0x1]	6448759	1			T22	131		T23	15		T24	131

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2861441	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

18061041

1

T22

361

T23

13

T24

829

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	79121	1			T24	4		T29	2		T31	8
valid_sources[0x01]	81215	1			T24	3		T29	1		T41	29
valid_sources[0x02]	75721	1			T22	3		T24	2		T26	2
valid_sources[0x03]	75249	1			T22	1		T24	3		T26	2
valid_sources[0x04]	82415	1			T22	1		T24	9		T26	1
valid_sources[0x05]	77544	1			T22	8		T24	6		T29	1
valid_sources[0x06]	80416	1			T24	9		T26	1		T29	8
valid_sources[0x07]	76979	1			T24	1		T26	3		T30	1
valid_sources[0x08]	79802	1			T22	1		T24	4		T26	3
valid_sources[0x09]	78508	1			T22	3		T24	19		T26	1
valid_sources[0x0a]	78298	1			T22	1		T24	2		T26	1
valid_sources[0x0b]	86007	1			T24	6		T26	1		T27	35
valid_sources[0x0c]	85698	1			T24	8		T42	2		T43	7
valid_sources[0x0d]	89385	1			T22	3		T24	8		T26	1
valid_sources[0x0e]	83563	1			T24	9		T26	1		T29	3
valid_sources[0x0f]	83008	1			T22	2		T24	1		T26	1
valid_sources[0x10]	70923	1			T24	7		T26	1		T29	3
valid_sources[0x11]	80642	1			T22	3		T24	1		T27	25
valid_sources[0x12]	74959	1			T22	2		T24	7		T29	1
valid_sources[0x13]	91157	1			T24	9		T26	1		T29	3
valid_sources[0x14]	83010	1			T22	5		T24	2		T31	2
valid_sources[0x15]	105369	1			T24	8		T26	5		T29	1
valid_sources[0x16]	74954	1			T22	2		T24	3		T29	3
valid_sources[0x17]	76525	1			T22	3		T26	2		T31	2
valid_sources[0x18]	79987	1			T22	4		T24	4		T30	1
valid_sources[0x19]	76768	1			T24	6		T26	2		T29	1
valid_sources[0x1a]	84827	1			T22	1		T26	3		T27	16
valid_sources[0x1b]	94761	1			T24	3		T29	1		T30	1
valid_sources[0x1c]	86305	1			T22	5		T24	5		T29	3
valid_sources[0x1d]	90752	1			T24	9		T29	1		T30	1
valid_sources[0x1e]	73696	1			T24	8		T29	1		T31	3
valid_sources[0x1f]	73771	1			T24	16		T26	1		T29	3
valid_sources[0x20]	74454	1			T22	5		T24	2		T28	2
valid_sources[0x21]	74658	1			T29	3		T42	5		T53	1
valid_sources[0x22]	88883	1			T24	2		T29	8		T31	2
valid_sources[0x23]	81065	1			T24	6		T26	1		T29	2
valid_sources[0x24]	79629	1			T22	2		T24	8		T27	51
valid_sources[0x25]	82306	1			T22	5		T24	6		T26	1
valid_sources[0x26]	75784	1			T24	6		T26	2		T29	5
valid_sources[0x27]	86361	1			T24	4		T27	88		T29	2
valid_sources[0x28]	70404	1			T23	1		T29	2		T31	2
valid_sources[0x29]	75917	1			T24	5		T26	3		T27	82
valid_sources[0x2a]	77202	1			T22	1		T24	1		T31	4
valid_sources[0x2b]	89069	1			T22	1		T24	5		T26	1
valid_sources[0x2c]	74742	1			T22	2		T24	3		T26	1
valid_sources[0x2d]	82710	1			T22	4		T24	3		T27	29
valid_sources[0x2e]	76142	1			T23	1		T24	4		T26	1
valid_sources[0x2f]	78349	1			T22	5		T24	4		T27	15
valid_sources[0x30]	87202	1			T24	4		T26	1		T27	196
valid_sources[0x31]	73407	1			T24	8		T26	3		T29	4
valid_sources[0x32]	87027	1			T22	1		T24	1		T26	1
valid_sources[0x33]	82710	1			T22	2		T24	10		T26	1
valid_sources[0x34]	73970	1			T22	2		T24	14		T26	4
valid_sources[0x35]	79158	1			T24	1		T29	3		T30	1
valid_sources[0x36]	76700	1			T22	1		T24	4		T26	2
valid_sources[0x37]	80030	1			T24	2		T26	3		T29	4
valid_sources[0x38]	84342	1			T24	5		T26	2		T30	3
valid_sources[0x39]	77172	1			T24	1		T30	1		T31	1
valid_sources[0x3a]	84466	1			T24	8		T26	1		T29	4
valid_sources[0x3b]	80017	1			T22	1		T24	10		T26	1
valid_sources[0x3c]	79697	1			T22	1		T24	5		T26	1
valid_sources[0x3d]	77954	1			T22	4		T24	4		T26	1
valid_sources[0x3e]	75971	1			T22	1		T26	4		T29	1
valid_sources[0x3f]	89211	1			T24	5		T29	7		T30	2
valid_sources[0x40]	82924	1			T24	3		T29	5		T30	1
valid_sources[0x41]	79879	1			T22	1		T24	13		T26	1
valid_sources[0x42]	80437	1			T24	5		T26	5		T27	192
valid_sources[0x43]	81693	1			T22	2		T24	6		T29	2
valid_sources[0x44]	77623	1			T22	1		T24	7		T26	2
valid_sources[0x45]	83878	1			T24	3		T26	3		T29	4
valid_sources[0x46]	94406	1			T22	4		T24	2		T30	1
valid_sources[0x47]	74904	1			T24	6		T26	3		T29	6
valid_sources[0x48]	77148	1			T22	3		T24	1		T26	3
valid_sources[0x49]	74159	1			T22	8		T24	1		T31	2
valid_sources[0x4a]	81834	1			T24	3		T29	3		T30	3
valid_sources[0x4b]	88472	1			T22	4		T24	8		T26	2
valid_sources[0x4c]	89831	1			T24	4		T26	2		T29	3
valid_sources[0x4d]	76230	1			T22	1		T24	8		T30	2
valid_sources[0x4e]	74640	1			T22	3		T24	1		T29	3
valid_sources[0x4f]	83755	1			T22	1		T24	1		T26	1
valid_sources[0x50]	79927	1			T24	1		T27	89		T29	3
valid_sources[0x51]	134601	1			T22	2		T24	13		T26	1
valid_sources[0x52]	75024	1			T24	1		T29	4		T30	1
valid_sources[0x53]	76893	1			T22	2		T24	10		T26	1
valid_sources[0x54]	84735	1			T24	5		T27	15		T29	13
valid_sources[0x55]	73947	1			T22	2		T24	10		T29	1
valid_sources[0x56]	71758	1			T24	13		T42	1		T53	2
valid_sources[0x57]	82124	1			T22	3		T24	4		T26	6
valid_sources[0x58]	77768	1			T22	3		T24	10		T31	1
valid_sources[0x59]	79089	1			T24	2		T31	4		T42	3
valid_sources[0x5a]	81946	1			T22	2		T24	10		T26	1
valid_sources[0x5b]	78610	1			T22	2		T24	2		T26	1
valid_sources[0x5c]	87401	1			T24	3		T26	5		T29	7
valid_sources[0x5d]	79675	1			T24	1		T26	2		T29	4
valid_sources[0x5e]	75549	1			T22	8		T24	6		T29	3
valid_sources[0x5f]	81927	1			T24	2		T26	2		T29	2
valid_sources[0x60]	78630	1			T22	1		T24	4		T26	2
valid_sources[0x61]	78805	1			T29	2		T31	5		T41	7
valid_sources[0x62]	81614	1			T24	4		T29	5		T30	1
valid_sources[0x63]	82639	1			T22	2		T24	1		T29	4
valid_sources[0x64]	74601	1			T24	2		T27	56		T31	4
valid_sources[0x65]	75147	1			T22	1		T24	3		T26	2
valid_sources[0x66]	85899	1			T22	1		T26	2		T29	3
valid_sources[0x67]	90431	1			T24	4		T29	2		T30	2
valid_sources[0x68]	77733	1			T22	8		T24	2		T26	2
valid_sources[0x69]	85277	1			T22	6		T24	2		T26	1
valid_sources[0x6a]	85974	1			T24	8		T26	2		T31	1
valid_sources[0x6b]	71077	1			T22	2		T24	3		T26	1
valid_sources[0x6c]	76771	1			T22	4		T24	4		T25	453
valid_sources[0x6d]	78965	1			T24	6		T26	1		T27	6
valid_sources[0x6e]	77181	1			T22	2		T24	1		T26	1
valid_sources[0x6f]	82683	1			T22	2		T24	1		T29	3
valid_sources[0x70]	85790	1			T22	1		T26	1		T29	3
valid_sources[0x71]	76807	1			T24	3		T29	2		T30	2
valid_sources[0x72]	79907	1			T24	6		T29	3		T30	2
valid_sources[0x73]	85761	1			T24	9		T26	3		T29	2
valid_sources[0x74]	77384	1			T24	6		T26	1		T29	5
valid_sources[0x75]	75638	1			T22	2		T24	6		T26	5
valid_sources[0x76]	80584	1			T22	2		T24	2		T26	2
valid_sources[0x77]	82157	1			T23	1		T24	11		T26	1
valid_sources[0x78]	81938	1			T22	5		T24	2		T26	2
valid_sources[0x79]	79163	1			T24	4		T29	3		T30	3
valid_sources[0x7a]	82165	1			T22	4		T24	1		T26	3
valid_sources[0x7b]	83550	1			T24	3		T29	1		T30	2
valid_sources[0x7c]	75448	1			T24	10		T26	1		T29	2
valid_sources[0x7d]	79109	1			T22	2		T24	2		T29	2
valid_sources[0x7e]	83587	1			T24	2		T26	1		T28	6
valid_sources[0x7f]	86907	1			T22	4		T24	7		T30	2
valid_sources[0x80]	74838	1			T22	1		T24	7		T26	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4801747

1

T22

81

T23

1

T24

463

values[0x0]

all_enables

biggest_size

6190926

1

T22

137

T23

6

T24

160

values[0x1]

all_enables

biggest_size

6185742

1

T22

131

T24

131

T25

167