Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	188664988	0	0	0
ctrl_en_input_filter_rd_A	188664988	103235	0	0
intr_ctrl_en_falling_rd_A	188664988	104778	0	0
intr_ctrl_en_lvlhigh_rd_A	188664988	102579	0	0
intr_ctrl_en_lvllow_rd_A	188664988	106225	0	0
intr_ctrl_en_rising_rd_A	188664988	103654	0	0
intr_enable_rd_A	188664988	103080	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188664988	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188664988	103235	0	0
T1	38161	269	0	0
T2	0	4863	0	0
T3	0	42	0	0
T4	0	147	0	0
T5	0	1	0	0
T6	0	8806	0	0
T7	0	176	0	0
T8	0	359	0	0
T9	0	36	0	0
T10	0	5572	0	0
T11	1737	0	0	0
T12	5069	0	0	0
T13	1369	0	0	0
T14	8549	0	0	0
T15	110517	0	0	0
T16	55811	0	0	0
T17	301448	0	0	0
T18	6102	0	0	0
T19	4981	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188664988	104778	0	0
T1	38161	195	0	0
T2	0	5061	0	0
T3	0	60	0	0
T4	0	201	0	0
T5	0	4	0	0
T6	0	8542	0	0
T7	0	157	0	0
T8	0	266	0	0
T9	0	3	0	0
T11	1737	0	0	0
T12	5069	0	0	0
T13	1369	0	0	0
T14	8549	0	0	0
T15	110517	0	0	0
T16	55811	0	0	0
T17	301448	0	0	0
T18	6102	0	0	0
T19	4981	0	0	0
T20	0	1	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188664988	102579	0	0
T1	38161	277	0	0
T2	0	5397	0	0
T3	0	33	0	0
T4	0	190	0	0
T5	0	7	0	0
T6	0	8536	0	0
T7	0	135	0	0
T8	0	307	0	0
T9	0	24	0	0
T11	1737	0	0	0
T12	5069	0	0	0
T13	1369	0	0	0
T14	8549	0	0	0
T15	110517	0	0	0
T16	55811	0	0	0
T17	301448	0	0	0
T18	6102	0	0	0
T19	4981	0	0	0
T20	0	14	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188664988	106225	0	0
T1	38161	311	0	0
T2	0	5064	0	0
T3	0	31	0	0
T4	0	236	0	0
T6	0	8542	0	0
T7	0	151	0	0
T8	0	381	0	0
T9	0	28	0	0
T10	0	5727	0	0
T11	1737	0	0	0
T12	5069	0	0	0
T13	1369	0	0	0
T14	8549	0	0	0
T15	110517	0	0	0
T16	55811	0	0	0
T17	301448	0	0	0
T18	6102	0	0	0
T19	4981	0	0	0
T21	0	3	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188664988	103654	0	0
T1	38161	296	0	0
T2	0	5163	0	0
T3	0	59	0	0
T4	0	211	0	0
T5	0	3	0	0
T6	0	8736	0	0
T7	0	165	0	0
T8	0	325	0	0
T9	0	15	0	0
T11	1737	0	0	0
T12	5069	0	0	0
T13	1369	0	0	0
T14	8549	0	0	0
T15	110517	0	0	0
T16	55811	0	0	0
T17	301448	0	0	0
T18	6102	0	0	0
T19	4981	0	0	0
T21	0	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188664988	103080	0	0
T1	38161	238	0	0
T2	0	5121	0	0
T3	0	65	0	0
T4	0	169	0	0
T5	0	5	0	0
T6	0	8649	0	0
T7	0	142	0	0
T8	0	314	0	0
T9	0	15	0	0
T10	0	5238	0	0
T11	1737	0	0	0
T12	5069	0	0	0
T13	1369	0	0	0
T14	8549	0	0	0
T15	110517	0	0	0
T16	55811	0	0	0
T17	301448	0	0	0
T18	6102	0	0	0
T19	4981	0	0	0