Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	168407995	0	0	0
ctrl_en_input_filter_rd_A	168407995	104253	0	0
intr_ctrl_en_falling_rd_A	168407995	107424	0	0
intr_ctrl_en_lvlhigh_rd_A	168407995	104730	0	0
intr_ctrl_en_lvllow_rd_A	168407995	106141	0	0
intr_ctrl_en_rising_rd_A	168407995	104932	0	0
intr_enable_rd_A	168407995	105531	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168407995	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168407995	104253	0	0
T1	475195	1324	0	0
T2	7688	2	0	0
T3	0	1	0	0
T4	0	14921	0	0
T5	0	3	0	0
T6	0	449	0	0
T7	0	241	0	0
T8	0	20	0	0
T9	0	178	0	0
T10	0	3837	0	0
T11	3757	0	0	0
T12	4630	0	0	0
T13	7027	0	0	0
T14	7516	0	0	0
T15	9066	0	0	0
T16	124327	0	0	0
T17	5932	0	0	0
T18	5144	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168407995	107424	0	0
T1	475195	1242	0	0
T2	7688	7	0	0
T4	0	16470	0	0
T5	0	7	0	0
T6	0	357	0	0
T7	0	280	0	0
T8	0	11	0	0
T9	0	228	0	0
T10	0	3898	0	0
T11	3757	0	0	0
T12	4630	0	0	0
T13	7027	0	0	0
T14	7516	0	0	0
T15	9066	0	0	0
T16	124327	0	0	0
T17	5932	0	0	0
T18	5144	0	0	0
T19	0	7642	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168407995	104730	0	0
T1	475195	1290	0	0
T2	7688	0	0	0
T4	0	14819	0	0
T5	0	1	0	0
T6	0	367	0	0
T7	0	239	0	0
T8	0	42	0	0
T9	0	284	0	0
T10	0	4046	0	0
T11	3757	0	0	0
T12	4630	0	0	0
T13	7027	0	0	0
T14	7516	0	0	0
T15	9066	0	0	0
T16	124327	0	0	0
T17	5932	0	0	0
T18	5144	0	0	0
T19	0	7821	0	0
T20	0	95	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168407995	106141	0	0
T1	475195	1310	0	0
T2	7688	0	0	0
T3	0	5	0	0
T4	0	15887	0	0
T5	0	7	0	0
T6	0	400	0	0
T7	0	249	0	0
T8	0	7	0	0
T9	0	211	0	0
T10	0	3763	0	0
T11	3757	0	0	0
T12	4630	0	0	0
T13	7027	0	0	0
T14	7516	0	0	0
T15	9066	0	0	0
T16	124327	0	0	0
T17	5932	0	0	0
T18	5144	0	0	0
T19	0	8031	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168407995	104932	0	0
T1	475195	1348	0	0
T2	7688	10	0	0
T4	0	14947	0	0
T5	0	9	0	0
T6	0	391	0	0
T7	0	355	0	0
T8	0	22	0	0
T9	0	158	0	0
T10	0	3726	0	0
T11	3757	0	0	0
T12	4630	0	0	0
T13	7027	0	0	0
T14	7516	0	0	0
T15	9066	0	0	0
T16	124327	0	0	0
T17	5932	0	0	0
T18	5144	0	0	0
T19	0	7849	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168407995	105531	0	0
T1	475195	1220	0	0
T2	7688	4	0	0
T4	0	15163	0	0
T5	0	4	0	0
T6	0	312	0	0
T7	0	272	0	0
T8	0	37	0	0
T9	0	237	0	0
T10	0	3982	0	0
T11	3757	0	0	0
T12	4630	0	0	0
T13	7027	0	0	0
T14	7516	0	0	0
T15	9066	0	0	0
T16	124327	0	0	0
T17	5932	0	0	0
T18	5144	0	0	0
T19	0	7794	0	0