Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	155429899	0	0	0
ctrl_en_input_filter_rd_A	155429899	107216	0	0
intr_ctrl_en_falling_rd_A	155429899	113564	0	0
intr_ctrl_en_lvlhigh_rd_A	155429899	107095	0	0
intr_ctrl_en_lvllow_rd_A	155429899	111045	0	0
intr_ctrl_en_rising_rd_A	155429899	108313	0	0
intr_enable_rd_A	155429899	108866	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155429899	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155429899	107216	0	0
T1	149115	5126	0	0
T2	0	5	0	0
T3	0	4337	0	0
T4	0	300	0	0
T5	0	311	0	0
T6	0	247	0	0
T7	0	181	0	0
T8	0	208	0	0
T9	0	1916	0	0
T10	0	1599	0	0
T11	854	0	0	0
T12	2747	0	0	0
T13	34261	0	0	0
T14	7048	0	0	0
T15	4791	0	0	0
T16	3946	0	0	0
T17	2163	0	0	0
T18	3959	0	0	0
T19	4527	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155429899	113564	0	0
T1	149115	5149	0	0
T3	0	4472	0	0
T4	0	317	0	0
T5	0	352	0	0
T6	0	180	0	0
T7	0	251	0	0
T8	0	163	0	0
T9	0	1827	0	0
T11	854	0	0	0
T12	2747	0	0	0
T13	34261	0	0	0
T14	7048	0	0	0
T15	4791	0	0	0
T16	3946	0	0	0
T17	2163	0	0	0
T18	3959	0	0	0
T19	4527	0	0	0
T20	0	4	0	0
T21	0	4	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155429899	107095	0	0
T1	149115	5023	0	0
T2	0	1	0	0
T3	0	4216	0	0
T4	0	226	0	0
T5	0	320	0	0
T6	0	253	0	0
T7	0	184	0	0
T8	0	212	0	0
T9	0	1792	0	0
T10	0	1720	0	0
T11	854	0	0	0
T12	2747	0	0	0
T13	34261	0	0	0
T14	7048	0	0	0
T15	4791	0	0	0
T16	3946	0	0	0
T17	2163	0	0	0
T18	3959	0	0	0
T19	4527	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155429899	111045	0	0
T1	149115	4674	0	0
T2	0	5	0	0
T3	0	4307	0	0
T4	0	296	0	0
T5	0	294	0	0
T6	0	244	0	0
T7	0	153	0	0
T8	0	175	0	0
T11	854	0	0	0
T12	2747	0	0	0
T13	34261	0	0	0
T14	7048	0	0	0
T15	4791	0	0	0
T16	3946	0	0	0
T17	2163	0	0	0
T18	3959	0	0	0
T19	4527	0	0	0
T21	0	1	0	0
T22	0	11	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155429899	108313	0	0
T1	149115	4952	0	0
T2	0	1	0	0
T3	0	4821	0	0
T4	0	289	0	0
T5	0	318	0	0
T6	0	170	0	0
T7	0	290	0	0
T11	854	0	0	0
T12	2747	0	0	0
T13	34261	0	0	0
T14	7048	0	0	0
T15	4791	0	0	0
T16	3946	0	0	0
T17	2163	0	0	0
T18	3959	0	0	0
T19	4527	0	0	0
T20	0	3	0	0
T21	0	4	0	0
T22	0	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155429899	108866	0	0
T1	149115	5108	0	0
T3	0	4486	0	0
T4	0	346	0	0
T5	0	253	0	0
T6	0	239	0	0
T7	0	249	0	0
T8	0	150	0	0
T9	0	1829	0	0
T10	0	1534	0	0
T11	854	0	0	0
T12	2747	0	0	0
T13	34261	0	0	0
T14	7048	0	0	0
T15	4791	0	0	0
T16	3946	0	0	0
T17	2163	0	0	0
T18	3959	0	0	0
T19	4527	0	0	0
T23	0	1	0	0