Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	180932995	0	0	0
ctrl_en_input_filter_rd_A	180932995	82602	0	0
intr_ctrl_en_falling_rd_A	180932995	84920	0	0
intr_ctrl_en_lvlhigh_rd_A	180932995	82723	0	0
intr_ctrl_en_lvllow_rd_A	180932995	84515	0	0
intr_ctrl_en_rising_rd_A	180932995	82632	0	0
intr_enable_rd_A	180932995	82762	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180932995	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180932995	82602	0	0
T1	124323	2810	0	0
T2	0	627	0	0
T3	0	160	0	0
T4	0	901	0	0
T5	0	8511	0	0
T6	0	892	0	0
T7	0	9	0	0
T8	0	3270	0	0
T9	0	84	0	0
T10	0	2027	0	0
T11	5318	0	0	0
T12	2934	0	0	0
T13	2996	0	0	0
T14	139873	0	0	0
T15	6396	0	0	0
T16	8570	0	0	0
T17	14424	0	0	0
T18	4058	0	0	0
T19	4945	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180932995	84920	0	0
T1	124323	3023	0	0
T2	0	667	0	0
T3	0	104	0	0
T4	0	998	0	0
T5	0	8697	0	0
T6	0	888	0	0
T8	0	3278	0	0
T9	0	61	0	0
T10	0	1919	0	0
T11	5318	0	0	0
T12	2934	0	0	0
T13	2996	0	0	0
T14	139873	0	0	0
T15	6396	0	0	0
T16	8570	0	0	0
T17	14424	0	0	0
T18	4058	0	0	0
T19	4945	0	0	0
T20	0	1024	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180932995	82723	0	0
T1	124323	3017	0	0
T2	0	685	0	0
T3	0	105	0	0
T4	0	1035	0	0
T5	0	8909	0	0
T6	0	878	0	0
T8	0	3543	0	0
T9	0	68	0	0
T10	0	2012	0	0
T11	5318	0	0	0
T12	2934	0	0	0
T13	2996	0	0	0
T14	139873	0	0	0
T15	6396	0	0	0
T16	8570	0	0	0
T17	14424	0	0	0
T18	4058	0	0	0
T19	4945	0	0	0
T20	0	888	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180932995	84515	0	0
T1	124323	2994	0	0
T2	0	615	0	0
T3	0	132	0	0
T4	0	881	0	0
T5	0	8726	0	0
T6	0	899	0	0
T8	0	3426	0	0
T9	0	41	0	0
T10	0	2095	0	0
T11	5318	0	0	0
T12	2934	0	0	0
T13	2996	0	0	0
T14	139873	0	0	0
T15	6396	0	0	0
T16	8570	0	0	0
T17	14424	0	0	0
T18	4058	0	0	0
T19	4945	0	0	0
T20	0	762	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180932995	82632	0	0
T1	124323	2886	0	0
T2	0	591	0	0
T3	0	139	0	0
T4	0	1002	0	0
T5	0	8479	0	0
T6	0	1003	0	0
T7	0	7	0	0
T8	0	3379	0	0
T9	0	68	0	0
T11	5318	0	0	0
T12	2934	0	0	0
T13	2996	0	0	0
T14	139873	0	0	0
T15	6396	0	0	0
T16	8570	0	0	0
T17	14424	0	0	0
T18	4058	0	0	0
T19	4945	0	0	0
T21	0	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180932995	82762	0	0
T1	124323	2917	0	0
T2	0	764	0	0
T3	0	146	0	0
T4	0	997	0	0
T5	0	8867	0	0
T6	0	900	0	0
T7	0	4	0	0
T8	0	3657	0	0
T9	0	50	0	0
T10	0	1863	0	0
T11	5318	0	0	0
T12	2934	0	0	0
T13	2996	0	0	0
T14	139873	0	0	0
T15	6396	0	0	0
T16	8570	0	0	0
T17	14424	0	0	0
T18	4058	0	0	0
T19	4945	0	0	0