Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3522333	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

15715033

1

T25

4

T1

95592

T11

214

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7685196	1			T25	1		T1	53779		T11	154
values[0x0]	5677161	1			T25	11		T1	34611		T11	69
values[0x1]	5875009	1			T25	4		T1	34138		T11	67

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2707476	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

16529890

1

T25

5

T1

101075

T11

228

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	68703	1			T1	497		T12	7		T13	1
valid_sources[0x01]	69142	1			T1	510		T12	2		T13	5
valid_sources[0x02]	69222	1			T1	350		T11	1		T12	5
valid_sources[0x03]	67208	1			T1	354		T12	4		T13	5
valid_sources[0x04]	67026	1			T1	385		T11	1		T12	8
valid_sources[0x05]	70433	1			T1	193		T12	2		T13	2
valid_sources[0x06]	68425	1			T25	16		T1	533		T11	2
valid_sources[0x07]	68140	1			T1	241		T12	10		T13	4
valid_sources[0x08]	83538	1			T1	413		T12	4		T13	4
valid_sources[0x09]	73477	1			T1	543		T13	8		T15	1
valid_sources[0x0a]	75052	1			T1	600		T12	5		T13	3
valid_sources[0x0b]	66787	1			T1	400		T11	1		T12	8
valid_sources[0x0c]	64893	1			T1	481		T12	5		T13	7
valid_sources[0x0d]	69322	1			T1	432		T12	5		T13	3
valid_sources[0x0e]	70792	1			T1	496		T12	5		T13	4
valid_sources[0x0f]	72092	1			T1	409		T11	1		T12	9
valid_sources[0x10]	78723	1			T1	140		T12	3		T13	5
valid_sources[0x11]	67512	1			T1	599		T11	15		T12	12
valid_sources[0x12]	74732	1			T1	374		T12	8		T13	4
valid_sources[0x13]	66970	1			T1	565		T12	3		T13	3
valid_sources[0x14]	78120	1			T1	657		T11	1		T12	9
valid_sources[0x15]	72304	1			T1	311		T12	5		T13	4
valid_sources[0x16]	80183	1			T1	665		T11	1		T12	2
valid_sources[0x17]	66963	1			T1	749		T12	3		T13	6
valid_sources[0x18]	75383	1			T1	638		T12	4		T13	4
valid_sources[0x19]	71387	1			T1	240		T12	2		T13	3
valid_sources[0x1a]	73869	1			T1	410		T12	8		T13	3
valid_sources[0x1b]	68878	1			T1	659		T12	4		T13	7
valid_sources[0x1c]	76553	1			T1	637		T12	6		T13	6
valid_sources[0x1d]	68877	1			T1	453		T12	9		T13	5
valid_sources[0x1e]	72095	1			T1	400		T12	15		T13	5
valid_sources[0x1f]	72453	1			T1	641		T11	7		T12	3
valid_sources[0x20]	67765	1			T1	599		T11	5		T12	6
valid_sources[0x21]	76303	1			T1	578		T12	3		T13	9
valid_sources[0x22]	72333	1			T1	377		T12	7		T13	3
valid_sources[0x23]	69326	1			T1	651		T12	8		T13	6
valid_sources[0x24]	75942	1			T1	482		T12	3		T13	2
valid_sources[0x25]	63936	1			T1	572		T12	4		T13	3
valid_sources[0x26]	72215	1			T1	625		T12	4		T13	4
valid_sources[0x27]	68100	1			T1	357		T12	6		T13	5
valid_sources[0x28]	78084	1			T1	470		T11	2		T12	4
valid_sources[0x29]	66005	1			T1	376		T11	1		T12	10
valid_sources[0x2a]	67078	1			T1	396		T12	5		T13	3
valid_sources[0x2b]	69055	1			T1	304		T12	9		T13	7
valid_sources[0x2c]	69738	1			T1	299		T12	9		T13	5
valid_sources[0x2d]	68583	1			T1	411		T12	3		T13	4
valid_sources[0x2e]	65336	1			T1	321		T12	7		T13	8
valid_sources[0x2f]	105746	1			T1	405		T11	11		T12	6
valid_sources[0x30]	78687	1			T1	291		T12	8		T13	3
valid_sources[0x31]	75266	1			T1	353		T12	3		T13	4
valid_sources[0x32]	70099	1			T1	541		T12	6		T13	7
valid_sources[0x33]	74879	1			T1	711		T12	3		T13	7
valid_sources[0x34]	72019	1			T1	423		T12	9		T15	1
valid_sources[0x35]	72810	1			T1	550		T12	9		T13	3
valid_sources[0x36]	70740	1			T1	474		T12	4		T13	6
valid_sources[0x37]	71235	1			T1	461		T11	14		T12	8
valid_sources[0x38]	74699	1			T1	598		T12	7		T13	3
valid_sources[0x39]	77348	1			T1	358		T12	3		T13	8
valid_sources[0x3a]	74057	1			T1	380		T11	2		T12	11
valid_sources[0x3b]	73796	1			T1	302		T12	8		T13	4
valid_sources[0x3c]	64382	1			T1	217		T12	4		T13	6
valid_sources[0x3d]	71978	1			T1	255		T12	10		T13	4
valid_sources[0x3e]	77698	1			T1	533		T12	7		T13	4
valid_sources[0x3f]	69566	1			T1	542		T12	3		T13	11
valid_sources[0x40]	77224	1			T1	659		T12	11		T13	4
valid_sources[0x41]	67891	1			T1	445		T12	2		T13	4
valid_sources[0x42]	72727	1			T1	455		T11	3		T12	2
valid_sources[0x43]	69826	1			T1	756		T12	13		T13	5
valid_sources[0x44]	160364	1			T1	727		T12	3		T13	3
valid_sources[0x45]	67767	1			T1	283		T12	9		T13	4
valid_sources[0x46]	67185	1			T1	579		T12	4		T13	10
valid_sources[0x47]	62812	1			T1	707		T12	10		T13	6
valid_sources[0x48]	68579	1			T1	376		T12	4		T13	5
valid_sources[0x49]	69323	1			T1	452		T11	6		T12	4
valid_sources[0x4a]	71117	1			T1	223		T12	10		T13	8
valid_sources[0x4b]	67909	1			T1	558		T12	9		T13	2
valid_sources[0x4c]	72472	1			T1	240		T12	6		T13	6
valid_sources[0x4d]	70825	1			T1	350		T12	2		T13	3
valid_sources[0x4e]	64300	1			T1	327		T11	4		T12	8
valid_sources[0x4f]	63660	1			T1	490		T12	3		T13	4
valid_sources[0x50]	75886	1			T1	296		T12	4		T13	6
valid_sources[0x51]	71951	1			T1	438		T12	6		T13	6
valid_sources[0x52]	72545	1			T1	429		T12	2		T13	7
valid_sources[0x53]	69649	1			T1	455		T12	8		T13	4
valid_sources[0x54]	71370	1			T1	411		T11	13		T12	2
valid_sources[0x55]	70653	1			T1	626		T12	2		T13	4
valid_sources[0x56]	70050	1			T1	494		T12	12		T13	7
valid_sources[0x57]	74183	1			T1	485		T12	6		T13	4
valid_sources[0x58]	209328	1			T1	417		T12	3		T13	6
valid_sources[0x59]	65221	1			T1	487		T12	4		T13	3
valid_sources[0x5a]	68754	1			T1	362		T12	7		T13	2
valid_sources[0x5b]	71187	1			T1	755		T12	9		T13	3
valid_sources[0x5c]	69319	1			T1	616		T12	9		T13	4
valid_sources[0x5d]	66568	1			T1	593		T11	4		T12	2
valid_sources[0x5e]	74912	1			T1	387		T12	4		T13	2
valid_sources[0x5f]	71968	1			T1	708		T11	9		T12	7
valid_sources[0x60]	71379	1			T1	364		T12	3		T13	3
valid_sources[0x61]	61393	1			T1	380		T12	7		T13	3
valid_sources[0x62]	68086	1			T1	406		T12	4		T13	2
valid_sources[0x63]	67886	1			T1	699		T12	4		T13	3
valid_sources[0x64]	72700	1			T1	561		T12	8		T13	4
valid_sources[0x65]	72755	1			T1	499		T11	4		T12	5
valid_sources[0x66]	112090	1			T1	491		T11	8		T12	4
valid_sources[0x67]	70442	1			T1	691		T12	7		T13	6
valid_sources[0x68]	72240	1			T1	675		T12	6		T13	3
valid_sources[0x69]	71348	1			T1	610		T11	5		T12	5
valid_sources[0x6a]	69620	1			T1	689		T12	4		T13	3
valid_sources[0x6b]	64496	1			T1	583		T12	6		T13	3
valid_sources[0x6c]	72598	1			T1	366		T12	8		T13	1
valid_sources[0x6d]	115784	1			T1	445		T12	4		T13	2
valid_sources[0x6e]	70489	1			T1	630		T12	6		T13	4
valid_sources[0x6f]	96143	1			T1	492		T11	1		T12	6
valid_sources[0x70]	105996	1			T1	713		T12	8		T13	2
valid_sources[0x71]	63398	1			T1	348		T11	14		T12	3
valid_sources[0x72]	69284	1			T1	316		T12	5		T13	6
valid_sources[0x73]	70110	1			T1	379		T12	8		T13	1
valid_sources[0x74]	69085	1			T1	344		T12	6		T13	4
valid_sources[0x75]	68038	1			T1	412		T12	3		T13	5
valid_sources[0x76]	74499	1			T1	446		T11	7		T12	8
valid_sources[0x77]	64505	1			T1	476		T12	6		T13	2
valid_sources[0x78]	71963	1			T1	452		T12	5		T13	4
valid_sources[0x79]	70327	1			T1	357		T11	6		T12	9
valid_sources[0x7a]	70021	1			T1	573		T11	2		T12	9
valid_sources[0x7b]	73272	1			T1	693		T12	2		T13	5
valid_sources[0x7c]	67968	1			T1	401		T12	5		T13	7
valid_sources[0x7d]	72652	1			T1	436		T12	9		T13	5
valid_sources[0x7e]	75488	1			T1	434		T12	2		T13	3
valid_sources[0x7f]	69350	1			T1	240		T12	10		T13	4
valid_sources[0x80]	76384	1			T1	537		T11	1		T12	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4400057

1

T1

26843

T11

78

T12

530

values[0x0]

all_enables

biggest_size

5657007

1

T25

3

T1

34611

T11

69

values[0x1]

all_enables

biggest_size

5657969

1

T25

1

T1

34138

T11

67