Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	156187208	0	0	0
ctrl_en_input_filter_rd_A	156187208	84494	0	0
intr_ctrl_en_falling_rd_A	156187208	86253	0	0
intr_ctrl_en_lvlhigh_rd_A	156187208	84377	0	0
intr_ctrl_en_lvllow_rd_A	156187208	86804	0	0
intr_ctrl_en_rising_rd_A	156187208	83236	0	0
intr_enable_rd_A	156187208	84774	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156187208	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156187208	84494	0	0
T1	146580	3194	0	0
T2	0	2	0	0
T3	0	2812	0	0
T4	0	441	0	0
T5	0	283	0	0
T6	0	3391	0	0
T7	0	135	0	0
T8	0	5819	0	0
T9	0	301	0	0
T10	0	33172	0	0
T11	4689	0	0	0
T12	6382	0	0	0
T13	9116	0	0	0
T14	1367	0	0	0
T15	4422	0	0	0
T16	424828	0	0	0
T17	3047	0	0	0
T18	3092	0	0	0
T19	31126	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156187208	86253	0	0
T1	146580	3254	0	0
T3	0	2788	0	0
T4	0	392	0	0
T5	0	345	0	0
T6	0	3451	0	0
T7	0	224	0	0
T8	0	5673	0	0
T11	4689	0	0	0
T12	6382	0	0	0
T13	9116	0	0	0
T14	1367	0	0	0
T15	4422	0	0	0
T16	424828	0	0	0
T17	3047	0	0	0
T18	3092	0	0	0
T19	31126	0	0	0
T20	0	5	0	0
T21	0	5	0	0
T22	0	6	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156187208	84377	0	0
T1	146580	3459	0	0
T2	0	9	0	0
T3	0	2677	0	0
T4	0	485	0	0
T5	0	272	0	0
T6	0	3501	0	0
T7	0	194	0	0
T11	4689	0	0	0
T12	6382	0	0	0
T13	9116	0	0	0
T14	1367	0	0	0
T15	4422	0	0	0
T16	424828	0	0	0
T17	3047	0	0	0
T18	3092	0	0	0
T19	31126	0	0	0
T20	0	3	0	0
T21	0	2	0	0
T22	0	1	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156187208	86804	0	0
T1	146580	3420	0	0
T2	0	9	0	0
T3	0	2927	0	0
T4	0	495	0	0
T5	0	231	0	0
T6	0	3244	0	0
T7	0	184	0	0
T8	0	5653	0	0
T11	4689	0	0	0
T12	6382	0	0	0
T13	9116	0	0	0
T14	1367	0	0	0
T15	4422	0	0	0
T16	424828	0	0	0
T17	3047	0	0	0
T18	3092	0	0	0
T19	31126	0	0	0
T20	0	10	0	0
T23	0	7	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156187208	83236	0	0
T1	146580	3492	0	0
T2	0	12	0	0
T3	0	2764	0	0
T4	0	396	0	0
T5	0	255	0	0
T6	0	3165	0	0
T7	0	206	0	0
T8	0	5655	0	0
T9	0	243	0	0
T11	4689	0	0	0
T12	6382	0	0	0
T13	9116	0	0	0
T14	1367	0	0	0
T15	4422	0	0	0
T16	424828	0	0	0
T17	3047	0	0	0
T18	3092	0	0	0
T19	31126	0	0	0
T20	0	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156187208	84774	0	0
T1	146580	3097	0	0
T2	0	4	0	0
T3	0	2752	0	0
T4	0	405	0	0
T5	0	295	0	0
T6	0	3191	0	0
T7	0	163	0	0
T8	0	5761	0	0
T11	4689	0	0	0
T12	6382	0	0	0
T13	9116	0	0	0
T14	1367	0	0	0
T15	4422	0	0	0
T16	424828	0	0	0
T17	3047	0	0	0
T18	3092	0	0	0
T19	31126	0	0	0
T22	0	5	0	0
T24	0	2	0	0