Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3219140	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

14323568

1

T23

116

T24

335

T25

275

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7020641	1			T23	22		T24	178		T25	77
values[0x0]	5174750	1			T23	56		T24	108		T25	125
values[0x1]	5347317	1			T23	52		T24	138		T25	118

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2476470	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

15066238

1

T23

118

T24

351

T25

286

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	63467	1			T24	3		T25	1		T11	2506
valid_sources[0x01]	70257	1			T24	4		T25	2		T11	2331
valid_sources[0x02]	64688	1			T11	2455		T14	7		T16	414
valid_sources[0x03]	65296	1			T23	1		T24	1		T25	1
valid_sources[0x04]	67603	1			T24	1		T25	1		T11	2486
valid_sources[0x05]	65108	1			T24	2		T25	2		T26	1
valid_sources[0x06]	63201	1			T24	1		T25	3		T26	1
valid_sources[0x07]	61708	1			T23	1		T24	1		T25	1
valid_sources[0x08]	67759	1			T24	2		T26	1		T11	2603
valid_sources[0x09]	66384	1			T24	1		T25	1		T26	1
valid_sources[0x0a]	109056	1			T24	1		T11	2265		T16	429
valid_sources[0x0b]	64632	1			T25	2		T26	1		T11	2647
valid_sources[0x0c]	69336	1			T24	1		T25	1		T11	2757
valid_sources[0x0d]	64254	1			T24	5		T25	1		T11	2543
valid_sources[0x0e]	62775	1			T24	3		T25	3		T26	1
valid_sources[0x0f]	63204	1			T23	3		T25	1		T26	2
valid_sources[0x10]	68001	1			T24	2		T11	2480		T16	358
valid_sources[0x11]	65148	1			T24	1		T26	2		T11	2540
valid_sources[0x12]	65924	1			T24	3		T25	1		T11	2712
valid_sources[0x13]	63108	1			T25	1		T11	2451		T16	375
valid_sources[0x14]	63166	1			T23	2		T24	1		T26	1
valid_sources[0x15]	62030	1			T23	2		T24	4		T11	2409
valid_sources[0x16]	193066	1			T23	2		T24	3		T25	1
valid_sources[0x17]	178307	1			T25	1		T26	1		T11	2418
valid_sources[0x18]	63643	1			T23	2		T24	2		T25	2
valid_sources[0x19]	65664	1			T23	2		T24	1		T26	1
valid_sources[0x1a]	64898	1			T11	2656		T16	417		T18	407
valid_sources[0x1b]	175209	1			T24	5		T25	1		T11	2411
valid_sources[0x1c]	64626	1			T24	1		T25	1		T11	2247
valid_sources[0x1d]	63968	1			T23	2		T24	3		T25	2
valid_sources[0x1e]	63779	1			T23	1		T24	4		T25	3
valid_sources[0x1f]	64158	1			T24	2		T26	1		T11	2747
valid_sources[0x20]	64854	1			T25	4		T26	1		T11	2769
valid_sources[0x21]	64002	1			T25	2		T11	2646		T16	470
valid_sources[0x22]	63850	1			T23	1		T25	2		T26	1
valid_sources[0x23]	66290	1			T24	2		T25	1		T11	2575
valid_sources[0x24]	67663	1			T23	1		T25	1		T26	1
valid_sources[0x25]	72052	1			T23	2		T24	3		T25	2
valid_sources[0x26]	64663	1			T23	2		T24	1		T25	2
valid_sources[0x27]	65620	1			T24	1		T26	1		T11	2232
valid_sources[0x28]	62463	1			T11	2486		T12	2		T16	410
valid_sources[0x29]	63946	1			T11	2525		T16	453		T18	418
valid_sources[0x2a]	64651	1			T24	3		T25	1		T11	2441
valid_sources[0x2b]	65681	1			T24	5		T25	2		T11	2472
valid_sources[0x2c]	90236	1			T24	1		T26	2		T11	2554
valid_sources[0x2d]	62907	1			T24	2		T25	1		T26	2
valid_sources[0x2e]	63567	1			T26	1		T11	2783		T16	445
valid_sources[0x2f]	105897	1			T24	1		T11	2505		T14	2
valid_sources[0x30]	65054	1			T24	1		T25	3		T26	2
valid_sources[0x31]	64674	1			T24	2		T25	2		T11	2297
valid_sources[0x32]	63243	1			T24	2		T26	1		T11	2470
valid_sources[0x33]	65628	1			T25	1		T11	2263		T16	434
valid_sources[0x34]	62975	1			T11	2297		T14	10		T16	389
valid_sources[0x35]	68167	1			T24	9		T26	2		T11	2789
valid_sources[0x36]	63768	1			T24	1		T11	2728		T14	2
valid_sources[0x37]	62666	1			T24	1		T25	1		T26	1
valid_sources[0x38]	68524	1			T23	1		T24	6		T25	2
valid_sources[0x39]	71303	1			T24	1		T25	2		T26	2
valid_sources[0x3a]	62760	1			T24	1		T25	1		T11	2535
valid_sources[0x3b]	63739	1			T23	1		T25	3		T26	1
valid_sources[0x3c]	66766	1			T23	1		T25	5		T11	2698
valid_sources[0x3d]	65135	1			T23	1		T24	5		T25	1
valid_sources[0x3e]	64142	1			T23	1		T25	1		T26	1
valid_sources[0x3f]	61517	1			T23	1		T24	1		T11	2469
valid_sources[0x40]	67756	1			T24	2		T11	2462		T16	398
valid_sources[0x41]	62675	1			T23	1		T24	1		T25	1
valid_sources[0x42]	64618	1			T24	1		T25	1		T26	1
valid_sources[0x43]	63457	1			T24	3		T25	3		T26	4
valid_sources[0x44]	63180	1			T23	1		T24	1		T25	1
valid_sources[0x45]	66151	1			T23	2		T25	1		T11	2673
valid_sources[0x46]	63973	1			T24	2		T25	1		T26	1
valid_sources[0x47]	65873	1			T24	2		T25	1		T11	2743
valid_sources[0x48]	65046	1			T23	3		T24	4		T11	2581
valid_sources[0x49]	63273	1			T23	2		T24	2		T11	2652
valid_sources[0x4a]	64195	1			T24	1		T11	2598		T16	459
valid_sources[0x4b]	63437	1			T25	1		T11	2543		T16	490
valid_sources[0x4c]	66661	1			T24	2		T11	2513		T16	477
valid_sources[0x4d]	64540	1			T25	2		T11	2557		T14	10
valid_sources[0x4e]	61228	1			T23	1		T24	4		T25	1
valid_sources[0x4f]	63251	1			T24	1		T11	2691		T16	374
valid_sources[0x50]	70808	1			T23	1		T24	1		T26	1
valid_sources[0x51]	62299	1			T25	1		T11	2566		T16	431
valid_sources[0x52]	63995	1			T24	1		T25	4		T11	2438
valid_sources[0x53]	64206	1			T24	1		T25	1		T11	2331
valid_sources[0x54]	64853	1			T25	1		T26	2		T11	2453
valid_sources[0x55]	63951	1			T25	1		T26	1		T11	2451
valid_sources[0x56]	64672	1			T24	1		T25	2		T26	2
valid_sources[0x57]	62923	1			T25	1		T26	2		T11	2736
valid_sources[0x58]	63357	1			T23	1		T11	2391		T14	1
valid_sources[0x59]	66243	1			T24	2		T25	1		T26	1
valid_sources[0x5a]	68884	1			T23	2		T24	1		T26	1
valid_sources[0x5b]	65977	1			T24	1		T25	1		T26	1
valid_sources[0x5c]	64010	1			T25	2		T26	1		T11	2701
valid_sources[0x5d]	64546	1			T24	1		T25	1		T11	2630
valid_sources[0x5e]	63111	1			T23	1		T25	2		T11	2633
valid_sources[0x5f]	64160	1			T24	5		T26	1		T11	2555
valid_sources[0x60]	63598	1			T23	1		T24	1		T25	1
valid_sources[0x61]	67901	1			T24	1		T25	1		T11	2437
valid_sources[0x62]	133436	1			T23	1		T24	1		T25	1
valid_sources[0x63]	65342	1			T24	2		T25	1		T11	2267
valid_sources[0x64]	63085	1			T24	1		T11	2561		T16	401
valid_sources[0x65]	70095	1			T23	2		T25	1		T26	3
valid_sources[0x66]	63988	1			T23	2		T24	1		T25	2
valid_sources[0x67]	65360	1			T24	4		T25	3		T26	2
valid_sources[0x68]	65000	1			T24	2		T25	2		T11	2621
valid_sources[0x69]	69080	1			T23	1		T11	2454		T14	2
valid_sources[0x6a]	69129	1			T23	1		T24	2		T25	1
valid_sources[0x6b]	65355	1			T25	1		T11	2411		T16	376
valid_sources[0x6c]	63360	1			T24	2		T25	1		T11	2608
valid_sources[0x6d]	65724	1			T23	1		T25	2		T11	2597
valid_sources[0x6e]	66398	1			T24	1		T11	2328		T15	14
valid_sources[0x6f]	63325	1			T25	1		T11	2579		T15	17
valid_sources[0x70]	64625	1			T24	3		T11	2410		T16	427
valid_sources[0x71]	63160	1			T24	1		T25	2		T11	2339
valid_sources[0x72]	65493	1			T23	2		T24	1		T25	1
valid_sources[0x73]	70276	1			T24	5		T25	1		T11	2632
valid_sources[0x74]	65370	1			T24	3		T25	1		T11	2481
valid_sources[0x75]	63579	1			T24	1		T25	1		T11	2665
valid_sources[0x76]	65788	1			T25	4		T26	1		T11	2784
valid_sources[0x77]	64240	1			T25	1		T11	2610		T16	432
valid_sources[0x78]	66216	1			T24	7		T25	5		T11	2340
valid_sources[0x79]	68867	1			T23	1		T24	4		T25	2
valid_sources[0x7a]	68288	1			T24	3		T11	2320		T16	361
valid_sources[0x7b]	65247	1			T25	1		T26	2		T11	2609
valid_sources[0x7c]	68363	1			T24	3		T25	1		T11	2401
valid_sources[0x7d]	67987	1			T23	1		T25	1		T11	2182
valid_sources[0x7e]	69508	1			T23	1		T24	3		T11	2403
valid_sources[0x7f]	63945	1			T24	1		T11	2522		T13	2
valid_sources[0x80]	65249	1			T23	1		T24	7		T25	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4012600

1

T23

8

T24

89

T25

32

values[0x0]

all_enables

biggest_size

5156918

1

T23

56

T24

108

T25

125

values[0x1]

all_enables

biggest_size

5154050

1

T23

52

T24

138

T25

118