Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	151369282	0	0	0
ctrl_en_input_filter_rd_A	151369282	101342	0	0
intr_ctrl_en_falling_rd_A	151369282	103329	0	0
intr_ctrl_en_lvlhigh_rd_A	151369282	99097	0	0
intr_ctrl_en_lvllow_rd_A	151369282	103839	0	0
intr_ctrl_en_rising_rd_A	151369282	98069	0	0
intr_enable_rd_A	151369282	99991	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151369282	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151369282	101342	0	0
T1	5603	67	0	0
T2	0	4	0	0
T3	0	4164	0	0
T4	0	4	0	0
T5	0	310	0	0
T6	0	94	0	0
T7	0	9024	0	0
T8	0	1809	0	0
T9	0	3804	0	0
T10	0	196	0	0
T11	464174	0	0	0
T12	1321	0	0	0
T13	1059	0	0	0
T14	2942	0	0	0
T15	2839	0	0	0
T16	497161	0	0	0
T17	2987	0	0	0
T18	961476	0	0	0
T19	3529	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151369282	103329	0	0
T1	5603	57	0	0
T3	0	3722	0	0
T5	0	315	0	0
T6	0	109	0	0
T7	0	9387	0	0
T8	0	1819	0	0
T9	0	3929	0	0
T10	0	229	0	0
T11	464174	0	0	0
T12	1321	0	0	0
T13	1059	0	0	0
T14	2942	0	0	0
T15	2839	0	0	0
T16	497161	0	0	0
T17	2987	0	0	0
T18	961476	0	0	0
T19	3529	0	0	0
T20	0	3707	0	0
T21	0	1928	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151369282	99097	0	0
T1	5603	33	0	0
T2	0	3	0	0
T3	0	3796	0	0
T4	0	4	0	0
T5	0	313	0	0
T6	0	92	0	0
T7	0	8743	0	0
T8	0	1870	0	0
T9	0	3829	0	0
T10	0	255	0	0
T11	464174	0	0	0
T12	1321	0	0	0
T13	1059	0	0	0
T14	2942	0	0	0
T15	2839	0	0	0
T16	497161	0	0	0
T17	2987	0	0	0
T18	961476	0	0	0
T19	3529	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151369282	103839	0	0
T1	5603	20	0	0
T3	0	3539	0	0
T5	0	325	0	0
T6	0	90	0	0
T7	0	9517	0	0
T8	0	1839	0	0
T9	0	3655	0	0
T10	0	330	0	0
T11	464174	0	0	0
T12	1321	0	0	0
T13	1059	0	0	0
T14	2942	0	0	0
T15	2839	0	0	0
T16	497161	0	0	0
T17	2987	0	0	0
T18	961476	0	0	0
T19	3529	0	0	0
T20	0	3559	0	0
T22	0	5	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151369282	98069	0	0
T1	5603	49	0	0
T3	0	3807	0	0
T4	0	8	0	0
T5	0	325	0	0
T6	0	71	0	0
T7	0	8156	0	0
T8	0	1766	0	0
T9	0	3953	0	0
T10	0	320	0	0
T11	464174	0	0	0
T12	1321	0	0	0
T13	1059	0	0	0
T14	2942	0	0	0
T15	2839	0	0	0
T16	497161	0	0	0
T17	2987	0	0	0
T18	961476	0	0	0
T19	3529	0	0	0
T22	0	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151369282	99991	0	0
T1	5603	37	0	0
T3	0	4102	0	0
T5	0	274	0	0
T6	0	106	0	0
T7	0	9111	0	0
T8	0	1918	0	0
T9	0	3771	0	0
T10	0	305	0	0
T11	464174	0	0	0
T12	1321	0	0	0
T13	1059	0	0	0
T14	2942	0	0	0
T15	2839	0	0	0
T16	497161	0	0	0
T17	2987	0	0	0
T18	961476	0	0	0
T19	3529	0	0	0
T20	0	3669	0	0
T21	0	1764	0	0