Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3534756	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

15461234

1

T23

1

T24

241

T25

97105

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7664625	1			T23	1		T24	25		T25	53649
values[0x0]	5578367	1			T24	118		T25	35370		T26	354
values[0x1]	5752998	1			T24	111		T25	35028		T26	356

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2729595	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

16266395

1

T23

1

T24

243

T25

102434

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	191963	1			T25	124047		T29	1473		T31	4
valid_sources[0x01]	73098	1			T29	1412		T32	2		T11	3800
valid_sources[0x02]	72046	1			T29	1524		T1	22		T11	3772
valid_sources[0x03]	72732	1			T29	1447		T32	3		T1	8
valid_sources[0x04]	67412	1			T29	1360		T31	3		T1	4
valid_sources[0x05]	67715	1			T29	1349		T11	3791		T13	1
valid_sources[0x06]	73823	1			T29	1430		T31	5		T32	3
valid_sources[0x07]	66993	1			T29	1393		T32	5		T1	3
valid_sources[0x08]	67215	1			T29	1428		T32	2		T11	3722
valid_sources[0x09]	67771	1			T29	1484		T32	2		T11	3839
valid_sources[0x0a]	61430	1			T29	1446		T11	3797		T13	4
valid_sources[0x0b]	99606	1			T29	1531		T30	19		T31	6
valid_sources[0x0c]	71695	1			T29	1439		T32	1		T11	3805
valid_sources[0x0d]	69249	1			T29	1542		T31	2		T32	1
valid_sources[0x0e]	65755	1			T29	1404		T1	5		T11	3958
valid_sources[0x0f]	65965	1			T29	1308		T1	5		T11	3889
valid_sources[0x10]	65672	1			T29	1419		T32	1		T11	3745
valid_sources[0x11]	75565	1			T29	1530		T30	18		T1	2
valid_sources[0x12]	67306	1			T29	1464		T11	3996		T15	21
valid_sources[0x13]	65064	1			T29	1436		T11	3828		T14	10
valid_sources[0x14]	68879	1			T29	1451		T32	3		T1	8
valid_sources[0x15]	65169	1			T29	1509		T1	4		T11	3934
valid_sources[0x16]	68367	1			T29	1612		T11	3992		T14	4
valid_sources[0x17]	67741	1			T23	1		T29	1456		T32	1
valid_sources[0x18]	67963	1			T29	1420		T1	1		T11	3789
valid_sources[0x19]	67287	1			T29	1370		T31	1		T11	3915
valid_sources[0x1a]	76548	1			T29	1391		T1	10		T11	3920
valid_sources[0x1b]	68797	1			T29	1424		T31	6		T32	2
valid_sources[0x1c]	67597	1			T29	1422		T31	1		T1	10
valid_sources[0x1d]	72065	1			T29	1321		T1	7		T11	3790
valid_sources[0x1e]	70499	1			T29	1356		T31	3		T1	15
valid_sources[0x1f]	68281	1			T29	1447		T1	5		T11	3980
valid_sources[0x20]	74441	1			T29	1386		T32	3		T11	3892
valid_sources[0x21]	65364	1			T29	1384		T11	3985		T13	1
valid_sources[0x22]	74422	1			T29	1428		T1	10		T11	3875
valid_sources[0x23]	75997	1			T29	1471		T11	3871		T13	1
valid_sources[0x24]	66992	1			T29	1428		T31	1		T11	3829
valid_sources[0x25]	67144	1			T29	1380		T31	2		T32	3
valid_sources[0x26]	63509	1			T29	1490		T1	12		T11	3794
valid_sources[0x27]	66044	1			T29	1368		T32	1		T11	3677
valid_sources[0x28]	64183	1			T29	1347		T32	1		T11	3890
valid_sources[0x29]	70072	1			T29	1421		T31	3		T11	3744
valid_sources[0x2a]	68596	1			T29	1413		T32	1		T11	4006
valid_sources[0x2b]	63278	1			T29	1427		T31	1		T32	5
valid_sources[0x2c]	72277	1			T29	1357		T32	1		T1	4
valid_sources[0x2d]	63441	1			T29	1408		T11	3926		T13	4
valid_sources[0x2e]	72774	1			T29	1562		T31	3		T1	11
valid_sources[0x2f]	109588	1			T29	1503		T32	1		T1	2
valid_sources[0x30]	70046	1			T29	1558		T31	2		T32	4
valid_sources[0x31]	68370	1			T29	1547		T31	2		T1	13
valid_sources[0x32]	168878	1			T29	1327		T32	6		T11	3916
valid_sources[0x33]	170929	1			T29	1447		T1	21		T11	3964
valid_sources[0x34]	188276	1			T29	1569		T30	19		T32	3
valid_sources[0x35]	69592	1			T29	1368		T11	3838		T13	1
valid_sources[0x36]	67118	1			T29	1405		T1	10		T11	3975
valid_sources[0x37]	68940	1			T29	1496		T32	3		T11	3970
valid_sources[0x38]	68261	1			T29	1441		T31	1		T11	3790
valid_sources[0x39]	69629	1			T29	1399		T30	10		T1	6
valid_sources[0x3a]	68775	1			T29	1548		T31	9		T1	8
valid_sources[0x3b]	66344	1			T29	1386		T1	1		T11	3749
valid_sources[0x3c]	67267	1			T29	1418		T32	4		T11	3784
valid_sources[0x3d]	70442	1			T29	1461		T1	21		T11	3813
valid_sources[0x3e]	66344	1			T29	1391		T11	3782		T14	2
valid_sources[0x3f]	63905	1			T29	1340		T1	2		T11	3886
valid_sources[0x40]	68746	1			T29	1326		T32	2		T11	3920
valid_sources[0x41]	67643	1			T29	1447		T32	5		T11	3823
valid_sources[0x42]	64039	1			T29	1451		T1	3		T11	3944
valid_sources[0x43]	78378	1			T29	1428		T31	2		T32	1
valid_sources[0x44]	67903	1			T29	1411		T31	3		T32	1
valid_sources[0x45]	71206	1			T29	1413		T32	2		T1	20
valid_sources[0x46]	71703	1			T29	1536		T11	3850		T14	1
valid_sources[0x47]	67180	1			T29	1374		T1	7		T11	4028
valid_sources[0x48]	65092	1			T29	1458		T31	2		T1	7
valid_sources[0x49]	66017	1			T29	1385		T1	2		T11	3838
valid_sources[0x4a]	63965	1			T29	1362		T11	3813		T15	15
valid_sources[0x4b]	66797	1			T29	1320		T1	2		T11	4095
valid_sources[0x4c]	224488	1			T29	1396		T32	1		T11	3887
valid_sources[0x4d]	68628	1			T29	1436		T32	1		T1	4
valid_sources[0x4e]	67419	1			T29	1397		T1	22		T11	3695
valid_sources[0x4f]	63983	1			T29	1430		T1	7		T11	3874
valid_sources[0x50]	63519	1			T29	1458		T11	3763		T13	2
valid_sources[0x51]	72636	1			T29	1414		T31	1		T1	15
valid_sources[0x52]	67009	1			T29	1472		T1	3		T11	3915
valid_sources[0x53]	73202	1			T29	1399		T32	2		T1	2
valid_sources[0x54]	66268	1			T29	1478		T31	1		T11	3925
valid_sources[0x55]	67703	1			T29	1506		T32	4		T1	5
valid_sources[0x56]	68455	1			T29	1482		T31	4		T11	3787
valid_sources[0x57]	86385	1			T29	1476		T30	16		T32	3
valid_sources[0x58]	63517	1			T29	1321		T1	3		T11	3770
valid_sources[0x59]	66125	1			T29	1429		T1	7		T11	3785
valid_sources[0x5a]	74346	1			T29	1541		T32	1		T1	2
valid_sources[0x5b]	65764	1			T29	1440		T32	1		T11	3904
valid_sources[0x5c]	72018	1			T29	1396		T11	3942		T13	2
valid_sources[0x5d]	69046	1			T29	1347		T1	1		T11	3807
valid_sources[0x5e]	67386	1			T29	1383		T11	3711		T13	1
valid_sources[0x5f]	64566	1			T29	1465		T1	4		T11	3944
valid_sources[0x60]	66648	1			T29	1474		T1	16		T11	3900
valid_sources[0x61]	117484	1			T29	1381		T11	3968		T13	1
valid_sources[0x62]	64853	1			T29	1509		T11	3931		T14	5
valid_sources[0x63]	68472	1			T29	1453		T32	8		T1	13
valid_sources[0x64]	198486	1			T29	1414		T1	17		T11	3873
valid_sources[0x65]	66577	1			T29	1342		T31	1		T11	3969
valid_sources[0x66]	68911	1			T29	1438		T32	1		T1	6
valid_sources[0x67]	69774	1			T29	1327		T30	17		T11	3965
valid_sources[0x68]	68589	1			T29	1458		T1	10		T11	3808
valid_sources[0x69]	66669	1			T29	1527		T11	3930		T14	1
valid_sources[0x6a]	67189	1			T29	1455		T32	2		T11	3951
valid_sources[0x6b]	67274	1			T29	1458		T31	3		T1	4
valid_sources[0x6c]	69608	1			T29	1468		T11	3845		T15	17
valid_sources[0x6d]	69444	1			T29	1426		T31	6		T1	4
valid_sources[0x6e]	67301	1			T29	1366		T1	2		T11	3871
valid_sources[0x6f]	66981	1			T29	1584		T11	3783		T13	1
valid_sources[0x70]	66149	1			T29	1436		T31	11		T1	34
valid_sources[0x71]	74049	1			T29	1476		T31	4		T32	2
valid_sources[0x72]	65708	1			T29	1432		T32	1		T11	3849
valid_sources[0x73]	73900	1			T29	1458		T31	1		T11	3677
valid_sources[0x74]	69519	1			T29	1409		T1	11		T11	3775
valid_sources[0x75]	68984	1			T29	1387		T1	4		T11	3802
valid_sources[0x76]	69512	1			T29	1522		T1	9		T11	3775
valid_sources[0x77]	68473	1			T29	1462		T30	59		T31	1
valid_sources[0x78]	66635	1			T29	1368		T32	1		T11	3954
valid_sources[0x79]	69785	1			T29	1389		T1	9		T11	3792
valid_sources[0x7a]	71533	1			T29	1351		T11	3919		T13	1
valid_sources[0x7b]	64835	1			T29	1575		T32	1		T11	3645
valid_sources[0x7c]	77274	1			T29	1464		T31	3		T11	3897
valid_sources[0x7d]	70993	1			T29	1393		T32	1		T11	3769
valid_sources[0x7e]	100470	1			T29	1420		T11	3906		T14	1
valid_sources[0x7f]	69928	1			T29	1345		T31	6		T11	3759
valid_sources[0x80]	68314	1			T29	1447		T11	3818		T14	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4345109

1

T23

1

T24

12

T25

26707

values[0x0]

all_enables

biggest_size

5560123

1

T24

118

T25

35370

T26

354

values[0x1]

all_enables

biggest_size

5556002

1

T24

111

T25

35028

T26

356