Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	147310699	0	0	0
ctrl_en_input_filter_rd_A	147310699	63154	0	0
intr_ctrl_en_falling_rd_A	147310699	64291	0	0
intr_ctrl_en_lvlhigh_rd_A	147310699	63112	0	0
intr_ctrl_en_lvllow_rd_A	147310699	64380	0	0
intr_ctrl_en_rising_rd_A	147310699	62888	0	0
intr_enable_rd_A	147310699	62319	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147310699	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147310699	63154	0	0
T1	11622	47	0	0
T2	0	985	0	0
T3	0	1387	0	0
T4	0	17012	0	0
T5	0	67	0	0
T6	0	2894	0	0
T7	0	1	0	0
T8	0	110	0	0
T9	0	2062	0	0
T10	0	6755	0	0
T11	727668	0	0	0
T12	5227	0	0	0
T13	3218	0	0	0
T14	3337	0	0	0
T15	50380	0	0	0
T16	6951	0	0	0
T17	1482	0	0	0
T18	29214	0	0	0
T19	1759	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147310699	64291	0	0
T1	11622	63	0	0
T2	0	1020	0	0
T3	0	1178	0	0
T4	0	17803	0	0
T5	0	59	0	0
T6	0	2653	0	0
T7	0	1	0	0
T8	0	57	0	0
T11	727668	0	0	0
T12	5227	0	0	0
T13	3218	0	0	0
T14	3337	0	0	0
T15	50380	0	0	0
T16	6951	0	0	0
T17	1482	0	0	0
T18	29214	0	0	0
T19	1759	0	0	0
T20	0	14	0	0
T21	0	9	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147310699	63112	0	0
T1	11622	27	0	0
T2	0	994	0	0
T3	0	1303	0	0
T4	0	16901	0	0
T5	0	28	0	0
T6	0	2457	0	0
T7	0	4	0	0
T8	0	82	0	0
T11	727668	0	0	0
T12	5227	0	0	0
T13	3218	0	0	0
T14	3337	0	0	0
T15	50380	0	0	0
T16	6951	0	0	0
T17	1482	0	0	0
T18	29214	0	0	0
T19	1759	0	0	0
T21	0	4	0	0
T22	0	11	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147310699	64380	0	0
T1	11622	44	0	0
T2	0	996	0	0
T3	0	1403	0	0
T4	0	17547	0	0
T5	0	39	0	0
T6	0	2526	0	0
T7	0	14	0	0
T8	0	84	0	0
T11	727668	0	0	0
T12	5227	0	0	0
T13	3218	0	0	0
T14	3337	0	0	0
T15	50380	0	0	0
T16	6951	0	0	0
T17	1482	0	0	0
T18	29214	0	0	0
T19	1759	0	0	0
T20	0	17	0	0
T22	0	1	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147310699	62888	0	0
T1	11622	60	0	0
T2	0	1040	0	0
T3	0	1298	0	0
T4	0	16609	0	0
T5	0	53	0	0
T6	0	2504	0	0
T7	0	2	0	0
T8	0	72	0	0
T11	727668	0	0	0
T12	5227	0	0	0
T13	3218	0	0	0
T14	3337	0	0	0
T15	50380	0	0	0
T16	6951	0	0	0
T17	1482	0	0	0
T18	29214	0	0	0
T19	1759	0	0	0
T20	0	5	0	0
T21	0	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147310699	62319	0	0
T1	11622	38	0	0
T2	0	1024	0	0
T3	0	1317	0	0
T4	0	16850	0	0
T5	0	74	0	0
T6	0	2433	0	0
T7	0	10	0	0
T11	727668	0	0	0
T12	5227	0	0	0
T13	3218	0	0	0
T14	3337	0	0	0
T15	50380	0	0	0
T16	6951	0	0	0
T17	1482	0	0	0
T18	29214	0	0	0
T19	1759	0	0	0
T20	0	2	0	0
T21	0	8	0	0
T22	0	12	0	0