Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	93744580	0	0	0
ctrl_en_input_filter_rd_A	93744580	73864	0	0
intr_ctrl_en_falling_rd_A	93744580	74340	0	0
intr_ctrl_en_lvlhigh_rd_A	93744580	74644	0	0
intr_ctrl_en_lvllow_rd_A	93744580	75747	0	0
intr_ctrl_en_rising_rd_A	93744580	74838	0	0
intr_enable_rd_A	93744580	72883	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93744580	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93744580	73864	0	0
T1	12931	55	0	0
T2	0	1	0	0
T3	0	9	0	0
T4	0	4232	0	0
T5	0	4672	0	0
T6	0	1832	0	0
T7	0	510	0	0
T8	0	3645	0	0
T9	0	80	0	0
T10	0	631	0	0
T11	6666	0	0	0
T12	2019	0	0	0
T13	7549	0	0	0
T14	4208	0	0	0
T15	117809	0	0	0
T16	2530	0	0	0
T17	1965	0	0	0
T18	3569	0	0	0
T19	2174	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93744580	74340	0	0
T1	12931	90	0	0
T2	0	4	0	0
T3	0	5	0	0
T4	0	4181	0	0
T5	0	4748	0	0
T6	0	1660	0	0
T7	0	588	0	0
T8	0	3761	0	0
T9	0	49	0	0
T10	0	534	0	0
T11	6666	0	0	0
T12	2019	0	0	0
T13	7549	0	0	0
T14	4208	0	0	0
T15	117809	0	0	0
T16	2530	0	0	0
T17	1965	0	0	0
T18	3569	0	0	0
T19	2174	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93744580	74644	0	0
T1	12931	79	0	0
T4	0	4187	0	0
T5	0	4594	0	0
T6	0	1855	0	0
T7	0	631	0	0
T8	0	3747	0	0
T9	0	84	0	0
T10	0	627	0	0
T11	6666	0	0	0
T12	2019	0	0	0
T13	7549	0	0	0
T14	4208	0	0	0
T15	117809	0	0	0
T16	2530	0	0	0
T17	1965	0	0	0
T18	3569	0	0	0
T19	2174	0	0	0
T20	0	6	0	0
T21	0	230	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93744580	75747	0	0
T1	12931	85	0	0
T3	0	8	0	0
T4	0	4260	0	0
T5	0	4657	0	0
T6	0	1873	0	0
T7	0	575	0	0
T8	0	4123	0	0
T9	0	68	0	0
T10	0	576	0	0
T11	6666	0	0	0
T12	2019	0	0	0
T13	7549	0	0	0
T14	4208	0	0	0
T15	117809	0	0	0
T16	2530	0	0	0
T17	1965	0	0	0
T18	3569	0	0	0
T19	2174	0	0	0
T20	0	12	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93744580	74838	0	0
T1	12931	55	0	0
T2	0	9	0	0
T3	0	10	0	0
T4	0	4180	0	0
T5	0	4797	0	0
T6	0	1822	0	0
T7	0	578	0	0
T8	0	3847	0	0
T9	0	52	0	0
T11	6666	0	0	0
T12	2019	0	0	0
T13	7549	0	0	0
T14	4208	0	0	0
T15	117809	0	0	0
T16	2530	6	0	0
T17	1965	0	0	0
T18	3569	0	0	0
T19	2174	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93744580	72883	0	0
T1	12931	83	0	0
T2	0	1	0	0
T4	0	4224	0	0
T5	0	4307	0	0
T6	0	1808	0	0
T7	0	569	0	0
T8	0	3588	0	0
T9	0	45	0	0
T10	0	546	0	0
T11	6666	0	0	0
T12	2019	0	0	0
T13	7549	0	0	0
T14	4208	0	0	0
T15	117809	0	0	0
T16	2530	0	0	0
T17	1965	0	0	0
T18	3569	0	0	0
T19	2174	0	0	0
T21	0	244	0	0