Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2928297	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

12764867

1

T20

1436

T21

418

T22

195

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	6348366	1			T20	1719		T21	199		T22	37
values[0x0]	4597288	1			T20	284		T21	166		T22	96
values[0x1]	4747510	1			T20	275		T21	140		T22	84

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2260086	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

13433078

1

T20

1607

T21

436

T22

199

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	58381	1			T20	23		T21	2		T25	4
valid_sources[0x01]	57737	1			T20	14		T21	1		T22	2
valid_sources[0x02]	61755	1			T20	4		T21	1		T27	1
valid_sources[0x03]	54849	1			T21	3		T22	1		T27	1
valid_sources[0x04]	59044	1			T20	12		T21	2		T22	2
valid_sources[0x05]	56972	1			T20	12		T21	1		T22	1
valid_sources[0x06]	57889	1			T20	4		T21	3		T22	2
valid_sources[0x07]	55723	1			T20	10		T21	1		T22	4
valid_sources[0x08]	146553	1			T20	11		T21	1		T23	1
valid_sources[0x09]	55740	1			T20	6		T21	2		T25	2
valid_sources[0x0a]	61279	1			T20	9		T21	1		T22	2
valid_sources[0x0b]	54640	1			T20	5		T21	3		T25	1
valid_sources[0x0c]	52010	1			T20	3		T23	3		T27	1
valid_sources[0x0d]	57094	1			T20	7		T25	1		T28	9
valid_sources[0x0e]	52902	1			T20	15		T21	1		T23	3
valid_sources[0x0f]	63079	1			T20	10		T21	4		T22	8
valid_sources[0x10]	53219	1			T20	4		T21	6		T28	7
valid_sources[0x11]	54965	1			T20	14		T21	1		T22	1
valid_sources[0x12]	63143	1			T20	8		T21	1		T27	1
valid_sources[0x13]	56408	1			T20	9		T21	9		T28	7
valid_sources[0x14]	57831	1			T22	1		T23	2		T25	1
valid_sources[0x15]	51548	1			T20	8		T21	4		T23	1
valid_sources[0x16]	56085	1			T20	14		T21	3		T23	1
valid_sources[0x17]	60482	1			T20	13		T21	5		T25	1
valid_sources[0x18]	55228	1			T20	2		T21	1		T27	1
valid_sources[0x19]	58424	1			T20	13		T21	4		T22	1
valid_sources[0x1a]	58472	1			T20	4		T21	1		T27	2
valid_sources[0x1b]	54820	1			T20	6		T21	2		T22	2
valid_sources[0x1c]	54589	1			T20	5		T21	3		T22	1
valid_sources[0x1d]	59368	1			T20	5		T21	2		T22	1
valid_sources[0x1e]	55920	1			T20	2		T21	1		T22	1
valid_sources[0x1f]	51440	1			T20	7		T21	5		T22	1
valid_sources[0x20]	56420	1			T20	5		T21	5		T25	1
valid_sources[0x21]	59733	1			T20	7		T21	1		T22	2
valid_sources[0x22]	62933	1			T21	4		T22	4		T23	1
valid_sources[0x23]	53181	1			T20	17		T21	3		T25	1
valid_sources[0x24]	56864	1			T20	15		T22	2		T23	1
valid_sources[0x25]	63176	1			T20	12		T21	5		T22	2
valid_sources[0x26]	52104	1			T20	12		T21	2		T22	1
valid_sources[0x27]	52895	1			T20	12		T22	1		T23	2
valid_sources[0x28]	56091	1			T20	21		T21	3		T25	2
valid_sources[0x29]	52633	1			T20	9		T28	8		T29	1929
valid_sources[0x2a]	61061	1			T20	6		T21	1		T23	1
valid_sources[0x2b]	63782	1			T20	8		T21	4		T22	2
valid_sources[0x2c]	56079	1			T20	15		T22	1		T27	3
valid_sources[0x2d]	58071	1			T20	6		T21	1		T22	1
valid_sources[0x2e]	61446	1			T20	15		T21	1		T22	2
valid_sources[0x2f]	69622	1			T20	3		T21	1		T25	1
valid_sources[0x30]	55160	1			T20	5		T21	1		T27	2
valid_sources[0x31]	58410	1			T20	16		T21	2		T22	2
valid_sources[0x32]	54208	1			T20	5		T21	1		T23	2
valid_sources[0x33]	55662	1			T20	15		T21	1		T22	2
valid_sources[0x34]	55040	1			T20	5		T21	3		T25	1
valid_sources[0x35]	56241	1			T20	4		T21	1		T25	1
valid_sources[0x36]	54003	1			T20	5		T21	1		T22	3
valid_sources[0x37]	57727	1			T20	6		T21	3		T23	2
valid_sources[0x38]	51482	1			T20	10		T21	4		T22	2
valid_sources[0x39]	56266	1			T20	3		T21	1		T23	1
valid_sources[0x3a]	59989	1			T20	8		T21	1		T28	6
valid_sources[0x3b]	145776	1			T20	6		T21	1		T22	2
valid_sources[0x3c]	56497	1			T20	11		T21	1		T23	2
valid_sources[0x3d]	56617	1			T20	3		T21	1		T22	2
valid_sources[0x3e]	58715	1			T20	10		T21	4		T22	2
valid_sources[0x3f]	55631	1			T20	6		T21	1		T22	1
valid_sources[0x40]	51993	1			T20	2		T21	2		T22	1
valid_sources[0x41]	57431	1			T20	15		T21	3		T22	2
valid_sources[0x42]	56379	1			T20	3		T21	4		T25	3
valid_sources[0x43]	53581	1			T20	5		T21	3		T27	1
valid_sources[0x44]	58714	1			T20	10		T21	1		T22	1
valid_sources[0x45]	55514	1			T20	12		T21	1		T27	2
valid_sources[0x46]	57541	1			T20	2		T27	1		T28	9
valid_sources[0x47]	53340	1			T20	9		T21	2		T22	1
valid_sources[0x48]	51520	1			T20	7		T21	4		T22	1
valid_sources[0x49]	59854	1			T20	2		T21	2		T22	1
valid_sources[0x4a]	55160	1			T20	34		T21	1		T28	7
valid_sources[0x4b]	61041	1			T20	10		T21	6		T22	1
valid_sources[0x4c]	58749	1			T20	15		T21	2		T25	1
valid_sources[0x4d]	54475	1			T20	18		T21	1		T27	2
valid_sources[0x4e]	59514	1			T20	3		T23	1		T25	1
valid_sources[0x4f]	56158	1			T20	12		T21	1		T25	2
valid_sources[0x50]	57772	1			T20	4		T22	2		T23	1
valid_sources[0x51]	71467	1			T20	10		T21	4		T22	1
valid_sources[0x52]	65247	1			T20	3		T22	1		T27	3
valid_sources[0x53]	57010	1			T20	15		T21	4		T22	2
valid_sources[0x54]	57183	1			T20	2		T21	1		T22	1
valid_sources[0x55]	58293	1			T20	7		T25	1		T28	3
valid_sources[0x56]	56058	1			T20	20		T21	2		T23	1
valid_sources[0x57]	55609	1			T21	1		T22	4		T23	1
valid_sources[0x58]	60181	1			T20	15		T21	2		T23	1
valid_sources[0x59]	56055	1			T20	17		T21	3		T27	2
valid_sources[0x5a]	56160	1			T20	14		T21	7		T23	2
valid_sources[0x5b]	54803	1			T20	3		T21	5		T22	2
valid_sources[0x5c]	56287	1			T20	2		T21	3		T22	2
valid_sources[0x5d]	53940	1			T20	8		T21	5		T22	2
valid_sources[0x5e]	56529	1			T20	23		T21	2		T23	2
valid_sources[0x5f]	53467	1			T20	5		T21	1		T25	1
valid_sources[0x60]	55906	1			T20	8		T21	3		T22	3
valid_sources[0x61]	60115	1			T20	8		T21	3		T23	2
valid_sources[0x62]	59270	1			T20	13		T21	1		T22	1
valid_sources[0x63]	163306	1			T20	2		T21	5		T22	1
valid_sources[0x64]	53283	1			T20	7		T21	3		T22	2
valid_sources[0x65]	54126	1			T20	4		T22	1		T23	1
valid_sources[0x66]	52936	1			T20	11		T28	9		T29	2174
valid_sources[0x67]	58611	1			T20	4		T21	3		T22	3
valid_sources[0x68]	56163	1			T20	12		T21	4		T22	1
valid_sources[0x69]	58516	1			T20	9		T21	3		T28	7
valid_sources[0x6a]	61118	1			T20	10		T21	5		T22	1
valid_sources[0x6b]	54475	1			T20	15		T25	1		T27	1
valid_sources[0x6c]	58086	1			T20	10		T21	3		T22	1
valid_sources[0x6d]	56894	1			T21	5		T28	5		T29	4298
valid_sources[0x6e]	60677	1			T20	11		T21	1		T22	3
valid_sources[0x6f]	55661	1			T20	24		T21	2		T23	3
valid_sources[0x70]	52129	1			T20	6		T22	2		T27	2
valid_sources[0x71]	57630	1			T20	2		T21	2		T22	1
valid_sources[0x72]	52933	1			T20	13		T21	1		T22	2
valid_sources[0x73]	53607	1			T20	6		T21	2		T22	2
valid_sources[0x74]	53208	1			T20	9		T25	1		T28	5
valid_sources[0x75]	107750	1			T20	7		T21	2		T28	6
valid_sources[0x76]	60110	1			T20	14		T25	3		T27	1
valid_sources[0x77]	53945	1			T20	11		T22	1		T23	3
valid_sources[0x78]	54474	1			T20	1		T21	1		T22	1
valid_sources[0x79]	56831	1			T20	14		T21	2		T28	14
valid_sources[0x7a]	169916	1			T20	8		T28	6		T29	2847
valid_sources[0x7b]	57360	1			T20	14		T21	3		T22	1
valid_sources[0x7c]	55831	1			T20	2		T23	1		T25	1
valid_sources[0x7d]	183743	1			T20	8		T21	2		T23	2
valid_sources[0x7e]	63130	1			T20	4		T22	1		T23	7
valid_sources[0x7f]	55467	1			T20	21		T21	4		T23	2
valid_sources[0x80]	54557	1			T20	3		T23	1		T27	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3598229

1

T20

877

T21

112

T22

15

values[0x0]

all_enables

biggest_size

4582178

1

T20

284

T21

166

T22

96

values[0x1]

all_enables

biggest_size

4584460

1

T20

275

T21

140

T22

84