Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	130520562	0	0	0
ctrl_en_input_filter_rd_A	130520562	88976	0	0
intr_ctrl_en_falling_rd_A	130520562	89922	0	0
intr_ctrl_en_lvlhigh_rd_A	130520562	87695	0	0
intr_ctrl_en_lvllow_rd_A	130520562	90802	0	0
intr_ctrl_en_rising_rd_A	130520562	87884	0	0
intr_enable_rd_A	130520562	88225	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130520562	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130520562	88976	0	0
T1	198230	686	0	0
T2	179320	5338	0	0
T3	0	1607	0	0
T4	0	1028	0	0
T5	0	6518	0	0
T6	0	340	0	0
T7	0	361	0	0
T8	0	254	0	0
T9	0	344	0	0
T10	0	5	0	0
T11	11973	0	0	0
T12	2031	0	0	0
T13	10358	0	0	0
T14	2860	0	0	0
T15	5501	0	0	0
T16	5204	0	0	0
T17	7877	0	0	0
T18	6995	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130520562	89922	0	0
T1	198230	762	0	0
T2	179320	5196	0	0
T3	0	1517	0	0
T4	0	1091	0	0
T5	0	6269	0	0
T6	0	264	0	0
T7	0	326	0	0
T8	0	269	0	0
T9	0	317	0	0
T10	0	3	0	0
T11	11973	0	0	0
T12	2031	0	0	0
T13	10358	0	0	0
T14	2860	0	0	0
T15	5501	0	0	0
T16	5204	0	0	0
T17	7877	0	0	0
T18	6995	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130520562	87695	0	0
T1	198230	727	0	0
T2	179320	5550	0	0
T3	0	1469	0	0
T4	0	961	0	0
T5	0	6276	0	0
T6	0	276	0	0
T7	0	298	0	0
T8	0	232	0	0
T9	0	219	0	0
T11	11973	0	0	0
T12	2031	0	0	0
T13	10358	0	0	0
T14	2860	0	0	0
T15	5501	0	0	0
T16	5204	0	0	0
T17	7877	0	0	0
T18	6995	0	0	0
T19	0	2100	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130520562	90802	0	0
T1	198230	630	0	0
T2	179320	5252	0	0
T3	0	1522	0	0
T4	0	1095	0	0
T5	0	6117	0	0
T6	0	418	0	0
T7	0	413	0	0
T8	0	237	0	0
T9	0	344	0	0
T10	0	5	0	0
T11	11973	0	0	0
T12	2031	0	0	0
T13	10358	0	0	0
T14	2860	0	0	0
T15	5501	0	0	0
T16	5204	0	0	0
T17	7877	0	0	0
T18	6995	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130520562	87884	0	0
T1	198230	675	0	0
T2	179320	5355	0	0
T3	0	1467	0	0
T4	0	936	0	0
T5	0	6564	0	0
T6	0	353	0	0
T7	0	254	0	0
T8	0	192	0	0
T9	0	297	0	0
T10	0	3	0	0
T11	11973	0	0	0
T12	2031	0	0	0
T13	10358	0	0	0
T14	2860	0	0	0
T15	5501	0	0	0
T16	5204	0	0	0
T17	7877	0	0	0
T18	6995	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130520562	88225	0	0
T1	198230	701	0	0
T2	179320	4994	0	0
T3	0	1600	0	0
T4	0	1019	0	0
T5	0	6358	0	0
T6	0	349	0	0
T7	0	295	0	0
T8	0	257	0	0
T9	0	290	0	0
T10	0	10	0	0
T11	11973	0	0	0
T12	2031	0	0	0
T13	10358	0	0	0
T14	2860	0	0	0
T15	5501	0	0	0
T16	5204	0	0	0
T17	7877	0	0	0
T18	6995	0	0	0