Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	175573119	0	0	0
ctrl_en_input_filter_rd_A	175573119	91121	0	0
intr_ctrl_en_falling_rd_A	175573119	92971	0	0
intr_ctrl_en_lvlhigh_rd_A	175573119	92342	0	0
intr_ctrl_en_lvllow_rd_A	175573119	93756	0	0
intr_ctrl_en_rising_rd_A	175573119	91380	0	0
intr_enable_rd_A	175573119	93851	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175573119	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175573119	91121	0	0
T1	44093	223	0	0
T2	13349	47	0	0
T3	23985	85	0	0
T4	0	6849	0	0
T5	0	1717	0	0
T6	0	1	0	0
T7	0	108	0	0
T8	0	4	0	0
T9	0	229	0	0
T10	0	10	0	0
T11	7228	0	0	0
T12	4530	0	0	0
T13	2473	0	0	0
T14	2001	0	0	0
T15	2840	0	0	0
T16	1353	0	0	0
T17	2421	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175573119	92971	0	0
T1	44093	210	0	0
T2	13349	87	0	0
T3	23985	80	0	0
T4	0	6540	0	0
T5	0	1841	0	0
T7	0	133	0	0
T9	0	226	0	0
T11	7228	0	0	0
T12	4530	0	0	0
T13	2473	0	0	0
T14	2001	0	0	0
T15	2840	0	0	0
T16	1353	0	0	0
T17	2421	0	0	0
T18	0	5	0	0
T19	0	1387	0	0
T20	0	2058	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175573119	92342	0	0
T1	44093	215	0	0
T2	13349	69	0	0
T3	23985	97	0	0
T4	0	6712	0	0
T5	0	1798	0	0
T7	0	92	0	0
T9	0	241	0	0
T10	0	4	0	0
T11	7228	0	0	0
T12	4530	0	0	0
T13	2473	0	0	0
T14	2001	0	0	0
T15	2840	0	0	0
T16	1353	0	0	0
T17	2421	0	0	0
T18	0	2	0	0
T19	0	1545	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175573119	93756	0	0
T1	44093	234	0	0
T2	13349	51	0	0
T3	23985	82	0	0
T4	0	6516	0	0
T5	0	1804	0	0
T6	0	2	0	0
T7	0	122	0	0
T9	0	193	0	0
T11	7228	0	0	0
T12	4530	0	0	0
T13	2473	0	0	0
T14	2001	0	0	0
T15	2840	0	0	0
T16	1353	0	0	0
T17	2421	0	0	0
T19	0	1576	0	0
T20	0	2276	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175573119	91380	0	0
T1	44093	206	0	0
T2	13349	66	0	0
T3	23985	120	0	0
T4	0	6423	0	0
T5	0	1795	0	0
T7	0	156	0	0
T8	0	4	0	0
T9	0	222	0	0
T10	0	3	0	0
T11	7228	0	0	0
T12	4530	0	0	0
T13	2473	0	0	0
T14	2001	0	0	0
T15	2840	0	0	0
T16	1353	0	0	0
T17	2421	0	0	0
T19	0	1456	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175573119	93851	0	0
T1	44093	219	0	0
T2	13349	106	0	0
T3	23985	66	0	0
T4	0	6420	0	0
T5	0	2002	0	0
T6	0	19	0	0
T7	0	124	0	0
T9	0	170	0	0
T10	0	5	0	0
T11	7228	0	0	0
T12	4530	0	0	0
T13	2473	0	0	0
T14	2001	0	0	0
T15	2840	0	0	0
T16	1353	0	0	0
T17	2421	0	0	0
T18	0	1	0	0