Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3146635	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

14191241

1

T30

197

T31

1310

T32

253

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	6897935	1			T30	97		T31	1602		T32	25
values[0x0]	5130550	1			T30	77		T31	249		T32	117
values[0x1]	5309391	1			T30	79		T31	269		T32	122

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2415346	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

14922530

1

T30

207

T31

1461

T32

256

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	66062	1			T33	1		T34	12		T35	9
valid_sources[0x01]	63731	1			T30	2		T35	12		T38	1
valid_sources[0x02]	62304	1			T30	1		T32	2		T33	3
valid_sources[0x03]	70360	1			T30	2		T33	2		T34	4
valid_sources[0x04]	68551	1			T30	1		T33	1		T34	5
valid_sources[0x05]	69284	1			T30	1		T32	2		T33	2
valid_sources[0x06]	63601	1			T30	3		T33	2		T34	31
valid_sources[0x07]	61578	1			T30	1		T33	1		T34	18
valid_sources[0x08]	65745	1			T30	1		T32	2		T33	1
valid_sources[0x09]	69233	1			T32	1		T33	2		T35	5
valid_sources[0x0a]	61251	1			T30	4		T32	3		T35	4
valid_sources[0x0b]	71165	1			T30	1		T32	1		T33	2
valid_sources[0x0c]	65000	1			T30	3		T33	1		T35	11
valid_sources[0x0d]	62698	1			T30	2		T32	2		T34	3
valid_sources[0x0e]	66068	1			T30	1		T32	1		T35	7
valid_sources[0x0f]	63865	1			T33	1		T34	11		T35	10
valid_sources[0x10]	63057	1			T30	1		T32	1		T33	1
valid_sources[0x11]	65798	1			T33	1		T34	12		T35	10
valid_sources[0x12]	68150	1			T30	1		T32	2		T33	1
valid_sources[0x13]	68018	1			T30	1		T32	1		T33	2
valid_sources[0x14]	61117	1			T30	1		T32	1		T35	10
valid_sources[0x15]	60145	1			T32	2		T33	4		T35	6
valid_sources[0x16]	65493	1			T30	2		T33	2		T35	6
valid_sources[0x17]	61987	1			T30	5		T33	1		T35	4
valid_sources[0x18]	62923	1			T32	1		T33	2		T34	2
valid_sources[0x19]	62761	1			T30	1		T33	1		T35	6
valid_sources[0x1a]	64110	1			T30	1		T33	1		T35	11
valid_sources[0x1b]	64696	1			T32	1		T33	1		T35	8
valid_sources[0x1c]	63158	1			T32	3		T33	1		T35	8
valid_sources[0x1d]	65061	1			T30	1		T33	2		T35	12
valid_sources[0x1e]	64615	1			T32	2		T34	17		T35	9
valid_sources[0x1f]	111152	1			T30	3		T32	2		T33	1
valid_sources[0x20]	63396	1			T30	1		T33	1		T35	9
valid_sources[0x21]	64425	1			T32	1		T33	1		T35	14
valid_sources[0x22]	66964	1			T32	1		T33	1		T35	21
valid_sources[0x23]	59184	1			T30	2		T32	1		T33	1
valid_sources[0x24]	62195	1			T32	3		T35	7		T36	4
valid_sources[0x25]	63028	1			T33	1		T35	11		T39	6
valid_sources[0x26]	68644	1			T30	1		T33	1		T35	3
valid_sources[0x27]	61525	1			T32	4		T33	1		T35	9
valid_sources[0x28]	63539	1			T30	3		T32	1		T33	1
valid_sources[0x29]	61213	1			T30	1		T32	1		T33	1
valid_sources[0x2a]	67674	1			T34	19		T35	8		T36	1
valid_sources[0x2b]	63030	1			T32	2		T33	1		T34	7
valid_sources[0x2c]	66317	1			T30	1		T32	1		T34	1
valid_sources[0x2d]	61998	1			T34	2		T35	15		T38	4
valid_sources[0x2e]	67659	1			T32	5		T35	10		T36	1
valid_sources[0x2f]	62553	1			T30	1		T33	2		T35	4
valid_sources[0x30]	63262	1			T30	1		T32	1		T33	2
valid_sources[0x31]	66850	1			T32	1		T33	1		T35	5
valid_sources[0x32]	59359	1			T30	1		T33	2		T35	13
valid_sources[0x33]	63882	1			T30	1		T32	1		T33	2
valid_sources[0x34]	61630	1			T32	5		T33	2		T35	6
valid_sources[0x35]	56622	1			T30	1		T34	6		T35	10
valid_sources[0x36]	66170	1			T30	2		T33	6		T34	2
valid_sources[0x37]	64652	1			T30	1		T34	3		T35	8
valid_sources[0x38]	160797	1			T33	2		T35	10		T36	1
valid_sources[0x39]	62908	1			T30	2		T32	2		T33	3
valid_sources[0x3a]	62292	1			T30	1		T32	3		T33	1
valid_sources[0x3b]	62344	1			T30	2		T33	1		T35	10
valid_sources[0x3c]	63954	1			T30	1		T32	1		T33	1
valid_sources[0x3d]	69296	1			T33	1		T34	6		T35	13
valid_sources[0x3e]	67823	1			T33	3		T35	5		T36	2
valid_sources[0x3f]	60753	1			T30	2		T32	2		T35	10
valid_sources[0x40]	64416	1			T30	1		T33	1		T34	7
valid_sources[0x41]	135361	1			T30	1		T33	3		T34	9
valid_sources[0x42]	64609	1			T30	1		T33	1		T34	3
valid_sources[0x43]	69320	1			T30	1		T33	1		T35	8
valid_sources[0x44]	254238	1			T30	2		T32	1		T33	1
valid_sources[0x45]	64294	1			T30	1		T32	1		T35	13
valid_sources[0x46]	72197	1			T30	1		T32	2		T33	1
valid_sources[0x47]	65520	1			T32	3		T35	7		T38	2
valid_sources[0x48]	62701	1			T30	1		T33	3		T34	6
valid_sources[0x49]	64349	1			T32	1		T33	2		T34	13
valid_sources[0x4a]	60512	1			T30	1		T35	6		T38	2
valid_sources[0x4b]	63925	1			T30	1		T33	1		T35	11
valid_sources[0x4c]	65393	1			T33	3		T35	13		T36	1
valid_sources[0x4d]	57895	1			T32	1		T33	1		T35	7
valid_sources[0x4e]	61025	1			T30	4		T35	12		T38	3
valid_sources[0x4f]	65361	1			T32	1		T33	2		T34	8
valid_sources[0x50]	61491	1			T30	1		T32	3		T35	10
valid_sources[0x51]	67207	1			T33	1		T34	6		T35	11
valid_sources[0x52]	59817	1			T30	1		T32	1		T33	2
valid_sources[0x53]	63892	1			T30	1		T32	1		T35	7
valid_sources[0x54]	61814	1			T30	1		T32	2		T33	1
valid_sources[0x55]	59785	1			T30	1		T33	2		T35	10
valid_sources[0x56]	66603	1			T33	2		T35	9		T36	1
valid_sources[0x57]	66846	1			T30	2		T32	1		T33	1
valid_sources[0x58]	57346	1			T32	2		T33	2		T35	9
valid_sources[0x59]	59899	1			T30	4		T32	1		T33	3
valid_sources[0x5a]	68576	1			T32	1		T33	2		T35	14
valid_sources[0x5b]	63110	1			T32	2		T33	1		T34	7
valid_sources[0x5c]	59567	1			T30	1		T33	1		T35	10
valid_sources[0x5d]	68086	1			T35	5		T36	1		T38	5
valid_sources[0x5e]	62252	1			T30	1		T32	3		T33	1
valid_sources[0x5f]	60924	1			T33	2		T35	11		T39	4
valid_sources[0x60]	64341	1			T35	3		T36	2		T38	2
valid_sources[0x61]	61554	1			T32	2		T35	10		T36	1
valid_sources[0x62]	63956	1			T30	1		T32	1		T33	1
valid_sources[0x63]	65606	1			T30	1		T32	2		T33	2
valid_sources[0x64]	67569	1			T30	1		T34	6		T35	11
valid_sources[0x65]	163217	1			T30	1		T33	1		T34	10
valid_sources[0x66]	61336	1			T30	1		T32	5		T35	8
valid_sources[0x67]	60653	1			T30	1		T32	4		T35	4
valid_sources[0x68]	65514	1			T33	1		T35	9		T38	1
valid_sources[0x69]	66893	1			T33	1		T34	1		T35	13
valid_sources[0x6a]	59034	1			T30	2		T34	2		T35	7
valid_sources[0x6b]	68403	1			T30	1		T33	1		T35	9
valid_sources[0x6c]	61324	1			T32	1		T33	1		T34	15
valid_sources[0x6d]	70407	1			T30	3		T32	1		T33	1
valid_sources[0x6e]	99817	1			T30	1		T32	1		T33	2
valid_sources[0x6f]	65894	1			T30	1		T32	1		T33	1
valid_sources[0x70]	61182	1			T33	1		T34	5		T35	15
valid_sources[0x71]	64135	1			T35	14		T36	2		T39	3
valid_sources[0x72]	74055	1			T30	2		T32	1		T35	9
valid_sources[0x73]	65179	1			T30	1		T32	1		T33	1
valid_sources[0x74]	67591	1			T30	1		T32	3		T33	4
valid_sources[0x75]	62743	1			T30	4		T32	1		T34	3
valid_sources[0x76]	69973	1			T32	2		T33	1		T35	8
valid_sources[0x77]	60376	1			T30	3		T34	13		T35	12
valid_sources[0x78]	65236	1			T33	1		T35	10		T39	5
valid_sources[0x79]	62152	1			T35	6		T36	1		T38	1
valid_sources[0x7a]	61770	1			T30	1		T32	5		T33	2
valid_sources[0x7b]	69120	1			T30	3		T32	1		T33	2
valid_sources[0x7c]	68205	1			T30	2		T33	1		T35	9
valid_sources[0x7d]	150598	1			T30	1		T33	1		T34	2
valid_sources[0x7e]	65891	1			T30	1		T32	1		T34	3
valid_sources[0x7f]	71128	1			T30	1		T33	1		T34	6
valid_sources[0x80]	60636	1			T30	2		T32	2		T35	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3972343

1

T30

41

T31

792

T32

14

values[0x0]

all_enables

biggest_size

5111818

1

T30

77

T31

249

T32

117

values[0x1]

all_enables

biggest_size

5107080

1

T30

79

T31

269

T32

122