Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	148101615	0	0	0
ctrl_en_input_filter_rd_A	148101615	86860	0	0
intr_ctrl_en_falling_rd_A	148101615	87550	0	0
intr_ctrl_en_lvlhigh_rd_A	148101615	85388	0	0
intr_ctrl_en_lvllow_rd_A	148101615	87234	0	0
intr_ctrl_en_rising_rd_A	148101615	84726	0	0
intr_enable_rd_A	148101615	86967	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148101615	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148101615	86860	0	0
T1	5499	4	0	0
T2	186695	7234	0	0
T3	0	7702	0	0
T4	0	1831	0	0
T5	0	272	0	0
T6	0	3198	0	0
T7	0	1639	0	0
T8	0	7	0	0
T9	0	3132	0	0
T10	0	3	0	0
T11	2649	0	0	0
T12	2882	0	0	0
T13	6532	0	0	0
T14	6090	0	0	0
T15	122543	0	0	0
T16	5035	0	0	0
T17	1970	0	0	0
T18	8582	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148101615	87550	0	0
T2	186695	7127	0	0
T3	0	7781	0	0
T4	0	1908	0	0
T5	0	230	0	0
T6	0	3390	0	0
T7	0	1668	0	0
T9	0	3146	0	0
T16	5035	0	0	0
T17	1970	0	0	0
T18	8582	0	0	0
T19	0	6	0	0
T20	0	47	0	0
T21	0	10	0	0
T22	602516	0	0	0
T23	2587	0	0	0
T24	5646	0	0	0
T25	2884	0	0	0
T26	29031	0	0	0
T27	6197	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148101615	85388	0	0
T1	5499	1	0	0
T2	186695	7014	0	0
T3	0	7791	0	0
T4	0	2037	0	0
T5	0	144	0	0
T6	0	3208	0	0
T7	0	1602	0	0
T8	0	6	0	0
T9	0	3049	0	0
T10	0	1	0	0
T11	2649	0	0	0
T12	2882	0	0	0
T13	6532	0	0	0
T14	6090	0	0	0
T15	122543	0	0	0
T16	5035	0	0	0
T17	1970	0	0	0
T18	8582	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148101615	87234	0	0
T2	186695	6877	0	0
T3	0	7835	0	0
T4	0	1819	0	0
T5	0	117	0	0
T6	0	3263	0	0
T7	0	1831	0	0
T9	0	3064	0	0
T10	0	6	0	0
T16	5035	0	0	0
T17	1970	0	0	0
T18	8582	0	0	0
T20	0	97	0	0
T22	602516	0	0	0
T23	2587	0	0	0
T24	5646	0	0	0
T25	2884	0	0	0
T26	29031	0	0	0
T27	6197	0	0	0
T28	0	3	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148101615	84726	0	0
T2	186695	6528	0	0
T3	0	7729	0	0
T4	0	1992	0	0
T5	0	172	0	0
T6	0	3253	0	0
T7	0	1535	0	0
T8	0	2	0	0
T9	0	3336	0	0
T16	5035	0	0	0
T17	1970	0	0	0
T18	8582	0	0	0
T20	0	67	0	0
T22	602516	0	0	0
T23	2587	0	0	0
T24	5646	0	0	0
T25	2884	0	0	0
T26	29031	0	0	0
T27	6197	0	0	0
T29	0	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148101615	86967	0	0
T1	5499	15	0	0
T2	186695	7168	0	0
T3	0	7745	0	0
T4	0	1842	0	0
T5	0	191	0	0
T6	0	2970	0	0
T7	0	1601	0	0
T8	0	2	0	0
T9	0	3098	0	0
T11	2649	0	0	0
T12	2882	0	0	0
T13	6532	0	0	0
T14	6090	0	0	0
T15	122543	0	0	0
T16	5035	0	0	0
T17	1970	0	0	0
T18	8582	0	0	0
T20	0	86	0	0