Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3232578	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

14184561

1

T23

8

T24

703

T25

59347

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7014601	1			T23	1		T24	376		T25	35393
values[0x0]	5120916	1			T23	4		T24	269		T25	20825
values[0x1]	5281622	1			T23	12		T24	243		T25	20963

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2493843	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

14923296

1

T23

9

T24

739

T25

62945

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	63133	1			T28	12		T112	3		T34	1
valid_sources[0x01]	62541	1			T28	57		T34	2		T113	2
valid_sources[0x02]	60603	1			T26	1		T28	35		T113	7
valid_sources[0x03]	61186	1			T26	1		T28	126		T32	1
valid_sources[0x04]	65162	1			T26	2		T28	17		T35	1
valid_sources[0x05]	59502	1			T28	12		T32	1		T114	2
valid_sources[0x06]	67467	1			T28	32		T112	3		T35	6
valid_sources[0x07]	63728	1			T26	4		T28	27		T115	1
valid_sources[0x08]	61102	1			T26	4		T112	1		T35	9
valid_sources[0x09]	60526	1			T27	13		T28	12		T116	257
valid_sources[0x0a]	59626	1			T26	2		T28	3		T115	1
valid_sources[0x0b]	61212	1			T26	1		T115	1		T35	4
valid_sources[0x0c]	66429	1			T28	97		T113	1		T35	4
valid_sources[0x0d]	63081	1			T26	2		T32	1		T112	4
valid_sources[0x0e]	62931	1			T26	2		T115	1		T117	21
valid_sources[0x0f]	60199	1			T26	8		T112	1		T115	1
valid_sources[0x10]	57741	1			T115	1		T35	14		T55	13
valid_sources[0x11]	65429	1			T26	3		T28	7		T115	1
valid_sources[0x12]	69598	1			T26	1		T28	31		T112	2
valid_sources[0x13]	66920	1			T26	3		T28	32		T112	6
valid_sources[0x14]	59207	1			T26	7		T112	2		T115	1
valid_sources[0x15]	112907	1			T28	33		T112	8		T35	6
valid_sources[0x16]	63980	1			T28	2		T115	1		T114	1
valid_sources[0x17]	63426	1			T26	1		T34	1		T114	1
valid_sources[0x18]	64837	1			T26	1		T28	9		T32	1
valid_sources[0x19]	60918	1			T27	17		T118	2		T114	1
valid_sources[0x1a]	65876	1			T112	1		T115	1		T118	1
valid_sources[0x1b]	64266	1			T24	888		T26	4		T112	4
valid_sources[0x1c]	68298	1			T28	24		T112	1		T34	2
valid_sources[0x1d]	65915	1			T26	2		T28	14		T114	2
valid_sources[0x1e]	65733	1			T26	5		T112	3		T35	4
valid_sources[0x1f]	70986	1			T28	10		T32	2		T112	7
valid_sources[0x20]	63314	1			T26	3		T28	54		T112	4
valid_sources[0x21]	65033	1			T26	1		T28	28		T114	1
valid_sources[0x22]	65479	1			T26	1		T28	5		T112	1
valid_sources[0x23]	57856	1			T26	2		T28	45		T32	7
valid_sources[0x24]	74189	1			T28	18		T112	3		T115	1
valid_sources[0x25]	141610	1			T25	77181		T26	1		T115	2
valid_sources[0x26]	67349	1			T26	4		T28	41		T112	5
valid_sources[0x27]	60122	1			T26	1		T28	3		T115	1
valid_sources[0x28]	67583	1			T28	30		T32	1		T33	187
valid_sources[0x29]	62371	1			T23	17		T26	1		T28	19
valid_sources[0x2a]	69052	1			T26	1		T27	4		T28	10
valid_sources[0x2b]	62396	1			T118	22		T114	3		T35	12
valid_sources[0x2c]	63019	1			T26	4		T28	29		T35	8
valid_sources[0x2d]	61847	1			T26	1		T28	8		T32	3
valid_sources[0x2e]	59995	1			T26	1		T28	43		T115	1
valid_sources[0x2f]	62255	1			T112	2		T115	1		T118	1
valid_sources[0x30]	60995	1			T26	1		T28	18		T115	1
valid_sources[0x31]	60510	1			T28	5		T115	2		T34	1
valid_sources[0x32]	63655	1			T112	1		T115	2		T114	1
valid_sources[0x33]	156852	1			T26	3		T28	8		T115	1
valid_sources[0x34]	63022	1			T26	1		T112	2		T35	3
valid_sources[0x35]	68594	1			T26	3		T115	2		T35	10
valid_sources[0x36]	61190	1			T26	2		T28	13		T118	7
valid_sources[0x37]	69195	1			T28	19		T30	11		T32	1
valid_sources[0x38]	64747	1			T28	38		T112	2		T114	1
valid_sources[0x39]	59926	1			T35	4		T55	7		T119	1
valid_sources[0x3a]	58414	1			T28	4		T112	3		T115	2
valid_sources[0x3b]	60642	1			T28	1		T112	1		T114	5
valid_sources[0x3c]	70920	1			T26	4		T28	8		T115	2
valid_sources[0x3d]	60211	1			T26	1		T28	10		T114	3
valid_sources[0x3e]	112022	1			T26	1		T28	13		T112	1
valid_sources[0x3f]	55780	1			T26	4		T28	6		T112	5
valid_sources[0x40]	67622	1			T26	2		T28	14		T114	1
valid_sources[0x41]	74934	1			T26	2		T28	35		T35	17
valid_sources[0x42]	63585	1			T27	4		T28	18		T112	2
valid_sources[0x43]	71160	1			T28	7		T115	2		T34	1
valid_sources[0x44]	61366	1			T26	3		T27	15		T28	15
valid_sources[0x45]	63264	1			T26	2		T28	16		T112	2
valid_sources[0x46]	66006	1			T26	1		T28	29		T112	2
valid_sources[0x47]	58165	1			T28	9		T32	3		T115	2
valid_sources[0x48]	61927	1			T26	3		T28	69		T112	4
valid_sources[0x49]	62082	1			T28	3		T113	3		T114	1
valid_sources[0x4a]	60397	1			T26	1		T112	1		T35	14
valid_sources[0x4b]	62473	1			T26	1		T115	1		T118	2
valid_sources[0x4c]	63792	1			T26	1		T28	63		T34	1
valid_sources[0x4d]	59702	1			T26	1		T114	1		T35	8
valid_sources[0x4e]	76152	1			T28	14		T115	1		T113	2
valid_sources[0x4f]	64189	1			T115	1		T114	1		T55	6
valid_sources[0x50]	71251	1			T114	5		T35	11		T55	2
valid_sources[0x51]	64400	1			T26	1		T28	19		T35	3
valid_sources[0x52]	72411	1			T26	3		T28	9		T117	28
valid_sources[0x53]	65975	1			T28	2		T32	1		T112	5
valid_sources[0x54]	73675	1			T26	2		T27	10		T112	1
valid_sources[0x55]	63256	1			T26	6		T28	1		T115	2
valid_sources[0x56]	59323	1			T26	2		T28	9		T32	1
valid_sources[0x57]	66370	1			T26	1		T28	7		T112	4
valid_sources[0x58]	62321	1			T26	1		T28	2		T32	3
valid_sources[0x59]	196642	1			T26	2		T28	6		T118	2
valid_sources[0x5a]	63751	1			T115	1		T114	1		T35	4
valid_sources[0x5b]	68571	1			T115	1		T35	8		T55	7
valid_sources[0x5c]	64408	1			T26	1		T34	1		T35	8
valid_sources[0x5d]	74540	1			T26	2		T28	40		T118	6
valid_sources[0x5e]	68739	1			T28	25		T112	4		T114	1
valid_sources[0x5f]	72921	1			T26	2		T112	2		T115	1
valid_sources[0x60]	59933	1			T28	28		T117	2		T34	1
valid_sources[0x61]	56403	1			T26	2		T27	1		T28	16
valid_sources[0x62]	72604	1			T26	2		T27	40		T28	8
valid_sources[0x63]	61169	1			T26	1		T28	32		T112	1
valid_sources[0x64]	61673	1			T26	2		T27	19		T115	2
valid_sources[0x65]	64083	1			T26	1		T28	9		T112	3
valid_sources[0x66]	66407	1			T28	1		T112	1		T115	1
valid_sources[0x67]	61869	1			T26	2		T112	7		T115	1
valid_sources[0x68]	75723	1			T28	27		T112	1		T35	8
valid_sources[0x69]	60210	1			T26	1		T28	21		T115	1
valid_sources[0x6a]	68361	1			T34	1		T35	9		T55	11
valid_sources[0x6b]	64125	1			T28	13		T35	17		T55	7
valid_sources[0x6c]	66209	1			T28	10		T112	1		T114	2
valid_sources[0x6d]	60311	1			T28	15		T32	2		T35	5
valid_sources[0x6e]	67850	1			T26	1		T28	10		T112	2
valid_sources[0x6f]	58424	1			T115	1		T114	1		T35	7
valid_sources[0x70]	74994	1			T26	2		T28	9		T112	2
valid_sources[0x71]	65017	1			T26	1		T27	7		T28	54
valid_sources[0x72]	67652	1			T26	1		T27	8		T28	84
valid_sources[0x73]	59370	1			T115	2		T34	1		T114	1
valid_sources[0x74]	60743	1			T26	2		T28	46		T115	1
valid_sources[0x75]	62806	1			T114	2		T35	8		T55	8
valid_sources[0x76]	66123	1			T26	3		T30	19		T112	4
valid_sources[0x77]	64293	1			T26	1		T112	3		T115	2
valid_sources[0x78]	65230	1			T26	1		T27	4		T32	1
valid_sources[0x79]	63701	1			T26	4		T28	75		T115	1
valid_sources[0x7a]	61774	1			T26	1		T112	1		T34	2
valid_sources[0x7b]	59168	1			T26	1		T28	3		T115	1
valid_sources[0x7c]	68092	1			T26	5		T112	11		T115	1
valid_sources[0x7d]	67410	1			T26	1		T112	6		T115	4
valid_sources[0x7e]	61449	1			T26	4		T28	16		T118	2
valid_sources[0x7f]	57753	1			T26	3		T28	22		T112	3
valid_sources[0x80]	67366	1			T26	1		T28	15		T112	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3982705

1

T23

1

T24

191

T25

17559

values[0x0]

all_enables

biggest_size

5103797

1

T23

3

T24

269

T25

20825

values[0x1]

all_enables

biggest_size

5098059

1

T23

4

T24

243

T25

20963