Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	143479168	0	0	0
ctrl_en_input_filter_rd_A	143479168	66758	0	0
intr_ctrl_en_falling_rd_A	143479168	66801	0	0
intr_ctrl_en_lvlhigh_rd_A	143479168	65821	0	0
intr_ctrl_en_lvllow_rd_A	143479168	67564	0	0
intr_ctrl_en_rising_rd_A	143479168	67859	0	0
intr_enable_rd_A	143479168	67058	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143479168	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143479168	66758	0	0
T1	106330	2872	0	0
T2	0	1	0	0
T3	0	9	0	0
T4	0	11011	0	0
T5	0	7	0	0
T6	0	257	0	0
T7	0	43	0	0
T8	0	6	0	0
T9	0	2969	0	0
T10	0	1411	0	0
T11	27916	0	0	0
T12	1901	0	0	0
T13	4541	0	0	0
T14	3105	0	0	0
T15	3079	0	0	0
T16	7670	0	0	0
T17	2351	0	0	0
T18	1418	0	0	0
T19	4246	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143479168	66801	0	0
T1	106330	2820	0	0
T3	0	12	0	0
T4	0	11731	0	0
T6	0	251	0	0
T7	0	21	0	0
T8	0	2	0	0
T9	0	3124	0	0
T10	0	1394	0	0
T11	27916	0	0	0
T12	1901	0	0	0
T13	4541	0	0	0
T14	3105	0	0	0
T15	3079	0	0	0
T16	7670	0	0	0
T17	2351	0	0	0
T18	1418	0	0	0
T19	4246	0	0	0
T20	0	3	0	0
T21	0	2810	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143479168	65821	0	0
T1	106330	2715	0	0
T4	0	10955	0	0
T5	0	5	0	0
T6	0	222	0	0
T7	0	27	0	0
T8	0	12	0	0
T9	0	2832	0	0
T10	0	1584	0	0
T11	27916	0	0	0
T12	1901	0	0	0
T13	4541	0	0	0
T14	3105	0	0	0
T15	3079	0	0	0
T16	7670	0	0	0
T17	2351	0	0	0
T18	1418	0	0	0
T19	4246	0	0	0
T20	0	3	0	0
T21	0	2921	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143479168	67564	0	0
T1	106330	2709	0	0
T3	0	2	0	0
T4	0	11897	0	0
T5	0	6	0	0
T6	0	318	0	0
T7	0	56	0	0
T9	0	2901	0	0
T10	0	1405	0	0
T11	27916	0	0	0
T12	1901	0	0	0
T13	4541	0	0	0
T14	3105	0	0	0
T15	3079	0	0	0
T16	7670	0	0	0
T17	2351	0	0	0
T18	1418	0	0	0
T19	4246	0	0	0
T20	0	1	0	0
T21	0	2640	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143479168	67859	0	0
T1	106330	2959	0	0
T4	0	10997	0	0
T5	0	2	0	0
T6	0	292	0	0
T7	0	75	0	0
T8	0	2	0	0
T9	0	3109	0	0
T10	0	1520	0	0
T11	27916	0	0	0
T12	1901	0	0	0
T13	4541	0	0	0
T14	3105	0	0	0
T15	3079	0	0	0
T16	7670	0	0	0
T17	2351	0	0	0
T18	1418	0	0	0
T19	4246	0	0	0
T21	0	2790	0	0
T22	0	62	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143479168	67058	0	0
T1	106330	2824	0	0
T3	0	10	0	0
T4	0	10867	0	0
T6	0	220	0	0
T7	0	63	0	0
T9	0	3023	0	0
T10	0	1364	0	0
T11	27916	0	0	0
T12	1901	0	0	0
T13	4541	0	0	0
T14	3105	0	0	0
T15	3079	0	0	0
T16	7670	0	0	0
T17	2351	0	0	0
T18	1418	0	0	0
T19	4246	0	0	0
T20	0	9	0	0
T21	0	2856	0	0
T22	0	18	0	0