Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4043245	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

18163827

1

T20

383

T1

2093

T11

164

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8844335	1			T20	87		T1	1570		T11	36
values[0x0]	6568494	1			T20	169		T1	676		T11	71
values[0x1]	6794243	1			T20	169		T1	676		T11	74

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3105628	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

19101444

1

T20

392

T1

2257

T11

166

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	92723	1			T20	1		T1	11		T2	392
valid_sources[0x01]	86050	1			T20	2		T1	10		T11	3
valid_sources[0x02]	88032	1			T1	16		T11	1		T13	1
valid_sources[0x03]	86753	1			T20	6		T1	20		T2	394
valid_sources[0x04]	80144	1			T1	16		T2	407		T3	275
valid_sources[0x05]	86810	1			T1	10		T13	2		T2	463
valid_sources[0x06]	91006	1			T1	11		T11	4		T13	1
valid_sources[0x07]	83219	1			T1	13		T13	1		T14	4
valid_sources[0x08]	168319	1			T20	2		T1	7		T11	1
valid_sources[0x09]	84650	1			T1	12		T13	2		T2	424
valid_sources[0x0a]	85126	1			T1	8		T11	1		T2	434
valid_sources[0x0b]	79687	1			T20	1		T1	11		T2	445
valid_sources[0x0c]	86849	1			T1	7		T11	1		T2	405
valid_sources[0x0d]	91664	1			T20	4		T1	11		T2	371
valid_sources[0x0e]	74919	1			T20	3		T1	14		T13	1
valid_sources[0x0f]	93661	1			T1	8		T11	2		T2	394
valid_sources[0x10]	79066	1			T1	11		T2	430		T3	196
valid_sources[0x11]	75985	1			T1	14		T11	1		T13	2
valid_sources[0x12]	92377	1			T20	4		T1	12		T11	1
valid_sources[0x13]	166918	1			T1	10		T2	394		T3	285
valid_sources[0x14]	76572	1			T1	9		T13	2		T2	424
valid_sources[0x15]	81863	1			T1	9		T13	2		T2	445
valid_sources[0x16]	86710	1			T20	11		T1	13		T2	442
valid_sources[0x17]	84536	1			T20	5		T1	9		T2	425
valid_sources[0x18]	80665	1			T20	5		T1	15		T11	1
valid_sources[0x19]	91307	1			T1	11		T2	405		T3	192
valid_sources[0x1a]	79747	1			T20	2		T1	12		T2	455
valid_sources[0x1b]	83445	1			T1	7		T13	1		T2	434
valid_sources[0x1c]	80356	1			T1	6		T11	2		T13	3
valid_sources[0x1d]	88360	1			T1	7		T2	419		T3	192
valid_sources[0x1e]	79525	1			T1	11		T11	1		T2	379
valid_sources[0x1f]	87977	1			T1	11		T2	420		T3	268
valid_sources[0x20]	89647	1			T20	1		T1	8		T11	1
valid_sources[0x21]	91825	1			T1	12		T2	393		T3	194
valid_sources[0x22]	91584	1			T1	7		T11	1		T2	405
valid_sources[0x23]	78055	1			T1	12		T13	2		T2	365
valid_sources[0x24]	90386	1			T20	1		T1	13		T13	2
valid_sources[0x25]	83212	1			T20	2		T1	13		T11	3
valid_sources[0x26]	82711	1			T1	13		T14	10		T2	403
valid_sources[0x27]	82625	1			T20	5		T1	13		T13	2
valid_sources[0x28]	82176	1			T20	8		T1	17		T11	2
valid_sources[0x29]	84033	1			T1	10		T11	1		T2	471
valid_sources[0x2a]	90347	1			T1	12		T13	1		T2	423
valid_sources[0x2b]	86306	1			T20	2		T1	12		T2	454
valid_sources[0x2c]	85131	1			T1	9		T11	1		T2	401
valid_sources[0x2d]	82891	1			T1	8		T14	12		T2	374
valid_sources[0x2e]	81393	1			T1	17		T2	384		T3	243
valid_sources[0x2f]	82347	1			T20	3		T1	11		T13	1
valid_sources[0x30]	89942	1			T1	11		T2	441		T3	264
valid_sources[0x31]	88182	1			T20	2		T1	14		T13	2
valid_sources[0x32]	83237	1			T20	1		T1	15		T11	2
valid_sources[0x33]	87695	1			T1	11		T2	429		T3	274
valid_sources[0x34]	81233	1			T1	9		T11	1		T13	1
valid_sources[0x35]	85376	1			T1	18		T11	1		T13	1
valid_sources[0x36]	87747	1			T1	11		T11	2		T2	407
valid_sources[0x37]	88411	1			T1	13		T13	1		T2	376
valid_sources[0x38]	91984	1			T20	5		T1	9		T11	1
valid_sources[0x39]	80417	1			T1	11		T11	1		T2	458
valid_sources[0x3a]	79240	1			T20	2		T1	9		T13	2
valid_sources[0x3b]	91181	1			T20	8		T1	7		T11	1
valid_sources[0x3c]	86750	1			T20	6		T1	8		T13	1
valid_sources[0x3d]	82669	1			T20	1		T1	17		T11	1
valid_sources[0x3e]	81085	1			T20	3		T1	14		T11	2
valid_sources[0x3f]	84895	1			T1	13		T11	2		T2	384
valid_sources[0x40]	79046	1			T1	9		T11	2		T13	2
valid_sources[0x41]	82191	1			T1	14		T2	422		T3	223
valid_sources[0x42]	97416	1			T20	7		T1	14		T11	1
valid_sources[0x43]	88505	1			T1	10		T11	1		T2	438
valid_sources[0x44]	86333	1			T20	3		T1	10		T11	1
valid_sources[0x45]	140626	1			T1	7		T13	1		T2	438
valid_sources[0x46]	88838	1			T20	2		T1	12		T13	1
valid_sources[0x47]	86038	1			T20	4		T1	6		T13	1
valid_sources[0x48]	81738	1			T1	9		T11	2		T13	1
valid_sources[0x49]	90522	1			T1	13		T11	3		T2	384
valid_sources[0x4a]	91415	1			T20	1		T1	15		T13	4
valid_sources[0x4b]	80168	1			T1	8		T11	1		T2	374
valid_sources[0x4c]	81438	1			T1	10		T11	1		T2	401
valid_sources[0x4d]	73955	1			T1	10		T11	2		T2	409
valid_sources[0x4e]	80194	1			T20	1		T1	13		T2	409
valid_sources[0x4f]	78674	1			T1	11		T2	444		T3	240
valid_sources[0x50]	87515	1			T1	11		T2	457		T3	269
valid_sources[0x51]	82679	1			T20	1		T1	13		T11	2
valid_sources[0x52]	83743	1			T20	1		T1	11		T13	3
valid_sources[0x53]	87171	1			T20	3		T1	8		T13	2
valid_sources[0x54]	78356	1			T1	8		T13	2		T2	424
valid_sources[0x55]	85541	1			T1	10		T13	3		T2	468
valid_sources[0x56]	96314	1			T20	3		T1	7		T11	3
valid_sources[0x57]	78683	1			T1	9		T2	421		T3	199
valid_sources[0x58]	82818	1			T20	3		T1	13		T13	2
valid_sources[0x59]	81215	1			T1	11		T11	1		T2	462
valid_sources[0x5a]	83859	1			T1	9		T14	26		T2	447
valid_sources[0x5b]	84845	1			T1	17		T2	438		T3	274
valid_sources[0x5c]	81618	1			T20	2		T1	12		T11	2
valid_sources[0x5d]	79116	1			T1	19		T11	1		T13	1
valid_sources[0x5e]	86756	1			T20	4		T1	11		T11	1
valid_sources[0x5f]	79455	1			T20	9		T1	15		T13	4
valid_sources[0x60]	89699	1			T1	10		T13	2		T2	420
valid_sources[0x61]	78419	1			T1	8		T11	1		T13	3
valid_sources[0x62]	78702	1			T20	2		T1	14		T11	1
valid_sources[0x63]	79636	1			T1	17		T11	1		T2	422
valid_sources[0x64]	239795	1			T1	15		T2	393		T15	39
valid_sources[0x65]	88539	1			T1	18		T11	1		T2	378
valid_sources[0x66]	86800	1			T1	16		T11	2		T13	2
valid_sources[0x67]	81167	1			T1	19		T13	1		T2	377
valid_sources[0x68]	81247	1			T20	4		T1	9		T11	2
valid_sources[0x69]	79520	1			T20	4		T1	6		T11	4
valid_sources[0x6a]	77335	1			T20	1		T1	12		T2	434
valid_sources[0x6b]	87424	1			T20	4		T1	11		T13	1
valid_sources[0x6c]	83871	1			T1	11		T2	412		T3	253
valid_sources[0x6d]	93757	1			T20	1		T1	6		T2	363
valid_sources[0x6e]	83457	1			T20	1		T1	11		T2	389
valid_sources[0x6f]	81540	1			T20	3		T1	11		T11	2
valid_sources[0x70]	92570	1			T20	7		T1	5		T2	417
valid_sources[0x71]	80927	1			T20	4		T1	16		T13	2
valid_sources[0x72]	77636	1			T20	2		T1	11		T11	3
valid_sources[0x73]	79580	1			T1	13		T2	412		T3	167
valid_sources[0x74]	80256	1			T20	1		T1	14		T2	408
valid_sources[0x75]	82092	1			T20	3		T1	4		T11	2
valid_sources[0x76]	90234	1			T1	11		T13	1		T2	462
valid_sources[0x77]	85589	1			T20	10		T1	8		T13	1
valid_sources[0x78]	86228	1			T20	2		T1	10		T2	387
valid_sources[0x79]	84069	1			T1	12		T11	2		T13	5
valid_sources[0x7a]	90277	1			T1	5		T11	4		T2	431
valid_sources[0x7b]	79192	1			T20	2		T1	9		T13	3
valid_sources[0x7c]	83533	1			T20	2		T1	17		T11	2
valid_sources[0x7d]	77924	1			T1	16		T2	444		T3	266
valid_sources[0x7e]	91271	1			T20	1		T1	9		T13	5
valid_sources[0x7f]	86019	1			T20	1		T1	17		T11	1
valid_sources[0x80]	78414	1			T1	9		T2	412		T3	186

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5078121

1

T20

45

T1

741

T11

19

values[0x0]

all_enables

biggest_size

6545507

1

T20

169

T1

676

T11

71

values[0x1]

all_enables

biggest_size

6540199

1

T20

169

T1

676

T11

74