Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	173654848	0	0	0
ctrl_en_input_filter_rd_A	173654848	50509	0	0
intr_ctrl_en_falling_rd_A	173654848	50030	0	0
intr_ctrl_en_lvlhigh_rd_A	173654848	50886	0	0
intr_ctrl_en_lvllow_rd_A	173654848	49742	0	0
intr_ctrl_en_rising_rd_A	173654848	49406	0	0
intr_enable_rd_A	173654848	50513	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173654848	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173654848	50509	0	0
T1	32630	196	0	0
T2	139274	5493	0	0
T3	660351	1813	0	0
T4	0	144	0	0
T5	0	1992	0	0
T6	0	6	0	0
T7	0	279	0	0
T8	0	3	0	0
T9	0	4985	0	0
T10	0	660	0	0
T11	2935	0	0	0
T12	5704	0	0	0
T13	5617	0	0	0
T14	3660	0	0	0
T15	1439	0	0	0
T16	6082	0	0	0
T17	5029	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173654848	50030	0	0
T1	32630	266	0	0
T2	139274	5373	0	0
T3	660351	1835	0	0
T4	0	103	0	0
T5	0	2021	0	0
T6	0	1	0	0
T7	0	305	0	0
T8	0	1	0	0
T9	0	4811	0	0
T10	0	789	0	0
T11	2935	0	0	0
T12	5704	0	0	0
T13	5617	0	0	0
T14	3660	0	0	0
T15	1439	0	0	0
T16	6082	0	0	0
T17	5029	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173654848	50886	0	0
T1	32630	237	0	0
T2	139274	5410	0	0
T3	660351	1866	0	0
T4	0	135	0	0
T5	0	2137	0	0
T7	0	290	0	0
T8	0	6	0	0
T9	0	5139	0	0
T10	0	811	0	0
T11	2935	0	0	0
T12	5704	0	0	0
T13	5617	0	0	0
T14	3660	0	0	0
T15	1439	0	0	0
T16	6082	0	0	0
T17	5029	0	0	0
T18	0	201	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173654848	49742	0	0
T1	32630	248	0	0
T2	139274	5443	0	0
T3	660351	1796	0	0
T4	0	149	0	0
T5	0	1922	0	0
T7	0	263	0	0
T8	0	3	0	0
T9	0	4790	0	0
T10	0	745	0	0
T11	2935	0	0	0
T12	5704	0	0	0
T13	5617	0	0	0
T14	3660	0	0	0
T15	1439	0	0	0
T16	6082	0	0	0
T17	5029	0	0	0
T18	0	174	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173654848	49406	0	0
T1	32630	221	0	0
T2	139274	5396	0	0
T3	660351	1576	0	0
T4	0	190	0	0
T5	0	1933	0	0
T6	0	8	0	0
T7	0	338	0	0
T8	0	2	0	0
T9	0	4839	0	0
T11	2935	0	0	0
T12	5704	0	0	0
T13	5617	0	0	0
T14	3660	0	0	0
T15	1439	0	0	0
T16	6082	0	0	0
T17	5029	0	0	0
T19	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173654848	50513	0	0
T1	32630	310	0	0
T2	139274	5592	0	0
T3	660351	1806	0	0
T4	0	152	0	0
T5	0	2242	0	0
T6	0	5	0	0
T7	0	262	0	0
T9	0	5005	0	0
T10	0	825	0	0
T11	2935	0	0	0
T12	5704	0	0	0
T13	5617	0	0	0
T14	3660	0	0	0
T15	1439	0	0	0
T16	6082	0	0	0
T17	5029	0	0	0
T18	0	254	0	0