Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3307859	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

14895957

1

T31

345

T32

888

T33

758365

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7248633	1			T31	74		T32	1398		T33	362021
values[0x0]	5385187	1			T31	152		T32	105		T33	275154
values[0x1]	5569996	1			T31	154		T32	88		T33	284921

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2541890	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

15661926

1

T31

349

T32

1010

T33

796637

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	68042	1			T32	6		T33	3656		T15	3286
valid_sources[0x01]	61486	1			T32	2		T33	3603		T1	3
valid_sources[0x02]	60884	1			T32	6		T33	3920		T1	3
valid_sources[0x03]	62979	1			T32	7		T33	3766		T19	5
valid_sources[0x04]	71755	1			T33	3382		T13	7		T15	3334
valid_sources[0x05]	60992	1			T32	1		T33	3414		T1	4
valid_sources[0x06]	58240	1			T32	10		T33	3416		T15	3000
valid_sources[0x07]	67204	1			T32	4		T33	3643		T15	3291
valid_sources[0x08]	63395	1			T32	13		T33	3409		T19	12
valid_sources[0x09]	64195	1			T32	7		T33	3612		T15	3295
valid_sources[0x0a]	61252	1			T32	8		T33	3732		T15	2827
valid_sources[0x0b]	63616	1			T32	5		T33	3668		T15	3352
valid_sources[0x0c]	61737	1			T32	6		T33	3505		T1	3
valid_sources[0x0d]	66637	1			T32	6		T33	3722		T15	3076
valid_sources[0x0e]	60763	1			T32	2		T33	3518		T15	2961
valid_sources[0x0f]	59653	1			T32	2		T33	3908		T1	4
valid_sources[0x10]	62222	1			T32	26		T33	3438		T15	3549
valid_sources[0x11]	63561	1			T33	3531		T15	3179		T16	3
valid_sources[0x12]	63401	1			T32	4		T33	3652		T15	3218
valid_sources[0x13]	64447	1			T32	6		T33	3477		T15	3264
valid_sources[0x14]	63964	1			T32	7		T33	3570		T15	3257
valid_sources[0x15]	63785	1			T32	15		T33	3695		T15	3691
valid_sources[0x16]	57138	1			T32	2		T33	3701		T19	3
valid_sources[0x17]	58806	1			T32	7		T33	3589		T1	1
valid_sources[0x18]	57973	1			T32	3		T33	3655		T1	2
valid_sources[0x19]	64893	1			T32	1		T33	3663		T1	1
valid_sources[0x1a]	61242	1			T32	10		T33	3493		T15	2587
valid_sources[0x1b]	60540	1			T32	3		T33	3478		T1	2
valid_sources[0x1c]	59044	1			T32	3		T33	3450		T1	2
valid_sources[0x1d]	66748	1			T31	380		T32	9		T33	3590
valid_sources[0x1e]	68669	1			T33	3590		T15	2898		T16	1
valid_sources[0x1f]	69525	1			T32	5		T33	3656		T15	3453
valid_sources[0x20]	57929	1			T32	5		T33	3634		T15	3212
valid_sources[0x21]	137251	1			T32	15		T33	3720		T1	6
valid_sources[0x22]	66809	1			T32	4		T33	3721		T13	2
valid_sources[0x23]	289954	1			T32	3		T33	3712		T15	3123
valid_sources[0x24]	65521	1			T32	9		T33	3797		T13	11
valid_sources[0x25]	59169	1			T32	5		T33	3612		T15	3314
valid_sources[0x26]	66550	1			T33	3517		T1	7		T13	11
valid_sources[0x27]	61331	1			T32	9		T33	3572		T19	25
valid_sources[0x28]	73631	1			T32	3		T33	3688		T15	3462
valid_sources[0x29]	61729	1			T32	2		T33	3408		T19	12
valid_sources[0x2a]	63914	1			T32	3		T33	3600		T13	4
valid_sources[0x2b]	60840	1			T32	10		T33	3618		T15	3249
valid_sources[0x2c]	60844	1			T32	8		T33	3384		T15	3149
valid_sources[0x2d]	71204	1			T32	10		T33	3524		T1	2
valid_sources[0x2e]	229717	1			T32	5		T33	3323		T1	1
valid_sources[0x2f]	60820	1			T32	15		T33	3643		T1	2
valid_sources[0x30]	65810	1			T32	10		T33	3679		T15	2987
valid_sources[0x31]	208706	1			T32	5		T33	3485		T15	3012
valid_sources[0x32]	63185	1			T32	11		T33	3425		T13	1
valid_sources[0x33]	62430	1			T32	6		T33	3826		T15	3217
valid_sources[0x34]	65844	1			T32	2		T33	3494		T15	2915
valid_sources[0x35]	67720	1			T32	2		T33	3459		T19	11
valid_sources[0x36]	64980	1			T32	4		T33	3361		T15	3298
valid_sources[0x37]	63738	1			T32	7		T33	3695		T1	1
valid_sources[0x38]	59501	1			T32	4		T33	3679		T15	3312
valid_sources[0x39]	59077	1			T32	4		T33	3405		T15	3062
valid_sources[0x3a]	61639	1			T32	8		T33	3810		T15	3172
valid_sources[0x3b]	61338	1			T32	8		T33	3572		T19	10
valid_sources[0x3c]	64111	1			T32	12		T33	3689		T1	1
valid_sources[0x3d]	64783	1			T32	6		T33	3351		T15	3263
valid_sources[0x3e]	61273	1			T32	4		T33	3674		T15	3135
valid_sources[0x3f]	63793	1			T32	11		T33	3714		T15	2899
valid_sources[0x40]	58416	1			T32	5		T33	3730		T15	3131
valid_sources[0x41]	59529	1			T32	7		T33	3851		T15	2724
valid_sources[0x42]	60803	1			T32	11		T33	3505		T15	3184
valid_sources[0x43]	60158	1			T32	11		T33	3578		T13	9
valid_sources[0x44]	60661	1			T32	3		T33	3769		T15	3453
valid_sources[0x45]	65723	1			T32	8		T33	3743		T13	5
valid_sources[0x46]	62774	1			T32	2		T33	3558		T1	1
valid_sources[0x47]	60809	1			T32	14		T33	3601		T15	3125
valid_sources[0x48]	66760	1			T33	3488		T15	3057		T17	3
valid_sources[0x49]	69383	1			T32	13		T33	3685		T15	3637
valid_sources[0x4a]	63595	1			T32	5		T33	3540		T1	1
valid_sources[0x4b]	67607	1			T32	3		T33	3812		T15	3482
valid_sources[0x4c]	63813	1			T32	4		T33	3496		T15	2937
valid_sources[0x4d]	62117	1			T32	11		T33	3578		T19	4
valid_sources[0x4e]	66522	1			T32	3		T33	3642		T13	1
valid_sources[0x4f]	64038	1			T32	3		T33	3589		T1	2
valid_sources[0x50]	138949	1			T32	11		T33	3660		T15	3333
valid_sources[0x51]	71058	1			T32	3		T33	3630		T15	3335
valid_sources[0x52]	60476	1			T32	14		T33	3661		T15	3442
valid_sources[0x53]	61992	1			T32	6		T33	3731		T15	3473
valid_sources[0x54]	61840	1			T32	11		T33	3689		T15	3383
valid_sources[0x55]	58330	1			T32	5		T33	3697		T15	2921
valid_sources[0x56]	66950	1			T33	3594		T13	2		T15	3603
valid_sources[0x57]	199425	1			T32	6		T33	3749		T1	1
valid_sources[0x58]	62410	1			T32	6		T33	3636		T15	3436
valid_sources[0x59]	61809	1			T32	9		T33	3585		T15	3085
valid_sources[0x5a]	62164	1			T32	5		T33	3433		T15	3241
valid_sources[0x5b]	60838	1			T32	8		T33	3630		T15	3476
valid_sources[0x5c]	62894	1			T32	12		T33	3541		T15	3346
valid_sources[0x5d]	60817	1			T32	3		T33	3753		T15	3070
valid_sources[0x5e]	66284	1			T32	12		T33	3608		T15	2936
valid_sources[0x5f]	65022	1			T32	7		T33	3823		T15	3058
valid_sources[0x60]	63156	1			T32	2		T33	3573		T19	16
valid_sources[0x61]	63634	1			T32	15		T33	3725		T1	3
valid_sources[0x62]	69085	1			T32	3		T33	3624		T1	5
valid_sources[0x63]	69891	1			T32	7		T33	3757		T19	5
valid_sources[0x64]	70685	1			T32	1		T33	3554		T15	3032
valid_sources[0x65]	60457	1			T32	4		T33	3526		T15	3152
valid_sources[0x66]	120129	1			T32	6		T33	3766		T15	3376
valid_sources[0x67]	68525	1			T32	12		T33	3422		T15	3136
valid_sources[0x68]	66543	1			T32	2		T33	3770		T15	3164
valid_sources[0x69]	58765	1			T32	4		T33	3630		T19	2
valid_sources[0x6a]	64182	1			T32	10		T33	3355		T1	6
valid_sources[0x6b]	68260	1			T32	3		T33	3546		T19	11
valid_sources[0x6c]	62037	1			T33	3658		T1	3		T13	1
valid_sources[0x6d]	171932	1			T32	9		T33	3776		T15	3153
valid_sources[0x6e]	60746	1			T32	15		T33	3405		T1	1
valid_sources[0x6f]	61755	1			T32	7		T33	3818		T15	3262
valid_sources[0x70]	62015	1			T32	18		T33	3546		T15	3128
valid_sources[0x71]	68744	1			T32	4		T33	3499		T15	3406
valid_sources[0x72]	62566	1			T32	9		T33	3554		T15	3134
valid_sources[0x73]	60245	1			T32	6		T33	3627		T15	3323
valid_sources[0x74]	59818	1			T32	3		T33	3740		T1	2
valid_sources[0x75]	68022	1			T32	3		T33	3501		T1	4
valid_sources[0x76]	66594	1			T32	19		T33	3621		T15	3165
valid_sources[0x77]	62728	1			T32	3		T33	3788		T15	3266
valid_sources[0x78]	64406	1			T32	6		T33	3495		T15	2840
valid_sources[0x79]	62558	1			T32	9		T33	3792		T15	3261
valid_sources[0x7a]	141384	1			T32	9		T33	3812		T15	3375
valid_sources[0x7b]	61554	1			T32	5		T33	3399		T1	4
valid_sources[0x7c]	65590	1			T32	8		T33	3582		T15	3156
valid_sources[0x7d]	68630	1			T32	2		T33	3591		T15	3331
valid_sources[0x7e]	64765	1			T32	3		T33	4126		T13	1
valid_sources[0x7f]	60041	1			T32	4		T33	3562		T15	3337
valid_sources[0x80]	61298	1			T32	3		T33	3540		T15	3021

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4167147

1

T31

39

T32

695

T33

209823

values[0x0]

all_enables

biggest_size

5366089

1

T31

152

T32

105

T33

274197

values[0x1]

all_enables

biggest_size

5362721

1

T31

154

T32

88

T33

274345