Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	158198398	0	0	0
ctrl_en_input_filter_rd_A	158198398	115768	0	0
intr_ctrl_en_falling_rd_A	158198398	118261	0	0
intr_ctrl_en_lvlhigh_rd_A	158198398	115777	0	0
intr_ctrl_en_lvllow_rd_A	158198398	118351	0	0
intr_ctrl_en_rising_rd_A	158198398	116292	0	0
intr_enable_rd_A	158198398	115083	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158198398	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158198398	115768	0	0
T1	6313	6	0	0
T2	54978	387	0	0
T3	0	4391	0	0
T4	0	43	0	0
T5	0	2	0	0
T6	0	7	0	0
T7	0	22	0	0
T8	0	3393	0	0
T9	0	3277	0	0
T10	0	2479	0	0
T11	2186	0	0	0
T12	366503	0	0	0
T13	2868	0	0	0
T14	38229	0	0	0
T15	539723	0	0	0
T16	4259	0	0	0
T17	7410	0	0	0
T18	2498	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158198398	118261	0	0
T1	6313	0	0	0
T2	54978	415	0	0
T3	0	4770	0	0
T4	0	38	0	0
T5	0	3	0	0
T7	0	22	0	0
T8	0	3430	0	0
T9	0	3378	0	0
T10	0	2703	0	0
T11	2186	0	0	0
T12	366503	0	0	0
T13	2868	0	0	0
T14	38229	0	0	0
T15	539723	0	0	0
T16	4259	0	0	0
T17	7410	0	0	0
T19	9808	6	0	0
T20	0	6421	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158198398	115777	0	0
T1	6313	0	0	0
T2	54978	385	0	0
T3	0	4439	0	0
T4	0	32	0	0
T7	0	48	0	0
T8	0	3553	0	0
T9	0	3712	0	0
T10	0	2759	0	0
T11	2186	0	0	0
T12	366503	0	0	0
T13	2868	0	0	0
T14	38229	0	0	0
T15	539723	0	0	0
T16	4259	0	0	0
T17	7410	0	0	0
T19	9808	6	0	0
T20	0	6628	0	0
T21	0	3	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158198398	118351	0	0
T1	6313	11	0	0
T2	54978	377	0	0
T3	0	4545	0	0
T4	0	40	0	0
T5	0	4	0	0
T6	0	4	0	0
T7	0	24	0	0
T8	0	3645	0	0
T9	0	3186	0	0
T10	0	2882	0	0
T11	2186	0	0	0
T12	366503	0	0	0
T13	2868	0	0	0
T14	38229	0	0	0
T15	539723	0	0	0
T16	4259	0	0	0
T17	7410	0	0	0
T18	2498	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158198398	116292	0	0
T1	6313	5	0	0
T2	54978	350	0	0
T3	0	4503	0	0
T4	0	47	0	0
T7	0	51	0	0
T8	0	3417	0	0
T9	0	3049	0	0
T10	0	2803	0	0
T11	2186	0	0	0
T12	366503	0	0	0
T13	2868	0	0	0
T14	38229	0	0	0
T15	539723	0	0	0
T16	4259	0	0	0
T17	7410	0	0	0
T18	2498	0	0	0
T20	0	6535	0	0
T22	0	5039	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158198398	115083	0	0
T2	54978	384	0	0
T3	0	4503	0	0
T4	0	33	0	0
T6	0	7	0	0
T7	0	45	0	0
T8	0	3461	0	0
T9	0	3041	0	0
T10	0	2779	0	0
T18	2498	0	0	0
T20	0	6614	0	0
T22	0	4843	0	0
T23	727	0	0	0
T24	8387	0	0	0
T25	4681	0	0	0
T26	6574	0	0	0
T27	1410	0	0	0
T28	4129	0	0	0
T29	3389	0	0	0
T30	3397	0	0	0