Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4137253	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

18713400

1

T23

107

T24

452

T25

319

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	9072537	1			T23	93		T24	248		T25	77
values[0x0]	6767355	1			T23	28		T24	149		T25	134
values[0x1]	7010761	1			T23	32		T24	179		T25	144

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3173014	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

19677639

1

T23

116

T24

474

T25

323

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	116679	1			T25	4		T26	2		T27	12
valid_sources[0x01]	88167	1			T23	2		T26	9		T27	14
valid_sources[0x02]	81907	1			T27	12		T30	7		T32	573
valid_sources[0x03]	83759	1			T27	13		T32	507		T33	20
valid_sources[0x04]	96361	1			T25	2		T27	14		T32	520
valid_sources[0x05]	80828	1			T23	2		T25	8		T27	21
valid_sources[0x06]	84447	1			T25	1		T27	8		T32	522
valid_sources[0x07]	77396	1			T23	1		T27	15		T32	540
valid_sources[0x08]	91491	1			T27	21		T31	1		T32	538
valid_sources[0x09]	87324	1			T27	15		T31	1		T32	505
valid_sources[0x0a]	87082	1			T26	1		T27	15		T32	502
valid_sources[0x0b]	97683	1			T25	1		T26	2		T27	6
valid_sources[0x0c]	93184	1			T26	2		T27	14		T31	2
valid_sources[0x0d]	83712	1			T26	1		T27	22		T32	548
valid_sources[0x0e]	95003	1			T23	1		T25	4		T26	2
valid_sources[0x0f]	84746	1			T26	2		T27	15		T31	1
valid_sources[0x10]	94160	1			T23	1		T27	19		T28	1
valid_sources[0x11]	87226	1			T27	14		T31	5		T32	520
valid_sources[0x12]	83497	1			T23	1		T27	15		T31	2
valid_sources[0x13]	80454	1			T25	4		T27	28		T32	546
valid_sources[0x14]	82260	1			T23	1		T25	3		T27	22
valid_sources[0x15]	85299	1			T26	1		T27	16		T32	502
valid_sources[0x16]	92181	1			T23	2		T26	2		T27	18
valid_sources[0x17]	90359	1			T23	2		T25	6		T27	23
valid_sources[0x18]	81672	1			T23	2		T26	3		T27	19
valid_sources[0x19]	83176	1			T23	2		T26	1		T27	13
valid_sources[0x1a]	124156	1			T25	3		T27	11		T32	523
valid_sources[0x1b]	77137	1			T26	2		T27	15		T32	467
valid_sources[0x1c]	75515	1			T23	1		T26	1		T27	16
valid_sources[0x1d]	78750	1			T27	18		T32	578		T68	2
valid_sources[0x1e]	139635	1			T27	17		T32	559		T33	28
valid_sources[0x1f]	79363	1			T25	3		T26	1		T27	15
valid_sources[0x20]	168098	1			T26	1		T27	14		T30	6
valid_sources[0x21]	91392	1			T25	1		T26	1		T27	13
valid_sources[0x22]	121382	1			T23	1		T27	7		T30	3
valid_sources[0x23]	82922	1			T23	2		T25	3		T27	17
valid_sources[0x24]	83561	1			T23	5		T26	1		T27	25
valid_sources[0x25]	99178	1			T23	2		T26	1		T27	12
valid_sources[0x26]	119094	1			T25	1		T26	1		T27	18
valid_sources[0x27]	89188	1			T23	1		T26	4		T27	8
valid_sources[0x28]	194609	1			T27	9		T31	3		T32	538
valid_sources[0x29]	92190	1			T23	2		T25	1		T26	1
valid_sources[0x2a]	83035	1			T23	1		T25	1		T26	1
valid_sources[0x2b]	76955	1			T23	1		T25	3		T27	12
valid_sources[0x2c]	90373	1			T27	20		T31	1		T32	552
valid_sources[0x2d]	97317	1			T23	1		T27	20		T31	1
valid_sources[0x2e]	86755	1			T27	10		T31	2		T32	516
valid_sources[0x2f]	80522	1			T27	22		T31	1		T32	476
valid_sources[0x30]	95482	1			T23	1		T27	13		T31	2
valid_sources[0x31]	83043	1			T26	1		T27	12		T32	563
valid_sources[0x32]	93316	1			T23	1		T26	6		T27	12
valid_sources[0x33]	91077	1			T27	11		T28	1		T32	564
valid_sources[0x34]	80779	1			T27	11		T32	505		T33	25
valid_sources[0x35]	84730	1			T27	21		T28	1		T31	1
valid_sources[0x36]	82781	1			T23	2		T25	2		T27	10
valid_sources[0x37]	137216	1			T23	1		T25	4		T26	6
valid_sources[0x38]	86588	1			T26	3		T27	14		T32	496
valid_sources[0x39]	83211	1			T23	3		T27	15		T31	1
valid_sources[0x3a]	82049	1			T27	22		T32	527		T68	3
valid_sources[0x3b]	82581	1			T26	5		T27	21		T32	517
valid_sources[0x3c]	79450	1			T23	1		T27	14		T31	1
valid_sources[0x3d]	81766	1			T25	1		T26	1		T27	16
valid_sources[0x3e]	190770	1			T23	3		T26	7		T27	23
valid_sources[0x3f]	82218	1			T23	3		T25	3		T26	2
valid_sources[0x40]	84935	1			T27	11		T32	510		T33	8
valid_sources[0x41]	83828	1			T25	4		T27	9		T31	2
valid_sources[0x42]	219298	1			T25	2		T26	1		T27	11
valid_sources[0x43]	82350	1			T25	4		T26	1		T27	7
valid_sources[0x44]	89130	1			T27	17		T31	1		T32	544
valid_sources[0x45]	91345	1			T27	14		T32	531		T68	3
valid_sources[0x46]	85477	1			T23	1		T27	9		T32	494
valid_sources[0x47]	88358	1			T25	1		T27	15		T31	2
valid_sources[0x48]	89760	1			T23	1		T26	4		T27	20
valid_sources[0x49]	79007	1			T23	1		T25	5		T27	8
valid_sources[0x4a]	78249	1			T23	3		T26	1		T27	16
valid_sources[0x4b]	82122	1			T23	3		T27	8		T32	464
valid_sources[0x4c]	87209	1			T23	1		T26	1		T27	5
valid_sources[0x4d]	78977	1			T25	1		T26	2		T27	17
valid_sources[0x4e]	82573	1			T23	1		T25	14		T26	4
valid_sources[0x4f]	92921	1			T25	4		T26	2		T27	22
valid_sources[0x50]	87066	1			T27	8		T31	2		T32	519
valid_sources[0x51]	86712	1			T23	1		T27	14		T32	515
valid_sources[0x52]	84004	1			T26	1		T27	18		T31	2
valid_sources[0x53]	83907	1			T25	8		T27	18		T32	548
valid_sources[0x54]	86743	1			T23	1		T27	18		T31	3
valid_sources[0x55]	88397	1			T23	1		T26	1		T27	18
valid_sources[0x56]	81215	1			T23	1		T27	14		T31	2
valid_sources[0x57]	81545	1			T23	1		T27	18		T31	4
valid_sources[0x58]	92883	1			T23	1		T25	11		T27	15
valid_sources[0x59]	78487	1			T24	576		T27	13		T31	1
valid_sources[0x5a]	91208	1			T27	19		T30	1		T32	581
valid_sources[0x5b]	89734	1			T23	1		T25	2		T26	2
valid_sources[0x5c]	81064	1			T23	1		T26	6		T27	10
valid_sources[0x5d]	79437	1			T27	18		T31	1		T32	504
valid_sources[0x5e]	76900	1			T25	1		T26	2		T27	12
valid_sources[0x5f]	83358	1			T26	4		T27	16		T32	546
valid_sources[0x60]	86922	1			T26	2		T27	20		T32	541
valid_sources[0x61]	76727	1			T23	1		T27	18		T32	559
valid_sources[0x62]	85641	1			T23	2		T26	2		T27	22
valid_sources[0x63]	82094	1			T23	2		T25	2		T27	25
valid_sources[0x64]	202765	1			T26	4		T27	18		T31	3
valid_sources[0x65]	86956	1			T25	2		T26	2		T27	16
valid_sources[0x66]	93255	1			T27	23		T32	509		T68	5
valid_sources[0x67]	79207	1			T26	1		T27	23		T30	20
valid_sources[0x68]	90538	1			T23	1		T26	1		T27	10
valid_sources[0x69]	126664	1			T25	3		T27	16		T32	553
valid_sources[0x6a]	80334	1			T27	19		T32	546		T68	3
valid_sources[0x6b]	84208	1			T27	11		T31	2		T32	504
valid_sources[0x6c]	78081	1			T26	2		T27	10		T32	529
valid_sources[0x6d]	80215	1			T26	3		T27	12		T31	1
valid_sources[0x6e]	82545	1			T26	1		T27	19		T32	586
valid_sources[0x6f]	86880	1			T26	1		T27	15		T31	1
valid_sources[0x70]	75263	1			T23	2		T25	5		T27	13
valid_sources[0x71]	76888	1			T25	2		T27	14		T31	1
valid_sources[0x72]	84592	1			T25	2		T26	3		T27	7
valid_sources[0x73]	81751	1			T26	3		T27	17		T28	1
valid_sources[0x74]	74350	1			T27	23		T31	4		T32	533
valid_sources[0x75]	91622	1			T27	17		T32	500		T33	10
valid_sources[0x76]	81483	1			T23	2		T27	21		T32	525
valid_sources[0x77]	76927	1			T27	16		T32	535		T68	2
valid_sources[0x78]	83638	1			T27	15		T31	6		T32	518
valid_sources[0x79]	83933	1			T26	3		T27	13		T31	1
valid_sources[0x7a]	86518	1			T27	17		T32	500		T33	17
valid_sources[0x7b]	78253	1			T26	2		T27	17		T32	487
valid_sources[0x7c]	74973	1			T26	2		T27	19		T31	1
valid_sources[0x7d]	94615	1			T25	2		T27	14		T32	499
valid_sources[0x7e]	87933	1			T25	4		T26	1		T27	15
valid_sources[0x7f]	81070	1			T23	1		T27	20		T32	548
valid_sources[0x80]	82024	1			T23	2		T26	1		T27	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5227866

1

T23

47

T24

124

T25

41

values[0x0]

all_enables

biggest_size

6742715

1

T23

28

T24

149

T25

134

values[0x1]

all_enables

biggest_size

6742819

1

T23

32

T24

179

T25

144