Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	178759855	0	0	0
ctrl_en_input_filter_rd_A	178759855	60982	0	0
intr_ctrl_en_falling_rd_A	178759855	62839	0	0
intr_ctrl_en_lvlhigh_rd_A	178759855	62615	0	0
intr_ctrl_en_lvllow_rd_A	178759855	64390	0	0
intr_ctrl_en_rising_rd_A	178759855	60730	0	0
intr_enable_rd_A	178759855	61878	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178759855	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178759855	60982	0	0
T1	136310	3230	0	0
T2	5596	3	0	0
T3	0	1674	0	0
T4	0	4	0	0
T5	0	228	0	0
T6	0	1644	0	0
T7	0	90	0	0
T8	0	213	0	0
T9	0	5	0	0
T10	0	139	0	0
T11	4894	0	0	0
T12	2153	0	0	0
T13	4787	0	0	0
T14	27856	0	0	0
T15	2606	0	0	0
T16	46273	0	0	0
T17	3510	0	0	0
T18	3965	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178759855	62839	0	0
T1	136310	3421	0	0
T2	5596	0	0	0
T3	0	1484	0	0
T5	0	282	0	0
T6	0	1527	0	0
T7	0	95	0	0
T8	0	257	0	0
T10	0	115	0	0
T11	4894	0	0	0
T12	2153	0	0	0
T13	4787	0	0	0
T14	27856	0	0	0
T15	2606	0	0	0
T16	46273	0	0	0
T17	3510	0	0	0
T18	3965	0	0	0
T19	0	1256	0	0
T20	0	207	0	0
T21	0	217	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178759855	62615	0	0
T1	136310	3550	0	0
T2	5596	10	0	0
T3	0	1531	0	0
T5	0	151	0	0
T6	0	1523	0	0
T7	0	118	0	0
T8	0	221	0	0
T9	0	2	0	0
T10	0	165	0	0
T11	4894	0	0	0
T12	2153	0	0	0
T13	4787	0	0	0
T14	27856	0	0	0
T15	2606	0	0	0
T16	46273	0	0	0
T17	3510	0	0	0
T18	3965	0	0	0
T19	0	1273	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178759855	64390	0	0
T1	136310	3547	0	0
T2	5596	0	0	0
T3	0	1453	0	0
T4	0	10	0	0
T5	0	148	0	0
T6	0	1549	0	0
T7	0	91	0	0
T8	0	230	0	0
T9	0	4	0	0
T10	0	90	0	0
T11	4894	0	0	0
T12	2153	0	0	0
T13	4787	0	0	0
T14	27856	0	0	0
T15	2606	0	0	0
T16	46273	0	0	0
T17	3510	0	0	0
T18	3965	0	0	0
T19	0	1228	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178759855	60730	0	0
T1	136310	3398	0	0
T2	5596	7	0	0
T3	0	1484	0	0
T4	0	2	0	0
T5	0	312	0	0
T6	0	1493	0	0
T7	0	93	0	0
T8	0	250	0	0
T10	0	108	0	0
T11	4894	0	0	0
T12	2153	0	0	0
T13	4787	0	0	0
T14	27856	0	0	0
T15	2606	0	0	0
T16	46273	0	0	0
T17	3510	0	0	0
T18	3965	0	0	0
T19	0	1452	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178759855	61878	0	0
T1	136310	3451	0	0
T2	5596	0	0	0
T3	0	1393	0	0
T5	0	271	0	0
T6	0	1605	0	0
T7	0	81	0	0
T8	0	331	0	0
T10	0	151	0	0
T11	4894	0	0	0
T12	2153	0	0	0
T13	4787	0	0	0
T14	27856	0	0	0
T15	2606	0	0	0
T16	46273	0	0	0
T17	3510	0	0	0
T18	3965	0	0	0
T19	0	1268	0	0
T20	0	128	0	0
T22	0	3	0	0