Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3846232	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

17759181

1

T22

364

T1

27823

T11

37293

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8496177	1			T22	69		T1	17104		T11	20286
values[0x0]	6431299	1			T22	155		T1	9736		T11	13437
values[0x1]	6677937	1			T22	174		T1	9622		T11	13638

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2941039	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

18664374

1

T22

368

T1

29536

T11

39271

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	76930	1			T1	114		T11	168		T15	1
valid_sources[0x01]	81298	1			T1	99		T11	184		T24	25
valid_sources[0x02]	84975	1			T1	129		T11	192		T15	8
valid_sources[0x03]	76672	1			T1	107		T11	189		T14	1
valid_sources[0x04]	78199	1			T1	124		T11	197		T24	6
valid_sources[0x05]	80601	1			T1	184		T11	164		T12	13
valid_sources[0x06]	76473	1			T1	139		T11	184		T14	1
valid_sources[0x07]	79159	1			T1	68		T11	170		T17	1
valid_sources[0x08]	75661	1			T1	187		T11	212		T17	2
valid_sources[0x09]	79723	1			T1	130		T11	185		T17	2
valid_sources[0x0a]	77111	1			T1	119		T11	187		T15	5
valid_sources[0x0b]	109031	1			T1	119		T11	176		T17	6
valid_sources[0x0c]	77762	1			T1	153		T11	218		T17	1
valid_sources[0x0d]	76806	1			T1	129		T11	167		T17	1
valid_sources[0x0e]	77298	1			T1	112		T11	166		T15	4
valid_sources[0x0f]	77431	1			T1	147		T11	148		T13	10
valid_sources[0x10]	77385	1			T1	163		T11	164		T17	2
valid_sources[0x11]	76197	1			T1	160		T11	176		T14	1
valid_sources[0x12]	78035	1			T1	142		T11	196		T12	8
valid_sources[0x13]	86602	1			T1	172		T11	199		T12	3
valid_sources[0x14]	82493	1			T1	141		T11	167		T14	1
valid_sources[0x15]	78561	1			T1	106		T11	182		T17	2
valid_sources[0x16]	78920	1			T1	167		T11	199		T14	1
valid_sources[0x17]	79397	1			T1	135		T11	192		T14	2
valid_sources[0x18]	77938	1			T1	107		T11	206		T24	18
valid_sources[0x19]	80364	1			T1	161		T11	175		T14	2
valid_sources[0x1a]	80770	1			T1	160		T11	160		T12	1
valid_sources[0x1b]	78129	1			T1	114		T11	175		T14	4
valid_sources[0x1c]	77172	1			T1	208		T11	187		T17	2
valid_sources[0x1d]	82669	1			T1	161		T11	164		T15	1
valid_sources[0x1e]	77009	1			T1	154		T11	167		T17	2
valid_sources[0x1f]	78246	1			T1	197		T11	169		T15	6
valid_sources[0x20]	80383	1			T1	131		T11	195		T15	1
valid_sources[0x21]	77320	1			T1	117		T11	195		T24	17
valid_sources[0x22]	192308	1			T1	126		T11	212		T14	1
valid_sources[0x23]	76626	1			T1	193		T11	213		T17	2
valid_sources[0x24]	76336	1			T1	159		T11	188		T14	3
valid_sources[0x25]	75306	1			T1	115		T11	177		T13	22
valid_sources[0x26]	76801	1			T1	158		T11	162		T12	12
valid_sources[0x27]	76386	1			T1	148		T11	194		T13	9
valid_sources[0x28]	78676	1			T1	106		T11	179		T13	17
valid_sources[0x29]	76617	1			T1	124		T11	195		T12	5
valid_sources[0x2a]	80215	1			T1	135		T11	169		T12	15
valid_sources[0x2b]	80308	1			T1	138		T11	190		T14	2
valid_sources[0x2c]	75294	1			T1	149		T11	205		T14	11
valid_sources[0x2d]	77452	1			T1	169		T11	163		T14	2
valid_sources[0x2e]	80132	1			T1	141		T11	202		T13	33
valid_sources[0x2f]	78795	1			T1	125		T11	154		T17	1
valid_sources[0x30]	77873	1			T1	132		T11	180		T15	2
valid_sources[0x31]	79062	1			T1	140		T11	165		T12	8
valid_sources[0x32]	77257	1			T1	216		T11	168		T15	7
valid_sources[0x33]	76055	1			T1	161		T11	172		T12	1
valid_sources[0x34]	80045	1			T1	115		T11	185		T14	2
valid_sources[0x35]	79671	1			T1	135		T11	198		T12	27
valid_sources[0x36]	78094	1			T1	205		T11	174		T12	4
valid_sources[0x37]	81353	1			T1	109		T11	158		T24	9
valid_sources[0x38]	79677	1			T1	120		T11	184		T14	1
valid_sources[0x39]	79268	1			T1	147		T11	192		T24	15
valid_sources[0x3a]	76750	1			T1	167		T11	141		T17	3
valid_sources[0x3b]	77771	1			T1	106		T11	174		T14	1
valid_sources[0x3c]	184316	1			T1	120		T11	172		T15	1
valid_sources[0x3d]	80995	1			T1	138		T11	199		T15	1
valid_sources[0x3e]	78770	1			T1	135		T11	195		T17	3
valid_sources[0x3f]	80860	1			T1	137		T11	145		T15	1
valid_sources[0x40]	77760	1			T1	168		T11	155		T17	1
valid_sources[0x41]	76800	1			T1	189		T11	219		T17	3
valid_sources[0x42]	78788	1			T1	163		T11	153		T17	2
valid_sources[0x43]	80377	1			T1	151		T11	200		T15	2
valid_sources[0x44]	82364	1			T1	193		T11	177		T15	1
valid_sources[0x45]	77930	1			T1	140		T11	187		T12	9
valid_sources[0x46]	81638	1			T1	166		T11	193		T17	1
valid_sources[0x47]	76018	1			T1	169		T11	192		T24	46
valid_sources[0x48]	79077	1			T1	146		T11	203		T13	13
valid_sources[0x49]	75240	1			T1	140		T11	169		T14	4
valid_sources[0x4a]	79971	1			T1	159		T11	186		T15	3
valid_sources[0x4b]	78553	1			T1	84		T11	173		T17	4
valid_sources[0x4c]	81356	1			T1	185		T11	212		T13	18
valid_sources[0x4d]	77871	1			T1	129		T11	216		T24	8
valid_sources[0x4e]	77423	1			T1	151		T11	209		T13	2
valid_sources[0x4f]	80595	1			T1	175		T11	179		T13	8
valid_sources[0x50]	75205	1			T1	130		T11	187		T24	25
valid_sources[0x51]	161445	1			T1	154		T11	194		T15	7
valid_sources[0x52]	82375	1			T1	128		T11	161		T13	1
valid_sources[0x53]	82096	1			T1	91		T11	147		T15	9
valid_sources[0x54]	82959	1			T1	112		T11	166		T17	2
valid_sources[0x55]	78220	1			T1	123		T11	187		T13	1
valid_sources[0x56]	80541	1			T1	169		T11	184		T17	1
valid_sources[0x57]	79853	1			T1	121		T11	193		T24	21
valid_sources[0x58]	76459	1			T1	159		T11	207		T14	1
valid_sources[0x59]	79970	1			T1	132		T11	212		T13	18
valid_sources[0x5a]	132488	1			T1	118		T11	194		T14	1
valid_sources[0x5b]	80500	1			T1	141		T11	185		T14	6
valid_sources[0x5c]	79060	1			T1	135		T11	178		T14	1
valid_sources[0x5d]	83037	1			T1	136		T11	168		T17	1
valid_sources[0x5e]	77443	1			T1	134		T11	176		T24	20
valid_sources[0x5f]	77033	1			T1	91		T11	195		T14	2
valid_sources[0x60]	81099	1			T1	137		T11	179		T12	4
valid_sources[0x61]	77132	1			T1	116		T11	199		T17	3
valid_sources[0x62]	76951	1			T1	150		T11	187		T17	1
valid_sources[0x63]	76854	1			T1	130		T11	182		T17	4
valid_sources[0x64]	77702	1			T1	104		T11	207		T15	1
valid_sources[0x65]	76984	1			T1	180		T11	207		T17	1
valid_sources[0x66]	79144	1			T1	194		T11	171		T17	1
valid_sources[0x67]	77978	1			T1	133		T11	178		T24	2
valid_sources[0x68]	80379	1			T1	190		T11	194		T14	3
valid_sources[0x69]	83112	1			T1	148		T11	173		T24	21
valid_sources[0x6a]	78959	1			T1	90		T11	169		T14	5
valid_sources[0x6b]	78451	1			T1	170		T11	192		T13	4
valid_sources[0x6c]	75907	1			T1	106		T11	200		T17	1
valid_sources[0x6d]	76649	1			T1	136		T11	190		T24	10
valid_sources[0x6e]	77780	1			T1	155		T11	199		T12	6
valid_sources[0x6f]	76041	1			T1	163		T11	177		T17	2
valid_sources[0x70]	77977	1			T1	153		T11	175		T14	5
valid_sources[0x71]	76468	1			T1	107		T11	199		T14	5
valid_sources[0x72]	78499	1			T1	134		T11	182		T24	11
valid_sources[0x73]	81862	1			T1	163		T11	160		T17	2
valid_sources[0x74]	83212	1			T1	127		T11	208		T15	9
valid_sources[0x75]	80277	1			T1	147		T11	175		T17	1
valid_sources[0x76]	79193	1			T1	140		T11	194		T15	11
valid_sources[0x77]	78878	1			T1	173		T11	184		T12	16
valid_sources[0x78]	76594	1			T1	149		T11	192		T13	1
valid_sources[0x79]	79690	1			T1	105		T11	191		T13	3
valid_sources[0x7a]	76309	1			T1	165		T11	161		T14	1
valid_sources[0x7b]	234074	1			T1	113		T11	160		T17	1
valid_sources[0x7c]	77424	1			T1	177		T11	188		T15	5
valid_sources[0x7d]	77537	1			T1	100		T11	178		T17	2
valid_sources[0x7e]	79027	1			T1	165		T11	198		T24	18
valid_sources[0x7f]	76282	1			T1	97		T11	194		T14	2
valid_sources[0x80]	81482	1			T1	150		T11	175		T24	29

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4945771

1

T22

35

T1

8465

T11

10218

values[0x0]

all_enables

biggest_size

6406518

1

T22

155

T1

9736

T11

13437

values[0x1]

all_enables

biggest_size

6406892

1

T22

174

T1

9622

T11

13638