Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	188631963	0	0	0
ctrl_en_input_filter_rd_A	188631963	104917	0	0
intr_ctrl_en_falling_rd_A	188631963	107281	0	0
intr_ctrl_en_lvlhigh_rd_A	188631963	104227	0	0
intr_ctrl_en_lvllow_rd_A	188631963	105772	0	0
intr_ctrl_en_rising_rd_A	188631963	103536	0	0
intr_enable_rd_A	188631963	104115	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188631963	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188631963	104917	0	0
T1	451073	1978	0	0
T2	0	125	0	0
T3	0	3076	0	0
T4	0	9	0	0
T5	0	4462	0	0
T6	0	47	0	0
T7	0	319	0	0
T8	0	8720	0	0
T9	0	227	0	0
T10	0	4	0	0
T11	468455	0	0	0
T12	4141	0	0	0
T13	7089	0	0	0
T14	2767	0	0	0
T15	3544	0	0	0
T16	32348	0	0	0
T17	4057	0	0	0
T18	1298	0	0	0
T19	5008	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188631963	107281	0	0
T1	451073	2176	0	0
T2	0	108	0	0
T3	0	3056	0	0
T5	0	4865	0	0
T6	0	63	0	0
T7	0	317	0	0
T8	0	8451	0	0
T9	0	197	0	0
T10	0	10	0	0
T11	468455	0	0	0
T12	4141	0	0	0
T13	7089	0	0	0
T14	2767	0	0	0
T15	3544	0	0	0
T16	32348	0	0	0
T17	4057	0	0	0
T18	1298	0	0	0
T19	5008	0	0	0
T20	0	4	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188631963	104227	0	0
T1	451073	1984	0	0
T2	0	155	0	0
T3	0	2887	0	0
T4	0	3	0	0
T5	0	4723	0	0
T6	0	67	0	0
T7	0	446	0	0
T8	0	8550	0	0
T9	0	194	0	0
T10	0	7	0	0
T11	468455	0	0	0
T12	4141	0	0	0
T13	7089	0	0	0
T14	2767	0	0	0
T15	3544	0	0	0
T16	32348	0	0	0
T17	4057	0	0	0
T18	1298	0	0	0
T19	5008	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188631963	105772	0	0
T1	451073	2116	0	0
T2	0	77	0	0
T3	0	3224	0	0
T5	0	4386	0	0
T6	0	60	0	0
T7	0	447	0	0
T8	0	8905	0	0
T9	0	164	0	0
T11	468455	0	0	0
T12	4141	0	0	0
T13	7089	0	0	0
T14	2767	0	0	0
T15	3544	0	0	0
T16	32348	0	0	0
T17	4057	0	0	0
T18	1298	0	0	0
T19	5008	0	0	0
T20	0	4	0	0
T21	0	5255	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188631963	103536	0	0
T1	451073	2098	0	0
T2	0	106	0	0
T3	0	3082	0	0
T4	0	22	0	0
T5	0	4315	0	0
T6	0	39	0	0
T7	0	416	0	0
T8	0	8709	0	0
T9	0	218	0	0
T10	0	10	0	0
T11	468455	0	0	0
T12	4141	0	0	0
T13	7089	0	0	0
T14	2767	0	0	0
T15	3544	0	0	0
T16	32348	0	0	0
T17	4057	0	0	0
T18	1298	0	0	0
T19	5008	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188631963	104115	0	0
T1	451073	2079	0	0
T2	0	129	0	0
T3	0	3181	0	0
T4	0	5	0	0
T5	0	4402	0	0
T6	0	39	0	0
T7	0	424	0	0
T8	0	8618	0	0
T9	0	198	0	0
T11	468455	0	0	0
T12	4141	0	0	0
T13	7089	0	0	0
T14	2767	0	0	0
T15	3544	0	0	0
T16	32348	0	0	0
T17	4057	0	0	0
T18	1298	0	0	0
T19	5008	0	0	0
T20	0	19	0	0