Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 3557031 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 15947871 1 T22 57587 T23 777 T24 1121



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 7778527 1 T22 33250 T23 954 T24 1323
values[0x0] 5763752 1 T22 20407 T23 159 T24 246
values[0x1] 5962623 1 T22 20514 T23 164 T24 217



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 2734670 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 16770232 1 T22 60855 T23 868 T24 1254



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 79252 1 T22 292 T23 22 T11 2
valid_sources[0x01] 74849 1 T22 283 T23 13 T28 1
valid_sources[0x02] 85045 1 T22 334 T30 4 T1 1
valid_sources[0x03] 77103 1 T22 304 T25 1 T1 2
valid_sources[0x04] 73567 1 T22 275 T27 1 T30 2
valid_sources[0x05] 74419 1 T22 283 T25 1 T27 1
valid_sources[0x06] 72465 1 T22 265 T23 3 T27 3
valid_sources[0x07] 71378 1 T22 268 T25 3 T11 6
valid_sources[0x08] 68467 1 T22 281 T23 4 T11 6
valid_sources[0x09] 70949 1 T22 262 T23 4 T11 4
valid_sources[0x0a] 84137 1 T22 232 T23 2 T28 1
valid_sources[0x0b] 69902 1 T22 315 T23 6 T25 1
valid_sources[0x0c] 72972 1 T22 322 T23 1 T25 1
valid_sources[0x0d] 74668 1 T22 334 T23 2 T28 1
valid_sources[0x0e] 74485 1 T22 311 T23 7 T25 1
valid_sources[0x0f] 72307 1 T22 285 T25 6 T27 4
valid_sources[0x10] 68833 1 T22 293 T23 4 T11 6
valid_sources[0x11] 76872 1 T22 266 T25 3 T28 1
valid_sources[0x12] 72989 1 T22 309 T23 10 T25 2
valid_sources[0x13] 72451 1 T22 266 T25 2 T27 1
valid_sources[0x14] 69278 1 T22 261 T23 4 T25 3
valid_sources[0x15] 70968 1 T22 327 T23 8 T25 1
valid_sources[0x16] 72401 1 T22 320 T23 1 T25 3
valid_sources[0x17] 74306 1 T22 306 T27 2 T30 1
valid_sources[0x18] 71368 1 T22 287 T23 14 T27 2
valid_sources[0x19] 73157 1 T22 284 T23 5 T11 8
valid_sources[0x1a] 72208 1 T22 290 T23 3 T25 1
valid_sources[0x1b] 100305 1 T22 267 T25 3 T11 3
valid_sources[0x1c] 75013 1 T22 263 T23 5 T25 1
valid_sources[0x1d] 74185 1 T22 298 T23 1 T30 1
valid_sources[0x1e] 70235 1 T22 315 T25 7 T28 1
valid_sources[0x1f] 80980 1 T22 314 T23 6 T25 3
valid_sources[0x20] 74537 1 T22 292 T23 6 T25 2
valid_sources[0x21] 71876 1 T22 301 T23 7 T25 4
valid_sources[0x22] 74597 1 T22 280 T23 3 T27 2
valid_sources[0x23] 72039 1 T22 317 T25 2 T11 8
valid_sources[0x24] 70169 1 T22 292 T23 7 T25 2
valid_sources[0x25] 69278 1 T22 242 T23 17 T25 3
valid_sources[0x26] 72344 1 T22 307 T23 13 T25 6
valid_sources[0x27] 70629 1 T22 305 T25 5 T11 4
valid_sources[0x28] 70891 1 T22 317 T23 4 T25 1
valid_sources[0x29] 70959 1 T22 273 T23 2 T27 3
valid_sources[0x2a] 70687 1 T22 306 T23 23 T25 3
valid_sources[0x2b] 70506 1 T22 324 T11 7 T13 3
valid_sources[0x2c] 69873 1 T22 299 T23 22 T25 3
valid_sources[0x2d] 68171 1 T22 306 T23 25 T11 7
valid_sources[0x2e] 71925 1 T22 347 T28 1 T11 5
valid_sources[0x2f] 76559 1 T22 301 T23 11 T25 4
valid_sources[0x30] 116006 1 T22 320 T23 2 T24 1786
valid_sources[0x31] 69644 1 T22 289 T23 3 T25 2
valid_sources[0x32] 71933 1 T22 290 T23 11 T25 1
valid_sources[0x33] 73767 1 T22 277 T23 4 T25 2
valid_sources[0x34] 76685 1 T22 265 T23 1 T25 1
valid_sources[0x35] 71129 1 T22 321 T23 8 T27 7
valid_sources[0x36] 74753 1 T22 309 T27 6 T28 1
valid_sources[0x37] 69338 1 T22 300 T23 16 T11 3
valid_sources[0x38] 69028 1 T22 283 T23 11 T25 2
valid_sources[0x39] 76077 1 T22 269 T25 1 T1 2
valid_sources[0x3a] 71003 1 T22 299 T23 5 T27 1
valid_sources[0x3b] 72190 1 T22 303 T30 26 T11 2
valid_sources[0x3c] 71793 1 T22 307 T25 2 T1 1
valid_sources[0x3d] 73945 1 T22 272 T23 10 T27 1
valid_sources[0x3e] 70321 1 T22 299 T23 1 T27 2
valid_sources[0x3f] 73372 1 T22 306 T28 1 T30 2
valid_sources[0x40] 71907 1 T22 278 T23 12 T25 3
valid_sources[0x41] 70802 1 T22 293 T23 2 T27 1
valid_sources[0x42] 71309 1 T22 327 T23 17 T25 4
valid_sources[0x43] 69377 1 T22 286 T28 1 T11 3
valid_sources[0x44] 77302 1 T22 306 T23 3 T25 2
valid_sources[0x45] 71360 1 T22 282 T28 1 T1 1
valid_sources[0x46] 71271 1 T22 287 T11 6 T13 1
valid_sources[0x47] 71259 1 T22 277 T30 1 T11 3
valid_sources[0x48] 72913 1 T22 319 T23 5 T28 2
valid_sources[0x49] 74336 1 T22 314 T23 9 T25 2
valid_sources[0x4a] 83556 1 T22 289 T23 7 T25 2
valid_sources[0x4b] 75997 1 T22 278 T25 2 T27 1
valid_sources[0x4c] 70377 1 T22 315 T23 13 T25 3
valid_sources[0x4d] 72052 1 T22 278 T23 8 T25 2
valid_sources[0x4e] 74162 1 T22 273 T23 6 T25 5
valid_sources[0x4f] 73271 1 T22 276 T25 3 T11 5
valid_sources[0x50] 75060 1 T22 286 T23 5 T27 1
valid_sources[0x51] 71435 1 T22 288 T23 7 T25 1
valid_sources[0x52] 68481 1 T22 271 T27 1 T1 2
valid_sources[0x53] 75082 1 T22 281 T11 4 T12 2
valid_sources[0x54] 71272 1 T22 294 T23 1 T25 1
valid_sources[0x55] 74803 1 T22 278 T27 1 T11 3
valid_sources[0x56] 74351 1 T22 280 T23 3 T25 1
valid_sources[0x57] 69379 1 T22 310 T23 6 T25 2
valid_sources[0x58] 71340 1 T22 305 T23 7 T25 1
valid_sources[0x59] 72957 1 T22 287 T25 3 T27 1
valid_sources[0x5a] 95417 1 T22 298 T23 12 T28 1
valid_sources[0x5b] 70647 1 T22 306 T23 6 T30 3
valid_sources[0x5c] 71635 1 T22 306 T23 1 T25 1
valid_sources[0x5d] 75164 1 T22 252 T23 14 T28 1
valid_sources[0x5e] 71372 1 T22 288 T25 5 T27 1
valid_sources[0x5f] 74634 1 T22 290 T25 1 T28 1
valid_sources[0x60] 70929 1 T22 289 T23 2 T25 1
valid_sources[0x61] 76970 1 T22 267 T23 6 T27 1
valid_sources[0x62] 71834 1 T22 263 T23 1 T11 4
valid_sources[0x63] 70706 1 T22 288 T23 20 T25 1
valid_sources[0x64] 72369 1 T22 258 T23 1 T25 1
valid_sources[0x65] 72258 1 T22 281 T23 1 T27 1
valid_sources[0x66] 74360 1 T22 308 T23 6 T25 2
valid_sources[0x67] 77288 1 T22 290 T23 1 T25 3
valid_sources[0x68] 70373 1 T22 296 T25 4 T11 8
valid_sources[0x69] 79020 1 T22 289 T23 9 T28 1
valid_sources[0x6a] 229328 1 T22 268 T23 5 T25 1
valid_sources[0x6b] 72316 1 T22 296 T27 2 T28 1
valid_sources[0x6c] 78704 1 T22 289 T23 2 T25 1
valid_sources[0x6d] 79861 1 T22 273 T30 4 T11 3
valid_sources[0x6e] 71966 1 T22 302 T28 2 T11 2
valid_sources[0x6f] 66754 1 T22 266 T23 7 T25 5
valid_sources[0x70] 123997 1 T22 259 T23 8 T28 1
valid_sources[0x71] 67663 1 T22 303 T23 1 T25 3
valid_sources[0x72] 72046 1 T22 262 T23 9 T25 1
valid_sources[0x73] 68023 1 T22 275 T30 2 T11 4
valid_sources[0x74] 71154 1 T22 300 T23 18 T27 1
valid_sources[0x75] 205882 1 T22 296 T23 11 T28 1
valid_sources[0x76] 70795 1 T22 277 T23 1 T28 1
valid_sources[0x77] 75254 1 T22 301 T23 5 T11 9
valid_sources[0x78] 69894 1 T22 287 T23 5 T28 1
valid_sources[0x79] 67548 1 T22 327 T11 5 T14 420
valid_sources[0x7a] 222472 1 T22 286 T23 1 T25 2
valid_sources[0x7b] 71657 1 T22 269 T23 2 T11 3
valid_sources[0x7c] 70654 1 T22 268 T23 9 T28 1
valid_sources[0x7d] 78043 1 T22 302 T23 20 T11 4
valid_sources[0x7e] 76621 1 T22 294 T23 15 T25 3
valid_sources[0x7f] 79157 1 T22 290 T25 3 T11 11
valid_sources[0x80] 71600 1 T22 258 T27 3 T1 2



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 4462967 1 T22 16666 T23 454 T24 658
values[0x0] all_enables biggest_size 5743411 1 T22 20407 T23 159 T24 246
values[0x1] all_enables biggest_size 5741493 1 T22 20514 T23 164 T24 217

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%