Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	163449128	0	0	0
ctrl_en_input_filter_rd_A	163449128	82793	0	0
intr_ctrl_en_falling_rd_A	163449128	86455	0	0
intr_ctrl_en_lvlhigh_rd_A	163449128	83358	0	0
intr_ctrl_en_lvllow_rd_A	163449128	85623	0	0
intr_ctrl_en_rising_rd_A	163449128	83554	0	0
intr_enable_rd_A	163449128	84296	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163449128	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163449128	82793	0	0
T1	4100	2	0	0
T2	307348	166	0	0
T3	0	284	0	0
T4	0	2034	0	0
T5	0	6	0	0
T6	0	247	0	0
T7	0	240	0	0
T8	0	323	0	0
T9	0	129	0	0
T10	0	3016	0	0
T11	6263	0	0	0
T12	2298	0	0	0
T13	8669	0	0	0
T14	454561	0	0	0
T15	13838	0	0	0
T16	2019	0	0	0
T17	4862	0	0	0
T18	324920	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163449128	86455	0	0
T2	307348	259	0	0
T3	0	243	0	0
T4	0	2162	0	0
T6	0	165	0	0
T7	0	318	0	0
T8	0	315	0	0
T9	0	121	0	0
T10	0	2956	0	0
T11	6263	0	0	0
T12	2298	0	0	0
T13	8669	0	0	0
T14	454561	0	0	0
T15	13838	0	0	0
T16	2019	0	0	0
T17	4862	0	0	0
T18	324920	0	0	0
T19	0	1950	0	0
T20	0	6458	0	0
T21	2452	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163449128	83358	0	0
T2	307348	247	0	0
T3	0	320	0	0
T4	0	2099	0	0
T6	0	269	0	0
T7	0	299	0	0
T8	0	308	0	0
T9	0	201	0	0
T10	0	2763	0	0
T11	6263	0	0	0
T12	2298	0	0	0
T13	8669	0	0	0
T14	454561	0	0	0
T15	13838	0	0	0
T16	2019	0	0	0
T17	4862	0	0	0
T18	324920	0	0	0
T19	0	2006	0	0
T20	0	6247	0	0
T21	2452	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163449128	85623	0	0
T2	307348	228	0	0
T3	0	383	0	0
T4	0	2123	0	0
T6	0	258	0	0
T7	0	285	0	0
T8	0	241	0	0
T9	0	140	0	0
T10	0	2685	0	0
T11	6263	0	0	0
T12	2298	0	0	0
T13	8669	0	0	0
T14	454561	0	0	0
T15	13838	0	0	0
T16	2019	0	0	0
T17	4862	0	0	0
T18	324920	0	0	0
T19	0	2125	0	0
T20	0	6514	0	0
T21	2452	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163449128	83554	0	0
T2	307348	232	0	0
T3	0	324	0	0
T4	0	2275	0	0
T5	0	2	0	0
T6	0	265	0	0
T7	0	332	0	0
T8	0	314	0	0
T9	0	179	0	0
T10	0	2947	0	0
T11	6263	0	0	0
T12	2298	0	0	0
T13	8669	0	0	0
T14	454561	0	0	0
T15	13838	0	0	0
T16	2019	0	0	0
T17	4862	0	0	0
T18	324920	0	0	0
T19	0	2224	0	0
T21	2452	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163449128	84296	0	0
T1	4100	3	0	0
T2	307348	268	0	0
T3	0	273	0	0
T4	0	2156	0	0
T5	0	4	0	0
T6	0	350	0	0
T7	0	253	0	0
T8	0	346	0	0
T9	0	172	0	0
T10	0	2887	0	0
T11	6263	0	0	0
T12	2298	0	0	0
T13	8669	0	0	0
T14	454561	0	0	0
T15	13838	0	0	0
T16	2019	0	0	0
T17	4862	0	0	0
T18	324920	0	0	0