Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3249260	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

13939291

1

T21

85

T22

894

T23

200

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	6994856	1			T21	43		T22	1342		T23	127
values[0x0]	5019590	1			T21	42		T22	111		T23	53
values[0x1]	5174105	1			T21	26		T22	106		T23	74

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2513061	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

14675490

1

T21

86

T22

1015

T23

211

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	60520	1			T22	7		T24	1		T25	2
valid_sources[0x01]	58761	1			T24	2		T25	4		T26	1
valid_sources[0x02]	60900	1			T24	2		T25	5		T26	2
valid_sources[0x03]	71672	1			T24	1		T25	2		T26	5
valid_sources[0x04]	61102	1			T21	1		T24	3		T25	7
valid_sources[0x05]	57569	1			T21	1		T22	10		T24	4
valid_sources[0x06]	57037	1			T21	2		T24	6		T25	4
valid_sources[0x07]	56588	1			T24	5		T25	2		T26	1
valid_sources[0x08]	60381	1			T22	3		T25	7		T27	1
valid_sources[0x09]	61530	1			T25	4		T26	1		T27	1
valid_sources[0x0a]	56088	1			T21	2		T22	21		T24	2
valid_sources[0x0b]	55597	1			T21	3		T22	15		T24	2
valid_sources[0x0c]	70417	1			T21	1		T22	7		T24	1
valid_sources[0x0d]	64956	1			T21	1		T22	2		T24	5
valid_sources[0x0e]	60652	1			T21	1		T22	43		T24	4
valid_sources[0x0f]	62701	1			T22	10		T24	4		T25	7
valid_sources[0x10]	60591	1			T22	7		T24	6		T25	6
valid_sources[0x11]	57606	1			T22	13		T24	5		T25	1
valid_sources[0x12]	58805	1			T21	1		T24	4		T25	3
valid_sources[0x13]	68739	1			T22	32		T24	3		T25	3
valid_sources[0x14]	65811	1			T21	1		T22	22		T24	8
valid_sources[0x15]	58977	1			T22	8		T24	2		T25	2
valid_sources[0x16]	60135	1			T21	1		T24	4		T25	2
valid_sources[0x17]	56384	1			T21	2		T22	7		T24	1
valid_sources[0x18]	58633	1			T22	23		T24	3		T25	5
valid_sources[0x19]	59224	1			T21	2		T22	8		T23	3
valid_sources[0x1a]	58113	1			T22	3		T23	5		T24	3
valid_sources[0x1b]	60388	1			T21	2		T22	30		T24	4
valid_sources[0x1c]	64148	1			T22	16		T24	1		T25	8
valid_sources[0x1d]	62750	1			T21	3		T24	8		T25	6
valid_sources[0x1e]	61922	1			T22	32		T24	4		T25	5
valid_sources[0x1f]	55596	1			T21	1		T24	7		T25	7
valid_sources[0x20]	57679	1			T21	1		T23	47		T24	4
valid_sources[0x21]	65717	1			T22	5		T24	9		T25	3
valid_sources[0x22]	65258	1			T22	3		T24	3		T25	11
valid_sources[0x23]	57639	1			T24	3		T25	5		T27	1
valid_sources[0x24]	59374	1			T22	13		T24	4		T25	8
valid_sources[0x25]	60426	1			T22	5		T24	6		T25	6
valid_sources[0x26]	60096	1			T24	1		T25	4		T27	1
valid_sources[0x27]	67968	1			T24	3		T25	10		T1	289
valid_sources[0x28]	62857	1			T21	1		T24	1		T25	9
valid_sources[0x29]	64225	1			T22	1		T23	12		T24	5
valid_sources[0x2a]	64893	1			T22	2		T24	2		T25	4
valid_sources[0x2b]	58176	1			T21	1		T22	37		T24	2
valid_sources[0x2c]	62586	1			T24	4		T25	2		T26	1
valid_sources[0x2d]	61321	1			T22	9		T24	2		T25	5
valid_sources[0x2e]	60252	1			T24	3		T25	4		T1	248
valid_sources[0x2f]	58437	1			T21	1		T22	25		T24	4
valid_sources[0x30]	54951	1			T21	1		T22	5		T24	3
valid_sources[0x31]	60373	1			T21	1		T22	5		T24	3
valid_sources[0x32]	95850	1			T22	10		T24	3		T25	6
valid_sources[0x33]	59872	1			T22	12		T24	3		T25	2
valid_sources[0x34]	54051	1			T21	1		T22	5		T24	3
valid_sources[0x35]	59210	1			T22	1		T24	2		T25	5
valid_sources[0x36]	61028	1			T24	1		T25	5		T27	3
valid_sources[0x37]	56603	1			T21	1		T24	4		T25	7
valid_sources[0x38]	56640	1			T22	6		T24	4		T25	8
valid_sources[0x39]	62342	1			T24	1		T25	6		T27	1
valid_sources[0x3a]	55428	1			T21	1		T23	6		T24	3
valid_sources[0x3b]	62710	1			T22	5		T24	2		T25	3
valid_sources[0x3c]	59261	1			T24	4		T25	7		T26	2
valid_sources[0x3d]	62105	1			T22	5		T24	3		T25	9
valid_sources[0x3e]	59954	1			T22	13		T24	3		T25	4
valid_sources[0x3f]	64654	1			T21	1		T22	10		T23	1
valid_sources[0x40]	56926	1			T21	1		T22	3		T24	3
valid_sources[0x41]	148296	1			T21	1		T24	5		T25	6
valid_sources[0x42]	55923	1			T24	4		T25	7		T27	1
valid_sources[0x43]	57432	1			T22	6		T24	4		T26	13
valid_sources[0x44]	65627	1			T21	1		T22	9		T24	3
valid_sources[0x45]	57974	1			T21	1		T22	7		T24	8
valid_sources[0x46]	59122	1			T21	1		T24	2		T25	8
valid_sources[0x47]	59349	1			T22	8		T24	4		T25	8
valid_sources[0x48]	173457	1			T22	9		T24	4		T25	6
valid_sources[0x49]	61654	1			T24	3		T25	3		T26	3
valid_sources[0x4a]	59878	1			T22	4		T23	6		T24	2
valid_sources[0x4b]	62450	1			T22	22		T24	6		T25	3
valid_sources[0x4c]	60616	1			T24	5		T25	7		T26	3
valid_sources[0x4d]	61328	1			T24	7		T25	6		T27	1
valid_sources[0x4e]	60827	1			T22	5		T24	3		T25	6
valid_sources[0x4f]	64507	1			T22	8		T24	2		T25	3
valid_sources[0x50]	61090	1			T21	1		T24	6		T25	1
valid_sources[0x51]	63948	1			T21	2		T22	14		T24	4
valid_sources[0x52]	56200	1			T22	6		T24	2		T25	3
valid_sources[0x53]	57647	1			T22	11		T24	3		T25	9
valid_sources[0x54]	57282	1			T21	1		T22	23		T24	1
valid_sources[0x55]	60418	1			T22	4		T24	6		T25	6
valid_sources[0x56]	59312	1			T22	2		T24	3		T25	3
valid_sources[0x57]	62100	1			T22	4		T24	2		T25	4
valid_sources[0x58]	55784	1			T22	10		T24	3		T25	5
valid_sources[0x59]	125698	1			T22	1		T24	7		T25	6
valid_sources[0x5a]	59672	1			T24	2		T25	5		T30	2
valid_sources[0x5b]	66036	1			T22	13		T24	4		T25	3
valid_sources[0x5c]	65726	1			T22	2		T25	2		T26	1
valid_sources[0x5d]	63108	1			T24	5		T25	7		T26	1
valid_sources[0x5e]	57746	1			T22	6		T24	6		T25	7
valid_sources[0x5f]	59640	1			T22	3		T24	4		T25	4
valid_sources[0x60]	56503	1			T22	15		T24	5		T25	9
valid_sources[0x61]	56717	1			T22	3		T24	2		T25	7
valid_sources[0x62]	60057	1			T24	2		T25	4		T27	2
valid_sources[0x63]	60087	1			T24	4		T25	5		T27	5
valid_sources[0x64]	311061	1			T24	4		T25	1		T26	1
valid_sources[0x65]	58430	1			T22	23		T24	3		T25	5
valid_sources[0x66]	58105	1			T21	1		T22	1		T24	3
valid_sources[0x67]	63125	1			T21	1		T24	3		T25	8
valid_sources[0x68]	58009	1			T21	1		T24	4		T25	3
valid_sources[0x69]	68367	1			T21	1		T22	1		T24	2
valid_sources[0x6a]	60175	1			T24	3		T25	6		T27	2
valid_sources[0x6b]	58001	1			T22	15		T24	3		T25	7
valid_sources[0x6c]	59035	1			T25	6		T26	1		T1	291
valid_sources[0x6d]	168023	1			T21	1		T24	3		T25	2
valid_sources[0x6e]	59012	1			T21	1		T22	17		T24	9
valid_sources[0x6f]	56796	1			T22	1		T24	4		T25	7
valid_sources[0x70]	54805	1			T22	7		T24	3		T25	6
valid_sources[0x71]	60254	1			T24	6		T25	3		T27	2
valid_sources[0x72]	57652	1			T22	1		T24	7		T25	3
valid_sources[0x73]	60123	1			T22	1		T24	4		T25	6
valid_sources[0x74]	95144	1			T24	2		T25	12		T26	5
valid_sources[0x75]	59176	1			T23	23		T24	3		T25	4
valid_sources[0x76]	58516	1			T21	1		T22	15		T23	41
valid_sources[0x77]	60912	1			T22	17		T24	4		T25	1
valid_sources[0x78]	60446	1			T22	5		T25	5		T27	2
valid_sources[0x79]	64603	1			T24	5		T25	7		T27	5
valid_sources[0x7a]	58951	1			T21	1		T24	7		T25	7
valid_sources[0x7b]	61857	1			T24	1		T25	4		T27	3
valid_sources[0x7c]	60638	1			T22	19		T24	2		T25	10
valid_sources[0x7d]	63215	1			T21	1		T25	4		T27	2
valid_sources[0x7e]	58533	1			T22	1		T24	8		T25	4
valid_sources[0x7f]	58889	1			T21	1		T22	15		T24	1
valid_sources[0x80]	62887	1			T21	1		T24	6		T25	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3929189

1

T21

17

T22

677

T23

73

values[0x0]

all_enables

biggest_size

5004373

1

T21

42

T22

111

T23

53

values[0x1]

all_enables

biggest_size

5005729

1

T21

26

T22

106

T23

74