Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	129627978	0	0	0
ctrl_en_input_filter_rd_A	129627978	67057	0	0
intr_ctrl_en_falling_rd_A	129627978	67640	0	0
intr_ctrl_en_lvlhigh_rd_A	129627978	67284	0	0
intr_ctrl_en_lvllow_rd_A	129627978	67659	0	0
intr_ctrl_en_rising_rd_A	129627978	67885	0	0
intr_enable_rd_A	129627978	68790	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129627978	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129627978	67057	0	0
T1	996915	3163	0	0
T2	341712	1309	0	0
T3	0	1219	0	0
T4	0	2376	0	0
T5	0	3934	0	0
T6	0	11	0	0
T7	0	11	0	0
T8	0	4460	0	0
T9	0	3331	0	0
T10	0	92	0	0
T11	6051	0	0	0
T12	33552	0	0	0
T13	6148	0	0	0
T14	2546	0	0	0
T15	1229	0	0	0
T16	2393	0	0	0
T17	3888	0	0	0
T18	6406	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129627978	67640	0	0
T1	996915	3463	0	0
T2	341712	1235	0	0
T3	0	1182	0	0
T4	0	2372	0	0
T5	0	3960	0	0
T6	0	8	0	0
T8	0	4475	0	0
T9	0	3248	0	0
T10	0	74	0	0
T11	6051	0	0	0
T12	33552	0	0	0
T13	6148	0	0	0
T14	2546	0	0	0
T15	1229	0	0	0
T16	2393	0	0	0
T17	3888	0	0	0
T18	6406	0	0	0
T19	0	100	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129627978	67284	0	0
T1	996915	3059	0	0
T2	341712	1310	0	0
T3	0	1089	0	0
T4	0	2346	0	0
T5	0	4046	0	0
T6	0	11	0	0
T8	0	4497	0	0
T9	0	3284	0	0
T10	0	79	0	0
T11	6051	0	0	0
T12	33552	0	0	0
T13	6148	0	0	0
T14	2546	0	0	0
T15	1229	0	0	0
T16	2393	0	0	0
T17	3888	0	0	0
T18	6406	0	0	0
T19	0	122	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129627978	67659	0	0
T1	996915	3048	0	0
T2	341712	1241	0	0
T3	0	1200	0	0
T4	0	2208	0	0
T5	0	3685	0	0
T6	0	3	0	0
T8	0	4950	0	0
T9	0	3194	0	0
T10	0	74	0	0
T11	6051	0	0	0
T12	33552	0	0	0
T13	6148	0	0	0
T14	2546	0	0	0
T15	1229	0	0	0
T16	2393	0	0	0
T17	3888	0	0	0
T18	6406	0	0	0
T19	0	100	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129627978	67885	0	0
T1	996915	3189	0	0
T2	341712	1318	0	0
T3	0	1207	0	0
T4	0	2387	0	0
T5	0	3918	0	0
T6	0	12	0	0
T8	0	4550	0	0
T9	0	3395	0	0
T10	0	132	0	0
T11	6051	0	0	0
T12	33552	0	0	0
T13	6148	0	0	0
T14	2546	0	0	0
T15	1229	0	0	0
T16	2393	0	0	0
T17	3888	0	0	0
T18	6406	0	0	0
T20	0	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129627978	68790	0	0
T1	996915	3495	0	0
T2	341712	1488	0	0
T3	0	1072	0	0
T4	0	2447	0	0
T5	0	3771	0	0
T8	0	4364	0	0
T9	0	3598	0	0
T10	0	108	0	0
T11	6051	0	0	0
T12	33552	0	0	0
T13	6148	0	0	0
T14	2546	0	0	0
T15	1229	0	0	0
T16	2393	0	0	0
T17	3888	0	0	0
T18	6406	0	0	0
T19	0	64	0	0
T20	0	2	0	0